阅读说明：本技术 开关电路的驱动电路 (Drive circuit of switch circuit ) 是由 蘭明文 于 2019-06-26 设计创作，主要内容包括：一种开关驱动电路,所述开关驱动电路对相互并联连接的多个开关进行驱动,所述开关驱动电路具有：充电单元,所述充电单元允许充电电流流到所述开关的栅极；断开开关,所述断开开关连接在所述开关的栅极和接地之间；检测单元,所述检测单元对所述开关的栅极的充电状态是否处于预定状态进行检测；以及转换单元,所述转换单元在所述充电单元允许充电电流流到栅极时,改变断开开关的状态。所述转换单元在检测单元未检测到栅极的充电状态处于预定状态时,将断开开关的状态变为接通,而在检测单元检测到栅极的充电状态处于预定状态时,将断开开关的状态变为断开。(A switch drive circuit that drives a plurality of switches connected in parallel with each other, the switch drive circuit comprising: a charging unit allowing a charging current to flow to a gate of the switch; a disconnect switch connected between a gate of the switch and ground; a detection unit that detects whether a charging state of a gate of the switch is in a predetermined state; and a switching unit that changes a state of the disconnection switch when the charging unit allows the charging current to flow to the gate. The switching unit changes the state of the off switch to on when the detecting unit does not detect that the charged state of the gate is in the predetermined state, and changes the state of the off switch to off when the detecting unit detects that the charged state of the gate is in the predetermined state.)

1. A switch drive circuit that drives a plurality of switches connected in parallel with each other, the switch drive circuit comprising:

a charging unit, each of which is provided for each of the plurality of switches, allowing a charging current to flow to a gate of each switch;

a plurality of switches, each of which is provided for each of the plurality of switches, and is connected between the gate of each switch and a ground to which electric charges of the gate are discharged;

a detection unit provided for each of the plurality of switches, each of the detection units detecting whether or not a charging state of the gate of each of the switches is in a predetermined state;

a switching unit that changes a state of each open switch when each charging unit allows a charging current to flow to the gate of each switch,

wherein the content of the first and second substances,

the switching unit is configured to change the state of each of the off switches to on when the respective detection units do not detect that the state of charge of the gate of each switch is in the predetermined state, and to change the state of each of the off switches to off when the respective detection units detect that the state of charge of the gate of each switch is in the predetermined state.

2. The switch driver circuit of claim 1,

the switch drive circuit has a communication unit provided in common for each detection unit, the communication unit transmitting a detection result of the each detection unit,

the communication unit is configured to change an output mode of a signal indicating the detection result when the respective detection units detect that the state of charge of the gate of each switch is in the predetermined state,

the switching unit is configured to change the state of each disconnect switch to off when it is determined that the communication unit changes the output mode of the signal.

3. The switch driver circuit of claim 2,

the switching unit is provided for each of a plurality of the switches,

each of the switching units is configured to turn OFF the OFF switch corresponding to the own switching unit.

4. The switch drive circuit according to any one of claims 1 to 3, wherein the switch drive circuit has a turn-off clamp control unit that turns the turn-off switch on when a drive signal of the switch is an off command.

5. The switch drive circuit according to any one of claims 1 to 3,

the charging unit is configured as a constant current charging unit that allows a constant current to flow to the gate of the switch.

Technical Field

The present invention relates to a driving circuit of a switch.

Background

Conventionally, a drive circuit for driving a switch is known. For example, JP- ｃA-2016-. Specifically, the drive circuit includes drive components designated as drive targets, which are provided for the respective switches. Each driving member drives a switch designated for its own driving object. The drive signal provides an on command or an off command for switching.

Here, the period from when the on command is input to each drive circuit to when the switch is turned on may vary significantly due to the configuration of the drive circuit. In this case, a current imbalance may occur in the switch in which the plurality of switches are first turned on. Current imbalance is a phenomenon in which a relatively large amount of current (bias current) briefly flows through the first switch to be turned on, among other switches. When a current imbalance occurs, the reliability of the switch through which the bias current flows may be reduced.

Disclosure of Invention

The present disclosure has been made in view of the above circumstances, and provides a switch drive circuit capable of suppressing a reduction in switching reliability.

The present disclosure provides a switch driving circuit that drives a plurality of switches connected in parallel to each other.

The switch drive circuit includes: a charging unit, each of which is provided for each of the plurality of switches, allowing a charging current to flow to a gate of each of the switches; disconnecting switches, each provided for each of the plurality of switches, connected between a gate of each switch and a ground through which electric charges of the gate are discharged; a detection unit, each of which is provided for each of the plurality of switches, and detects whether a charging state of a gate of each of the switches is in a predetermined state; and a switching unit that changes a state of each of the disconnection switches when the respective charging unit allows the charging current to flow to the gate of each of the switches. The switching unit is configured to change the state of each off switch to on when the respective detection unit does not detect that the charged state of the gate of each switch is in the predetermined state, and to change the state of each off switch to off when the respective detection unit detects that the charged state of the gate of each switch is in the predetermined state.

According to the present disclosure, a charging unit is provided for each switch so as to change the state of each switch to an on state. Here, depending on the configuration of each charging unit, current imbalance may occur.

In this regard, according to the present disclosure, the disconnection switch and the detection unit are provided for each switch. The switching unit of the present disclosure is configured to change the state of each off switch to on when the respective detection unit does not detect that the charged state of the gate of each switch is in a predetermined state. In this state, since the amount of charge at the gate terminal of each switch is insufficient to turn the switch on, each switch remains off. On the other hand, the switching unit changes the state of the disconnection switch to the disconnected state when all the detection units detect that the charged state of the gate is in the predetermined state. By turning the off switches to the off state, the amount of charge required to change the gates of the switches is sufficient to turn the respective switches to the on state. As a result, it is possible to suppress a change in the switching timing of each switch to be turned on. Therefore, current imbalance can be suppressed, and reduction in switching reliability can be suppressed.

Drawings

In the drawings:

fig. 1 is an overall configuration of a control system of a rotary electric machine according to a first embodiment of the invention;

fig. 2 is a diagram showing a configuration of a drive circuit;

FIG. 3 is a timing diagram showing the operation of the drive circuit, wherein the signals are labeled (a) through (j);

fig. 4 is a diagram showing the configuration of a drive circuit of the second embodiment;

fig. 5 is a timing chart showing the operation of the drive circuit according to the second embodiment, in which signals are denoted by (a) to (k);

fig. 6 is a diagram showing a drive circuit according to a third embodiment;

fig. 7 is a diagram showing the configuration of a drive circuit according to another embodiment.

DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION

(first embodiment)

Hereinafter, with reference to the drawings, a first embodiment of a drive circuit embodying the present disclosure will be described. The drive circuit according to the present embodiment is configured as a control system of the rotary electric machine.

As shown in fig. 1, the control system is provided with a battery 10 as a DC (direct current) power source, an inverter 20 as a power converter, a rotating electrical machine 30, and a control unit 40. The rotating electrical machine 30 is connected to the battery 10 via the inverter 20. Note that the smoothing capacitor 11 is provided between the battery 10 and the inverter 20. As the rotating electric machine 30, a permanent magnet field type synchronous machine can be employed.

The inverter 20 is provided with an upper arm switch and a lower arm switch for a three-phase bit cell. Each of the upper arm switch and the lower arm switch includes a first switch SWA and a second switch SWB connected in parallel. A first end of the smoothing capacitor 11 is connected to the high-side terminals of the first switch SWA and the second switch SWB of the upper arm switch of each phase unit. The high-side terminals of the first switch SWA and the second switch SWB of the lower arm switch of each phase unit are connected to the low-side terminals of the first switch SW and the second switch SWB of the upper arm switch of each phase unit. A second terminal of the smoothing capacitor 11 is connected to the low-side terminals of the first switch SWA and the second switch SWB of the lower arm switch of each phase unit. In each phase unit, a first end of the winding 31 of the rotary electric machine 30 is connected to a connection point between the low-side terminals of the first switch SWA and the second switch SWB of the upper arm switch and the high-side terminals of the first switch SWA and the second switch SWB of the lower arm switch. The second end of the winding 31 of each phase unit is connected to the neutral point.

According to the present embodiment, voltage control type semiconductor switching elements are used as the first switch SWA and the second switch SWB. Specifically, a Si-IGBT (insulated gate bipolar transistor) is employed. Thus, in each of the first switch and the second switch, the high-side terminal is a collector and the low-side terminal is an emitter. For the first switch SWA and the second switch SWB, the first freewheeling diode FDA and the second freewheeling diode FDB are connected in anti-parallel. In addition, according to the present embodiment, as the first switch SWA and the second switch SWB, switches having the same specification are used. Specifically, switches having the same threshold voltage Vth are used.

The control unit 40 controls the first and second switches SWA and SWB of the upper arm switch and the first and second switches SWA and SWB of the lower arm switch to be alternately in an on state in each phase unit. The control amount is, for example, torque. The control unit 40 outputs an on command commanding an on state and an off command commanding an off state as the drive signals SG of the first switch SWA and the second switch SWB to the drive circuit Dr provided separately for the paired first switch SWA and second switch SWB in each arm and each phase unit.

The drive circuit Dr included in the inverter 20 acquires a drive signal SG from the control unit 40, and controls the first switch SWA and the second switch SWB to be on or off states in a synchronous manner based on the acquired drive signal SG.

Next, referring to fig. 2, the driving circuit Dr of the first switch and the second switch will be described.

The driving circuit Dr includes a constant voltage source 41, a first substrate 50, and a second substrate 70. The first substrate 50 and the second substrate 70 are arranged to be separated from each other.

First, the configuration of the first substrate 50 will be described. The drive circuit Dr is provided with a first a charging resistor 51A, a first charging switch 52, and a first B charging resistor 51B. According to the present embodiment, the first charge switch 52 is configured as a P-channel MOSFET. The first charging resistor 51A, the first charging switch 52, and the first B charging resistor 51B are mounted on the first substrate 50.

The constant voltage source 41 is connected to a first terminal of the first a-charging resistor 51A, and the source of the first charging switch 52 is connected to a second terminal of the first a-charging resistor 51A. A first terminal of the first B-charge resistor 51B is connected to the drain of the first charge switch 52. The first a terminal T1A of the first substrate 50 is connected to the second end of the first B charging resistor 51B. The gate of the first switch SWA is connected to the first a terminal T1A.

The drive circuit Dr is provided with a first discharge resistor 53, a first discharge switch 54, and a first disconnection switch 55. The first discharge switch 54 and the first disconnection switch 55 are configured as N-channel MOSFETs. The first discharge resistor 53, the first discharge switch 54, and the first disconnection switch 55 are mounted on the first substrate 50.

A first end of the first discharge resistor 53 and a drain of the first disconnection switch 55 are connected to the first a terminal T1A. The drain of the first discharge switch 54 is connected to the first discharge switch 54. An emitter of the first switch SWA as a ground is connected to each source of the first discharge switch 54 and the first disconnection switch 55.

The driving circuit Dr includes a first a adjusting resistor 56A, a first B adjusting resistor 56B, a first changeover switch 57, a first constant current source 58, a first operational amplifier (op-amp)59, a first comparator 60, a first and circuit 61, and a first driving unit 62. According to the present embodiment, the first a adjusting resistor 56A, the first B adjusting resistor 56B, the first changeover switch 57, the first constant current source 58, the first operational amplifier 59, the first comparator 60, the first and circuit 61, and the first driving unit 62 are mounted on the first substrate 50.

The constant voltage source 41 is connected to a first terminal of a first a adjusting resistor 56A, and a first terminal of a first B adjusting resistor 56B is connected to a second terminal of the first a adjusting resistor 56A. The emitter of the first switch SWA is connected to the second terminal of the first B adjustment resistor 56B via the first changeover switch 57 and the first constant current source 58.

A second end of the first a resistor 51A is connected to an inverting input terminal of the first operational amplifier 59, and a second end of the first B adjusting resistor 56B is connected to a non-inverting input terminal of the first operational amplifier 59. The gate of the first charge switch 52 is connected to the output terminal of the first operational amplifier 59. According to the present embodiment, the first a charging resistor 51A, the first charging switch 52, the first a adjusting resistor 56A, the first B adjusting resistor 56B, the first changeover switch 57, and the first constant current source 58 correspond to a constant current charging unit corresponding to the first switch SWA.

The first driving unit 62 acquires the driving signal SG from the control unit 40 via the first B-terminal T1B of the first substrate 50. The first driving unit 62 controls the first charge switch 52, the first discharge switch 54, the first off switch 55, and the first changeover switch 57 to be turned on and off based on the acquired driving signal SG. The functions of the first drive unit 62 may be realized by software stored in a substantially tangible recording medium, a computer or hardware executing the software, or a combination thereof.

A second end of the first charging resistor 51A is connected to the inverting input terminal of the first comparator 60, and a connection point between the first a adjustment resistor 56A and the first B adjustment resistor 56B is connected to the non-inverting input terminal of the first comparator 60. The first C terminal T1C of the first substrate 50 is connected to the output terminal of the first comparator 60. According to the present embodiment, the first comparator 60 corresponds to a detection unit for the first switch SWA.

The first and circuit 61 receives a command signal for the first changeover switch 57 output by the first drive circuit 62 and a logical inversion signal of the output signal of the first comparator 60. The gate of the first disconnection switch 55 is connected to the output terminal of the first and circuit 61.

Subsequently, the configuration of the second substrate 70 will be described. The second substrate 70 has the same configuration as the first substrate 50. Therefore, a detailed description of the configuration of the second substrate 70 will be appropriately omitted.

The drive circuit Dr is provided with a second a charging resistor 71A, a first charging switch 72, and a second B charging resistor 71B. According to the present embodiment, the second charge switch 72 is configured as a P-channel MOSFET. The second charging resistor 71A, the second charging switch 72, and the second B charging resistor 71B are mounted on the second substrate 70.

A first terminal of the second B-charge resistor 71B is connected to a drain of the second switch 72. The second a terminal T2A of the second substrate 70 is connected to a second end of the second B charging resistor 71B. The gate of the second switch SWB is connected to the second a terminal T2A.

The driving circuit Dr is provided with a second discharge resistor 73, a second discharge switch 74, a second disconnection switch 75, a second a adjustment resistor 76A, a second B adjustment resistor 76B, a second changeover switch 77, a second constant current source 78, a second operational amplifier 79, a second comparator 80, a second and circuit 81, and a second driving circuit 92, which are mounted on the second substrate 70. According to the present embodiment, the second discharge switch 74 and the second disconnection switch 75 are configured as N-channel MOSFETs. An emitter of the second switch SWB as a ground is connected to each source of the second discharge switch 74 and the second disconnection switch 75.

The second driving unit 82 acquires a driving signal SG that is a common signal of the driving signals SG input to the first B-terminal T1B via the second B-terminal T2B of the second substrate 70. The second driving unit 82 controls the second charge switch 72, the second discharge switch 74, the second off switch 75, and the second changeover switch 77 to be turned on and off based on the acquired driving signal SG.

The second C terminal T2C of the second substrate 70 is connected to the output terminal of the second comparator 80. The second and circuit 81 receives a command signal for the second changeover switch 77 output from the second drive circuit 82 and a logic inversion signal of the output signal of the second comparator 80. The gate of the second disconnection switch 75 is connected to the output terminal of the second and circuit 81.

The drive circuit Dr is provided with a second constant voltage source 43, a resistor 42, and a communication line L. The second constant voltage source 43 is connected to a first end of the resistance 42, and the first C terminal T1C and the second C terminal T2C are connected to a second end of the resistance 42 via the communication line L. Hereinafter, the voltage signal on the second end side of the resistance 42 is referred to as a communication signal COM.

According to the present embodiment, the second charging resistor 71A, the second charging switch 72, the second a adjustment resistor 76A, the second changeover switch 77, and the second constant current source 78 correspond to a constant current charging unit for the second switch SWB. The first and circuit 61 corresponds to a switching unit for the first switch SWA, and the second and circuit 81 corresponds to a switching unit for the second switch SWB.

According to the present embodiment, the resistance values of the first a adjustment resistor 56A and the second a adjustment resistor 76A are set to the same value, and the resistance values of the first B adjustment resistor 56B and the second B adjustment resistor 76B are set to the same value. Further, the resistance values of the first B charging resistor 51B and the second B charging resistor 71B are set to the same value.

Subsequently, referring to fig. 3, an operation mode of the drive circuit Dr will be described. Fig. 3 (a) shows changes in the drive signal SG, fig. 3 (b) and (f) show changes in the drive states of the first switch SWA and the second switch SWB, fig. 3 (c) and (g) show changes in the drive states of the first discharge switch 54 and the second discharge switch 74, and fig. 3 (d) and (h) show changes in the drive states of the first disconnection switch 55 and the second disconnection switch 75. Fig. 3 (e) and (i) show changes in the determination results of the first comparator 60 and the second comparator 80, and fig. 3 (j) shows changes in the communication signal COM.

At time t1, the first drive unit 62 determines that the acquired drive signal SG is an on command, and outputs an on command having a logic H to the first changeover switch 57 to change the state of the first changeover switch 57 to on and change the state of the first discharge switch 54 to off. Further, the gate voltage of the first charging switch 52 is adjusted so that the voltage difference between the second end side of the first charging resistor 51A and the emitter of the first switch SWA and the voltage difference between the second end side of the first B adjusting resistor 56B and the emitter of the first switch SWA are the same. As a result, a constant current starts to flow to the gate of the first switch SWA.

Also at time t1, the second driving unit 82 determines that the acquired driving signal SG is an on command, outputs an on command having a logic H to the second changeover switch 77 to change the state of the second changeover switch 77 to on, and changes the state of the second discharging switch 74 to off. Accordingly, the gate voltage of the second charging switch 72 is adjusted so that the voltage difference between the second end side of the second a charging resistor 71A and the emitter of the second switch SWB and the voltage difference between the second end side of the second B adjusting resistor 76B and the emitter of the second switch SWB are the same. As a result, a constant current starts to flow to the gate of the second switch SWB.

Here, since the response time of the first operational amplifier 59 and the response time of the second operational amplifier 79 are different, the timing at which the constant current starts to flow through the first a-charging resistor 51A is earlier than the timing at which the constant current starts to flow through the second a-charging resistor 71A. As a result, as shown in (e) of fig. 3, at time t2, it can be determined that the signal voltage at the non-inverting input terminal of the first comparator 60 is greater than the signal voltage at the inverting input terminal of the first comparator 60. This determination timing is set to a time when the constant current flowing through the first a-charge resistor 51A reaches a predetermined current in which a predetermined ratio (for example, 50% or more, specifically 80%) is multiplied by the target current Itgt. This timing is set by adjusting each resistance value of the first a adjustment resistor 56A and the first B adjustment resistor 56B.

However, at time t2, the voltage at the non-inverting input terminal of the second comparator 80 is determined to be not greater than the voltage at the inverting input terminal of the second comparator 80. Therefore, the logic of the output signal from the second comparator 80 becomes L, and the logic of the communication signal COM is held at L. In other words, the output pattern of the communication signal COM is not changed. As a result, the first off switch 55 and the second off switch 75 are maintained in the on state.

However, at time t3, the voltage at the non-inverting input terminal of the second comparator 80 is determined to be greater than the voltage at the inverting input terminal of the second comparator 80. This determination timing is defined as a time when the constant current flowing through the second a charging resistor 71A becomes the predetermined current described above. Therefore, the logic of the communication signal COM becomes H. In other words, the output pattern of the communication signal COM changes. As a result, the logics of the two output signals of the first and circuit 61 and the second and circuit 81 become logic L, and the first disconnection switch 55 and the second disconnection switch 75 become the disconnected state.

When the first and second disconnection switches 55 and 75 become the off state, the gate voltages of the first and second switches SWA and SWB start to increase. Thus, the gate voltages of the first switch SWA and the second switch SWB exceed the threshold voltage Vth, and the first switch SWA and the second switch SWB are synchronized to the on state.

At time t4, the first drive unit 62 and the second drive unit 82 determine that the acquired drive signal SG is the off command. In this case, the first and second charge switches 52 and 72 and the first and second changeover switches 57 and 77 become off-states, and the first and second discharge switches 54 and 74 become on-states. Further, the discharge current is discharged from the gates of the first switch SWA and the second switch SWB, and the gate voltages of the first switch SWA and the second switch SWB become less than the threshold voltage Vth. As a result, the first switch and the second switch become the off state. In addition, since the logic L signal is applied to the gates of the first and second transfer switches 57 and 77, the first and second disconnection switches 55 and 75 become the off state.

According to the present embodiment described above, the timings at which the first switch SWA and the second switch SWB are changed to the on-state may be the same timing, whereby the occurrence of current imbalance may be prevented. As a result, the reliability of the first switch SWA and the second switch SWB can be prevented from being lowered.

According to the present embodiment, the communication line L, the resistance 42, and the second constant voltage source 43 are commonly provided as a communication unit for the first comparator 60 and the second comparator 80. Therefore, each of the first substrate 50 side including the first comparator 60 and the second substrate 70 side including the second comparator 80 can monitor the state of the charging current supplied to the gate. In particular, according to the present embodiment, the respective and circuits 61 and 81 input output signals from the comparators 60 and 80 via the common communication line L. Therefore, in addition to the configuration in which the state of the charging current is monitored by the two comparators, the configuration in which the off switch is changed to the on state based on the monitoring result can be easily realized.

(second embodiment)

Hereinafter, the second embodiment will be described with reference to the drawings. In the second embodiment, a configuration different from that of the first embodiment will be mainly described. According to the present embodiment, the first disconnection switch 55 and the second disconnection switch 75 possess a disconnection clamping function.

Fig. 4 shows the configuration of the drive circuit Dr according to the present embodiment. In fig. 4, the same reference numerals are applied to the same configurations as those shown in fig. 2 for convenience.

The first substrate 50 further includes a first judgment comparator 63, a first judgment and circuit 64, and a first or circuit 65.

The first a terminal T1A is connected to the inverting input terminal of the first judgment comparator 63. The reference voltage VREF is connected to the non-inverting input terminal of the first judgment comparator 63. The reference voltage VREF is set to be higher than 0 and smaller than the threshold voltage Vth described above.

The first determination and circuit 64 inputs a logic inversion signal with respect to the command signal of the first changeover switch 57 output by the first drive unit 62 and an output signal of the first determination comparator 63. The first or circuit 65 inputs each of the output signals from the first and circuit 61 and the first and circuit 64. The gate of the first disconnection switch 55 inputs the output signal of the first or circuit.

The second substrate 70 is mounted with a second judgment comparator 83, a second judgment and circuit 84, and a second or circuit 85.

The second a terminal T2A is connected to the inverting input terminal of the second judgment comparator 83. The non-inverting input terminal of the second judgment comparator 83 is input with the reference voltage VREF described above.

The second determination and circuit 84 inputs the logic inversion signal with respect to the command signal of the second changeover switch 77 output from the second drive circuit 82 and the output signal of the second determination comparator 83. The second or circuit 85 inputs output signals of the second and circuit 81 and the second and circuit 84. An output signal of the second or circuit 85 is input to the gate of the second disconnection switch 75.

According to the present embodiment, the first and circuit 61 and the first or circuit 65 correspond to a switching unit of the first switch SWA, and the second and circuit 81 and the second or circuit 85 correspond to a switching unit of the second switch SWB. The first judgment comparator 63, the first judgment and circuit 64, and the first or circuit 65 correspond to an off clamp control unit for the first switch SWA, and the second judgment comparator 83, the second judgment and circuit 84, and the second or circuit 85 correspond to an off clamp control unit for the second switch SWB.

Subsequently, with reference to fig. 5, it will be described that the first disconnection switch 55 and the second disconnection switch 75 function as disconnection clamp switches. Fig. 5 (a) to 5 (j) correspond to fig. 3 (a) to 3 (j) described above. Fig. 5 (k) shows changes in the output signals of the first judgment comparator 63 and the second judgment comparator 83. Further, the times t1 to t4 shown in fig. 5 correspond to the above-described times t1 to t4 shown in fig. 3.

After time t4, the gate voltages at the first switch SWA and the second switch SWB decrease. Then at time t5, the gate voltage decreases below the reference voltage VREF, whereby the logic states of the output signals of the first and second determination comparators 63 and 83 change from L to H. Therefore, the logic states of the output signals of the first and second and circuits 64 and 84 become H, and the logic states of the output signals of the first and second or circuits 65 and 85 become H. As a result, during a period in which the drive signal SG indicates the off command, the first off switch 55 and the second off switch 75 become on-state, thereby functioning as off clamp switches. Therefore, a self-turn-on phenomenon in which the first switch SWA and the second switch SWB, which should maintain the off-state, are turned on erroneously can be avoided.

Thereafter, at time t6 when the logic state of the communication signal COM becomes H, the first disconnection switch 55 and the second disconnection switch 75 become the disconnected state. Accordingly, the first switch SWA and the second switch SWB become on-states.

According to the present embodiment as described above, the first and second disconnection switches 55 and 75 can function as disconnection clamp switches by adding such simple configurations as the first and second judgment comparators 63 and 83, the first and second judgment and circuits 64 and 84, and the first and second or circuits 65 and 85.

(third embodiment)

Hereinafter, the third embodiment will be described with reference to the drawings. In the third embodiment, a configuration different from that of the first embodiment will be mainly described. According to the present embodiment, a constant voltage control is used to change the states of the first switch SWA and the second switch SWB instead of using a constant current control.

Fig. 6 shows a drive circuit Dr according to the present embodiment. In fig. 6, the same reference numerals are applied to the same configurations as those shown in fig. 2 for convenience.

First, the configuration of the first substrate 50 will be described. A constant voltage source 41 is connected to the source of the first charge switch 52. The first a terminal T1A is connected to the inverting input terminal of the first comparator 60. A positive terminal of a first power supply 66 mounted on the first substrate 50 is connected to the non-inverting input terminal of the first comparator 60. The emitter of the first switch SWA is connected to the negative terminal of the first power supply 66.

Subsequently, the configuration of the second substrate 70 will be described. The constant voltage source 41 is connected to the source of the second charge switch 72. The second a terminal T2A is connected to the inverting input terminal of the second comparator 80. The positive terminal of the second power supply 86 mounted on the second substrate 70 is connected to the non-inverting input terminal of the second comparator 80. The emitter of the second switch SWB is connected to the negative terminal of the second power supply 86.

According to the present embodiment, the first charge switch 52 and the first B charge resistor 51B correspond to a constant voltage charging unit for the first switch SWA, and the second charge switch 72 and the second B charge resistor 71B correspond to a constant voltage charging unit for the second switch SWB. According to the present embodiment, the output voltages of the first power supply 66 and the second power supply 86 are referred to as a predetermined voltage VS. The predetermined voltage VS is set to be greater than 0 and less than the threshold voltage described above.

According to the present embodiment as described above, when both gate voltages of the first switch SWA and the second switch SWB exceed the predetermined voltage VS in a state where the drive signal SG indicates the on command, the first off switch 55 and the second off switch 75 become the off state. Accordingly, the first switch SWA and the second switch SWB are synchronized to the on state, and the occurrence of current imbalance can be prevented.

(other embodiments)

The above-described embodiments may be modified in the following manner.

The voltage applied to the inverting input terminals of the first and second comparators 60 and 80 may be a divided voltage of the gate voltages of the first and second switches SWA and SWB. In this case, since the predetermined voltage VS corresponds to the divided voltage value, the predetermined voltage VS may be set to be smaller than that set in the third embodiment.

The configuration in which the first disconnection switch 55 and the second disconnection switch 75 function as disconnection clamp switches may be applied to the configuration of the third embodiment.

As the configuration of the communication unit, for example, a configuration as shown in fig. 7 may be utilized. In fig. 7, the same reference numerals are applied to the same configurations as those shown in fig. 2 for convenience.

The emitters of the first switch SWA and the second switch SWB are connected to a first terminal of a resistor 42. Further, for each of the first comparator 60 and the second comparator 80, the input signal at the non-inverting input terminal and the input signal at the inverting input terminal are exchanged, compared to the signals shown in fig. 2. The first and circuit 61 and the second and circuit 81 input the output signals of the first comparator 60 and the second comparator 80 instead of the logical inversion signals of the output signals of the first comparator 60 and the second comparator 80. In this case, when each charging current flowing through the respective first and second a-charging resistors 51A and 71A exceeds a predetermined current, the logic state of the output signals of the first and second comparators 60 and 80 changes from H to L, and the first and second disconnection switches 55 and 75 may be in the off state.

Instead of being mounted on separate two substrates, the components of the driving circuit Dr may be mounted on a single common substrate.

The switches constituting the inverter are not limited to IGBTs, and for example, N-channel MOSFETs of SiC may be used. In this case, the high-side terminal of the switch is the drain and the low-side terminal is the source.

The ground is not limited to the emitters of the switch SWA and the switch SWB. For example, a negative voltage source may be used. The negative voltage source outputs a negative voltage lower than the voltage of the emitter.

The number of parallel connections of the switches constituting the inverter is not limited to 2, but 3 or more connections may be used. For example, the number of parallel connections of the switches may be changed according to the amount of output current of the inverter. In this case, when the driver circuits are provided in an amount appropriate to the number of parallel connections, the manufacturing cost and the development man-hours increase. In this respect, since the above-described configuration in which the change timing at which the respective switches become on-states is the same is utilized, even if the number of parallel connections of the switches is changed at the stage of design, the change timing at which the respective switches become on-states can be made the same while reducing the manufacturing cost and the number of development man-hours.

The power converter is not limited to an inverter, and is a DC-DC converter that outputs a converted input voltage. Specifically, the converter includes at least one of a step-down function of stepping down the input voltage and a step-up function of outputting the stepped-up input voltage.