阅读说明：本技术 Gm增强型差分压控振荡器（VCO） (Gm enhanced differential Voltage Controlled Oscillator (VCO) ) 是由 殷毅 于 2019-06-24 设计创作，主要内容包括：本申请涉及一种差分考毕兹压控振荡器(VCO)电路,所述差分考毕兹VCO电路包括一对晶体管和一对耦合器,所述一对晶体管具有通过共同偏置电压偏置的控制端,所述一对耦合器被布置成交叉耦合所述晶体管的集电极/漏极和所述差分晶体管的基极/栅极。所述一对耦合器具有耦合因子k<Sub>c</Sub>,所述耦合因子用于增强所述晶体管对的跨导,因此可以用于降低功耗并且最小化相位噪声。(The present application relates to a differential colpitts Voltage Controlled Oscillator (VCO) circuit comprising a pair of transistors having control terminals biased by a common bias voltage and a pair of couplers arranged to cross-couple collectors/drains of the transistors and bases/gates of the differential transistors. The pair of couplers have a coupling factor k c The coupling factor is used to enhance the transconductance of the transistor pair and thus may be used to reduce power consumption and minimize phase noise.)

1. A differential voltage controlled oscillator, VCO, circuit comprising:

a pair of differential transistors (130, 130 ', 135'), the pair of differential transistors (130, 130 ', 135') having a common bias voltage (V)_bias) A biased control terminal; and

a pair of couplers (180, 180 ', 185'), the pair of couplers (180, 180 ', 185') being arranged to cross-couple the first current terminal and the control terminal of the pair of transistors (130, 130 ', 135'), wherein the pair of couplers (180, 180 ', 185') has a coupling factor (k_c)。

2. The circuit of claim 1,

each coupler of the pair of couplers (180, 180 ', 185') comprising a main path and a coupling path,

a first coupler (180, 180 ') of the pair of couplers (180, 180 ', 185 ') is coupled to one transistor (130, 130 ') of the pair of transistors (130, 130 ', 135 ') through the main path and to the other transistor (135, 135 ') of the pair of transistors (130, 130 ', 135 ') through the coupling path,

a second coupler (180, 180 ') of the pair of couplers (180, 180 ', 185 ') is coupled to the other transistor (135, 135 ') of the pair of transistors (130, 130 ', 135 ') through the main path and to the one transistor (130, 130 ') of the pair of transistors (130, 130 ', 135 ') through the coupling path.

3. The circuit of claim 2,

the coupling paths of the pair of couplers (180, 180 ', 185') are connected to each other by an interconnect,

the coupling paths of the pair of couplers (180, 180 ', 185') form a series circuit coupling the control terminals of the pair of transistors (130, 130 ', 135').

4. The circuit of claim 3,

the common bias voltage (V)_bias) Is fed into the interconnect.

5. The circuit of any preceding claim, further comprising:

a bias voltage source (160), the bias voltage source (160) being arranged to supply the common bias voltage (V) through a bias resistor (165)_bias)。

6. The circuit of any preceding claim,

the pair of couplers is one of a pair of coupling transformers and a pair of transmission line based couplers.

7. The circuit of any preceding claim, further comprising:

a differential transformer (150), the differential transformer (150) having a primary coil (155) and a secondary coil (156), the primary coil (155) being inserted between the first current terminals of the transistors (130, 130 ', 135'), the secondary coil (156) being coupled in a closed series circuit with two varactors (220, 225), the two varactors (220, 225) being arranged to pass a first common tuning voltage (Vtune)_tune1) Tuning is carried out; and

a series circuit comprising a second transistor coupled in series to the transistor (130, 130 ', 135')Two further varactors (170, 175) of the two current terminals, wherein the two further varactors (170, 175) are arranged to pass a second common tuning voltage (V;)_tune2) The tuning is performed.

8. The circuit of any preceding claim, further comprising:

a feedback capacitor (120, 125), each of the feedback capacitors (120, 125) coupled between the first and second current terminals of a respective one of the transistors (130, 130 ', 135').

9. The circuit of any preceding claim, further comprising:

a bias current source (190), the bias current source (190) coupled between the second current terminal of the pair of transistors (130, 130 ', 135') and a reference potential.

10. The circuit of any preceding claim,

the circuit is a colpitts differential voltage controller oscillator (100).

Technical Field

The present disclosure generally relates to a differential Voltage Controlled (VCO) oscillator. In particular, the present disclosure relates to a Gm enhanced (transconductance enhanced) differential VCO with a Colpitts (Colpitts) configuration.

Background

In the past few years, Automotive Driving Assistance Systems (ADAS), high-throughput short-range wireless communications, and non-destructive scanning systems for security and security have driven the development of millimeter-wave silicon technology. For example, ADAS utilizes Ultra Wideband (UWB)/Frequency Modulated Continuous Wave (FMCW) radar circuits in the W-band (75GHz to 110 GHz). A complete ADAS device typically includes a 77-81GHz proximity radar (SRR) UWB sensor for parking assistance, blind spot detection and collision mitigation assistance and a 76-77GHz remote radar (LRR) sensor with FMCW modulation for forward monitoring and Adaptive Cruise Control (ACC). Currently, IEEE (802.15.TG3c) is studying the 57GHz to 64GHz band for Wireless Personal Area Network (WPAN) communication with data rates of 1Gbps and above. Also, research is being conducted on wireless communication in the terahertz region, specifically, in the frequency range of 300GHz to 3 THz. In addition, a terahertz time-domain spectroscopy technique using a pulse wave is applied to security inspection.

The frequency synthesizer employed in such systems should provide a clock reference with a wide frequency range, however, the spectral purity and large output power of the Power Amplifier (PA) are also desirable. In Voltage Controlled Oscillator (VCO) based frequency synthesizers, the power and in-band noise performance depends on the VCO circuitry, which represents a key block of the frequency synthesizer with a high frequency divider (i.e., prescaler). Despite past developments, it remains challenging to implement a millimeter wave VCO with low Phase Noise (PN) and wide Tuning Range (TR) in combination with a high output power oscillating signal.

It has been shown that prior art VCOs with the colpitts configuration partially meet the above requirements but the start-up characteristics are significantly worse, which means that high power consumption must be accepted to ensure reliable start-up.

Disclosure of Invention

According to a first aspect of the present invention there is provided a differential voltage controlled oscillator, VCO, circuit comprising:

a pair of differential transistors having control terminals biased by a common bias voltage; and

a pair of couplers arranged to cross-couple the first current terminal and the control terminal of the pair of transistors, wherein the pair of couplers have a coupling factor.

In one or more embodiments, each coupler of the pair of couplers includes a main path and a coupled path,

a first coupler of the pair of couplers is coupled to one transistor of the pair of transistors through the main path and to the other transistor of the pair of transistors through the coupling path,

the second coupler of the pair of couplers is coupled to the other transistor of the pair of transistors through the main path and to the one transistor of the pair of transistors through the coupling path.

In one or more embodiments, the coupling paths of the pair of couplers are connected to each other by an interconnect,

the coupling paths of the pair of couplers form a series circuit coupling the control terminals of the pair of transistors.

In one or more embodiments, the common bias voltage is fed into the interconnect.

In one or more embodiments, the circuit further comprises:

a bias voltage source arranged to supply the common bias voltage through a bias resistor.

In one or more embodiments, the pair of couplers is one of a pair of coupling transformers and a pair of transmission line based couplers.

In one or more embodiments, the circuit further comprises:

a differential transformer having a primary coil and a secondary coil, the primary coil being inserted between the first current terminals of the transistors, the secondary coil being coupled in a closed series circuit having two varactors, the two varactors being arranged to be tuned by a first common tuning voltage; and

a series circuit comprising two further varactors coupled in series to a second current terminal of the transistor, wherein the two further varactors are arranged to be tuned by a second common tuning voltage.

In one or more embodiments, the circuit further comprises:

a feedback capacitor, each of the feedback capacitors coupled between the first and second current terminals of a respective one of the transistors.

In one or more embodiments, the circuit further comprises:

a bias current source coupled between the second current terminals of the pair of transistors and a reference potential.

In one or more embodiments, the circuit is a colpitts differential voltage controller oscillator.

In one or more embodiments, the primary coil has a center tap, the center tap being arranged to receive a supply voltage,

the secondary coil has a center tap coupled to a reference potential.

In one or more embodiments, the transistor is a bipolar transistor, wherein the first current terminal is a collector terminal, the second current terminal is an emitter terminal, and the control terminal is a base terminal.

In one or more embodiments, the transistor is a metal oxide semiconductor, MOS, transistor, wherein the first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal.

In one or more embodiments, the circuit further comprises:

a first tuning voltage source coupled to an interconnection of the two varactors and arranged to supply the first common tuning voltage.

In one or more embodiments, the circuit further comprises:

a second tuning voltage source coupled to an interconnection of the two further varactors and arranged to supply the second common tuning voltage.

These and other aspects of the invention are apparent from and will be elucidated with reference to the embodiments described hereinafter.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present invention and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the pertinent art to make and use the invention.

Fig. 1 schematically shows a circuit diagram for illustrating a configuration of a bipolar transistor based Gm enhanced differential colpitts Voltage Controlled Oscillator (VCO) with a coupling transformer according to an example of the present invention;

fig. 2 schematically shows a circuit diagram for illustrating a configuration of a MOS transistor-based Gm enhanced differential colpitts VCO with a coupling transformer according to another example of the present invention;

fig. 3 schematically shows a circuit diagram for illustrating a configuration of a bipolar transistor-based Gm enhanced differential colpitts Voltage Controlled Oscillator (VCO) having a transmission line based coupler according to an example of the present invention;

fig. 4 schematically shows a circuit diagram for illustrating a configuration of a MOS transistor-based Gm enhanced differential colpitts VCO with a transmission line-based coupler according to another example of the present invention; and is

Fig. 5a to 5d schematically show the layout of an exemplary transmission line based coupler suitable for use in the Gm enhanced differential colpitts VCO specified above according to an example of the present invention.

Detailed Description

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It is to be noted that the same reference numerals are used in the drawings to denote the same or equivalent elements, and the description thereof will not be repeated. The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the invention. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the invention and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

Referring to fig. 1, there is shown a circuit schematic diagram illustrating a configuration of a Gm enhanced differential Voltage Controlled Oscillator (VCO) according to an example of the present invention. The differential VCO 100 is a colpitts VCO and employs a differential VCO having a positive output terminal V _out+110 and a negative output terminal V _out-115 in the form of a differential VCO circuit. It should be noted that in the context of this specification, a differential signal may comprise two components of the same amplitude but opposite phase. The differential signal can be provided through two endsAnd (4) supplying.

The differential VCO includes two active devices, in this case a first transistor 130 and a second transistor 135. Any type of transistor or suitable active device may be used. The properties of the active devices, respectively transistors 130 and 135, may be the same to provide a symmetric active device. Specifically, the two active devices are bipolar transistors 130 and 135; more specifically, the two active devices are bipolar junction transistors 130 and 135. Transistors suitable for high frequencies may be considered for or as active devices, in particular NPN-type transistors. Positive output terminal V _out+110 and a negative output terminal V _out-115 are coupled to the collectors of respective ones of transistors 130 and 135.

In the illustrated configuration, bipolar transistors 130 and 135 form a balanced differential pair of bipolar transistors 130 and 135. Capacitors 120 and 125 are coupled in parallel to the collector-emitter paths of transistors 130 and 135. Capacitor 120 and capacitor 125 form feedback capacitors, each of which is connected to the collector and emitter of a respective one of transistors 130 and 135. Capacitors 120 and 125 provide positive feedback from the emitter to the collector of respective ones of transistors 130 and 135. It is feasible to choose the capacitances of the capacitors 120 and 125 to be equal.

Is biased to be at a supply voltage V_ddCoil 155 of 140 is coupled to the collectors of transistors 130 and 135 such that the collectors of transistors 130 and 135 are coupled to each other through coil 155. The collectors of transistors 130 and 135 are coupled to respective ones of the end taps of coil 155. In one example, the supply voltage V _dd140 to coil 155; in particular, the supply voltage V _dd140 to the center tap of the coil 155. For example, the supply voltage V_ddAnd may be 2.5V or lower or higher (e.g., 3.3V or 5V).

The emitters of transistors 130 and 135 are additionally connected to a common reference ground through varactors 170 and 175, respectively. The capacitance of varactors 170 and 175 may be provided by a tuning voltage source 200 as a tuning voltage V that supplies an interconnected common network of varactors 170 and 175_tune2The tuning is performed. Tuning voltage V_tune2Provided by a dc voltage source or in the form of a current mirror voltage, e.g. provided by a current mirror circuit. It is feasible to choose the capacitances of varactors 170 and 175 to be equal. Varactors 170 and 175 tune to varying tuning voltages V within a suitable tuning voltage range_tune2May have substantially the same capacitance dependence. In the illustrated configuration, varactors 170 and 175 are inserted in series between the emitters of transistors 130 and 135. Capacitive tuning of varactors 170 and 175 by single-ended tuning voltage V_tune2And (5) realizing control.

In a differential VCO, bias current source 190 provides bias current I for transistor 130 and transistor 135, respectively_b. The bias current source 190 may provide a DC bias current I_b. In one example, a bias current source 190 is inserted between the emitters of transistors 130 and 135 and the lowest reference potential, such as ground potential. In one example, the emitters of both transistors 130 and 135 are connected together by an interconnect, with a bias current source 190 interposed between the interconnect and the lowest reference potential.

Coil 155 is the primary (or main) coil 155 of transformer 150, which transformer 150 includes a secondary coil 156 that is inductively coupled to primary coil 155. The secondary coil 156 is connected in series to varactors 220 and 225, the capacitances of which varactors 220 and 225 are connectable by a tuning voltage source 230 to a tuning voltage V provided to a common interconnection of varactors 220 and 225_tune1The tuning is performed. Tuning voltage V_tune1Provided by a dc voltage source or in the form of a current mirror voltage, e.g. provided by a current mirror circuit. Capacitive tuning of varactors 220 and 225 by single-ended tuning voltage V_tune1And (5) realizing control. It is feasible to choose the capacitances of varactors 220 and 225 to be equal. Varactors 220 and 225 may respond to a varying tuning voltage V within a suitable tuning voltage range_tune1Changing the capacitance. In the illustrated configuration, varactors 220 and 225 are connected in series with respective ones of the end taps of secondary coil 156. The center tap of secondary coil 156 is supplied to the lowest reference potential. Specifically, the center tap of secondary coil 156 is set to the lowest reference potential, such as ground, so as to be at a given potentialThe maximum tuning range is obtained within the supply.

The main frequency tuning of the differential VCO is achieved by transformer coupled varactor pairs 220 and 225. The transformer coupled varactor pairs 220 and 225 enable a wide tuning of the oscillator frequency, e.g., in the W-band. For example, transformer coupled varactor pairs 220 and 225 enable tuning of oscillator frequencies in a frequency range that includes the LRR frequency range (76-77GHz) and the SRR frequency range (77-81 GHz). For example, transformer coupled varactor pairs 220 and 225 enable tuning of oscillator frequencies in a frequency range that includes the 57-64GHz band of IEEE 802.15.TG3c WPAN communications. The frequency tuning range of the differential VCO is further extended by the emitter-side arranged varactor pair 170 and 175, which not only enables a wide tuning range for e.g. LRR and SRR applications, but can be used to compensate inter alia for oscillation frequency drifts due to process, supply and temperature variations (PVT).

The base and collector terminals of transistors 130 and 135 are used with a coupling factor k_cCoupling transformers 180 and 185 are cross-coupled. Each of the couplers 180 and 185 includes a primary (or primary) coil 181 and 186, respectively, and a secondary (or coupling) coil 182 and 187, respectively. The primary coils 181 and 186 form a primary (or primary) path, respectively, and the secondary coils 182 and 187 form a coupling (or secondary) path, respectively. Each of the coupling transformers 180 and 185 couples a limited amount of the electromagnetic power of the main signal on the main path into the coupled signal on the coupling path. The limited amount is defined by a coupling factor k_cAnd (4) showing. The main paths of the couplers 180 and 185 are connected in series between respective ones of the collector terminals of the transistors 130 and 135 and respective ones of the end taps of the primary coil 155, respectively. The coupling paths of couplers 180 and 185 are cross-coupled to the base terminals of transistors 130 and 135. The coupler 180 having a main path coupled to the collector terminal of the transistor 130 is coupled to the base terminal of the transistor 135 through a coupling path thereof, and the coupler 185 having a main path coupled to the collector terminal of the transistor 135 is coupled to the base terminal of the transistor 130 through a coupling path thereof. Thus, coupling to the crystal in couplers 180 and 185The coupled signal at the coupled signal side of the respective coupler at the collector terminal of one of the transistors 130 and 135 is cross-coupled to the base terminal of the respective other one of the transistors 130 and 135.

In one example, the common bias voltage V_biasAnd additionally to the base terminals of transistors 130 and 135. For example, bias voltage source 160 is interposed between a lowest reference potential (e.g., ground) and couplers 180 and 185. Specifically, the bias voltage source 160 is interposed between the lowest reference potential and the common interconnection of the coupling paths of the couplers 180 and 185 (e.g., the common interconnection connecting the second end taps of the secondary coils 182 and 187 of the couplers 180 and 185). A bias resistor 165 may be disposed between bias voltage source 160 and the base terminals of transistors 130 and 135. In one example, the coupling paths of couplers 180 and 185 are arranged in a series circuit of base terminals of cross-coupled transistors 130 and 135.

Couplers 180 and 185 arranged to cross-couple the collector and base terminals of transistors 130 and 135 couple the differential signal present at the collector terminals of transistors 130 and 135 to the base terminal of the respective other of transistors 130 and 135, which effectively modifies the effective transconductance by a factor of 1+ a, where a k_c(1+C₁/C_var3) Wherein k is_cIs the coupling factor, C, of the coupler 180₁Is the capacitance of capacitor 120, and C_var3Is the capacitance of the varactor 170. Thus, the start-up behavior of the differential VCO is effectively improved, since less bias current is required. An additional effect of the reduction in bias current is a reduction in channel noise and a reduction in noise contribution from transistor pairs 130 and 135.

Furthermore, by adjusting the coupling factor k_cAn optimal RMS (root mean square) value of an optional charge swing across a current noise source and an effective pulse sensitivity function (ISF) associated with the noise source may be achieved, thereby achieving optimized phase noise.

The small signal admittance with respect to the collector of the transistor is as follows:

wherein g is_mIs the collector transconductance, C, of transistor 130₁Is the capacitance of the capacitor 120, C_var3Is the capacitance, k, of the varactor 170_cIs the coupling factor of coupler 180 and ω is the circular frequency of the differential VCO. It should be noted that it is further assumed that transistors 130 and 135, capacitors 120 and 125, and varactors 170 and 175 have the same properties and specifications. This means that the properties and specifications of the components of the differential VCO are symmetrical with respect to the virtual ground plane.

Factor 1+ k as a contribution of coupler-based cross-coupling_c(1+C₁/C_var3) The amount of negative small signal conductance is increased. Contribution a ═ k_c(1+C₁/C_var3) Can be understood as a Gm enhancer.

With respect to fig. 1, an example of a Gm-enhanced differential VCO is shown and described that includes bipolar transistors 130 and 135 as active devices. In particular, the SiGe bipolar transistors 130 and 135 may provide the desired high frequency characteristics. However, implementation of a Gm enhanced differential VCO should not be understood to be limited to bipolar transistors 130 and 135 as active devices. MOS (metal oxide semiconductor) transistors and in particular NMOS (n-type metal oxide semiconductor) transistors may also be used as active devices.

Referring now to fig. 2, there is shown a circuit schematic diagram illustrating another configuration of a Gm enhanced differential VCO, and in particular, a Gm enhanced differential colpitts VCO, in accordance with an example of the present invention. The active devices, which may be identical in nature to provide symmetric active devices, respectively transistors 130 and 135, are MOS transistors 130 'and 135'; more specifically, the two active devices are NMOS transistors 130 'and 135' in a balanced configuration. The remainder of the circuit substantially corresponds to that described with reference to figure 1. Therefore, the above description basically applies equally to the configuration of fig. 2, provided that technical terms relating to the ends of the bipolar transistors 130 and 135 are converted into technical terms relating to the ends of the MOS transistors 130 'and 135'. Those skilled in the art will immediately understand that the terms "collector", "emitter" and "base" used in the context of a bipolar transistor translate into the corresponding terms "drain", "source" and "gate" of a MOS transistor. Therefore, repetition is omitted.

For illustration, the collector and drain terminals will also be referred to as first current terminals, the emitter and drain terminals will also be referred to as second current terminals, and the base and gate terminals will also be referred to as control terminals.

With respect to fig. 1 and 2, an example of a Gm-enhanced differential VCO is shown and described that includes coupling transformers for the base/gate and collector/drain terminals of cross-coupled transistors 130/130 'and 135/135'. However, implementations of Gm-enhanced differential VCOs should not be understood to be limited to coupling transformers for cross-coupling.

Referring now to fig. 3 and 4, there are shown circuit schematic diagrams illustrating configurations of Gm enhanced differential colpitts VCOs with transmission line based couplers according to further examples of the present invention. Fig. 3 schematically shows an example of a Gm-enhanced differential VCO with bipolar transistors 130 and 135 as active devices, while fig. 4 schematically shows an example of a Gm-enhanced differential VCO with MOS transistors 130 'and 135' as active devices. The description above with respect to fig. 2 with respect to bipolar transistors 130 and 135 and MOS transistors 130 'and 135' applies equally. It should be noted that couplers 180 and 185 will be discussed below, as the remainder of the circuitry substantially corresponds to that described with reference to fig. 1 and 2, respectively.

Similar to fig. 1 and 2, using a coupling factor k_cThe coupled transmission line based couplers 180 'and 185' cross-couple the base/gate terminals and the collector/drain terminals of the transistors 130/130 'and 135/135'.

Each of couplers 180 'and 185' includes a primary (or main) transmission line 181 'and 186', respectively, and a secondary (or coupled) transmission line 182 'and 187', respectively. Primary transmission lines 181 'and 186' form primary (or primary) paths, respectively, and secondary transmission lines 182 'and 187' form coupled (or secondary) paths, respectively. Coupler180 'and 185' each couple a defined amount of electromagnetic power of the main signal on the main path into the coupled signal on the coupling path. The limited amount is defined by a coupling factor k_cAnd (4) showing. The main paths of the couplers 180 'and 185' are connected in series between respective ones of the collector/drain terminals of the transistors 130/130 'and 135/135', respectively, and respective ones of the end taps of the primary coil 155. The coupling paths of couplers 180 'and 185' are cross-coupled to the base/gate terminals of transistors 130/130 'and 135/135'. The coupler 180 'having a main path coupled to the collector/drain terminal of the transistor 130/130' is coupled through its coupling path to the base/gate terminal of the transistor 135/135 ', and the coupler 185' having a main path coupled to the collector/drain terminal of the transistor 135/135 'is coupled through its coupling path to the base/gate terminal of the transistor 130/130'. Thus, the coupled signal on the coupled signal side of the respective one of the couplers 180 'and 185' coupled to the collector/drain terminal of one of the transistors 130/130 'and 135/135' is cross-coupled to the base/gate terminal of the respective other one of the transistors 130/130 'and 135/135'.

In one example, the common bias voltage V_biasAnd additionally to the base/gate terminals of transistors 130/130 'and l 35/135'. For example, bias voltage source 160 is interposed between a lowest reference potential (e.g., ground) and couplers 180 'and 185'. Specifically, the bias voltage source 160 is interposed between the lowest reference potential and the common interconnect network of the coupling paths of the couplers 180 'and 185' (e.g., the common interconnect network connecting the secondary transmission lines 182 'and 187' of the couplers 180 'and 185'). A bias resistor 165 may be disposed between bias voltage source 160 and the base/gate terminals of transistors 130/130 'and 135/135'. In one example, the coupling paths of couplers 180 and 185 are arranged in a series circuit of base/gate terminals of cross-coupled transistors 130/130 'and 135/135'.

Couplers 180 ' and 185 ' arranged to cross-couple the collector/drain terminals and base/gate terminals of transistors 130/130 ' and 135/135 ' provide differential coupling signals to the base/gate terminals of the respective other of transistors 130/130 ' and 135/135Sign (decoupled from the main signal at the collector/drain terminals of transistors 130/130 'and 135/135'). The cross-coupling effectively modifies the effective transconductance by a factor of 1+ a, where a ═ k_c(1+C₁/C_var3)，k_cIs the coupling factor, C, of the coupler 180₁Is the capacitance of capacitor 120, and C_var3Is the capacitance of the varactor 170. Thus, the start-up behavior of the differential VCO is effectively improved, since less bias current is required. An additional effect of the reduction in bias current is a reduction in channel noise and a reduction in noise contribution from the transistor pair 130/130 'and 135/135'.

Referring now to fig. 5a to 5d, there is shown a schematic layout of a transmission line based coupler suitable for use in the Gm enhanced differential colpitts VCO described above according to an example of the present invention.

As shown, for example, in fig. 5a and 5b, couplers 180 'and 185' may be implemented by two top metal strips having a common ground plane. In the example shown in fig. 5a, parts of the metal strips are arranged to overlap. The coupling factor k is, among other things_cDetermined by the size of the overlapping portion of the two top metal strips. Thus, the coupling factor k is adjusted_cThis can be achieved by adjusting the size of the overlapping portion. In a further example shown in fig. 5b, the two metal strips 310 and 315 may be arranged to be coplanar in a common layer above a common ground plane 330 (separated by an insulator 320). The coupling factor k is, among other things_cDetermined by the size and spacing of the two top metal strips. Thus, the coupling factor k is adjusted_cThis can be achieved by adjusting the size and spacing of the metal strips in a coplanar arrangement. The metal strip may be a microstrip.

In another example, hybrid couplers may also be used for cross-coupling. For example, fig. 5c shows a coupled line coupler, and fig. 5d shows a spur line coupler. The coupled line coupler is constituted by, for example, two transmission lines. A spur coupler is for example constituted by two main transmission lines connected in series by two secondary branch transmission lines. The coupler has a symmetrical four-port layout. The first port is called the input port, the second portAnd the third port is referred to as the output port and the fourth port is referred to as the isolated port. The second port is also referred to as a direct or pass-through port and the third port is referred to as a coupled port. In one example, the coupling port is used to cross-couple the collector/gate terminal of one of the transistors 130/130 'and 135/135' to the base/gate terminal of the respective other of the transistors 130/130 'and 135/135'. The isolated port is used to couple couplers 180 'and 185' via a common interconnect network, which can couple a common bias voltage V_biasInto the common internet.

It should be noted that the present invention is not limited to the exemplary couplers described above. Virtually any type of coupling device that couples a portion of the signal power from the primary path into the secondary path may be used with embodiments of the Gm enhanced differential VCO according to the present invention.

According to an example of the present application, there is provided a differential VCO circuit comprising a pair of transistors having control terminals biased by a common bias voltage and a pair of couplers arranged to cross-couple a first current terminal of the pair of transistors and the control terminals. The pair of couplers have a coupling factor k_c。

In one example, each coupler of the pair of couplers includes a main path and a coupled path. A first coupler of the pair of couplers is coupled to one of the pair of transistors through the main path and to the other of the pair of transistors through the coupling path. The second coupler of the pair of couplers is coupled to the other of the pair of transistors through the main path and to the one of the pair of transistors through the coupling path.

In one example, the coupling paths of the pair of couplers are connected to each other by an interconnect. The coupling paths of the pair of couplers form a series circuit coupling the control terminals of the pair of transistors.

In one example, the common bias voltage is fed into the interconnect.

In one example, the circuit additionally comprises a bias voltage source arranged to supply the common bias voltage through a bias resistor.

In one example, the pair of couplers is one of a pair of coupling transformers and a pair of transmission line based couplers.

In one example, the circuit further comprises a differential transformer having a primary coil and a secondary coil, the primary coil being inserted between the first current terminals of the transistors, and the secondary coil being coupled in a closed series circuit having two varactors arranged to be tuned by a first common tuning voltage. The circuit further comprises a series circuit comprising two further varactors coupled in series to a second current terminal of the transistor. The two further varactors are arranged to be tuned by a second common tuning voltage.

In one example, the circuit additionally includes feedback capacitors, each of the feedback capacitors coupled between the first and second current terminals of a respective one of the transistors.

In one example, the circuit additionally includes a bias current source coupled between the second current terminals of the pair of transistors and a reference potential.

In one example, the circuit is a colpitts differential voltage controller oscillator.

In one example, the primary coil has a center tap arranged to receive a supply voltage. The secondary coil has a center tap coupled to a reference potential.

In one example, the transistor is a bipolar transistor. The first current terminal is a collector terminal, the second current terminal is an emitter terminal, and the control terminal is a base terminal.

In one example, the transistor is a MOS transistor. The first current terminal is a drain terminal, the second current terminal is a source terminal, and the control terminal is a gate terminal.

In one example, the circuit further comprises a first tuning voltage source coupled to the interconnection of the two varactors and arranged to supply the first common tuning voltage.

In one example, the circuit further comprises a second tuning voltage source coupled to the interconnection of the two further varactors and arranged to supply the second common tuning voltage.

In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims.

For example, the semiconductor substrate described herein may be any semiconductor material or combination of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.

The connections or couplings discussed herein may be any type of connection or coupling suitable for communicating signals to and from the respective node, unit or device, e.g., through intermediate devices. The terms coupled and connected, respectively, may be used interchangeably. Thus, unless implied or stated otherwise, the connections may be, for example, direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connection. For example, a single unidirectional connection may be used instead of a bidirectional connection, and vice versa. Also, the multiple connections may be replaced with a single connection that transfers multiple signals serially or in a time division multiplexed manner. Likewise, a single connection carrying multiple signals may be split into various different connections carrying subsets of these signals. Therefore, there are many options for transferring signals.

Each of the signals described herein may be designed as a differential positive or negative analog signal. In the case of a negative analog signal, the signal is relative to a common mode DC signal corresponding to an analog ground level of zero. In the case of a positive analog signal, the signal is higher than the common mode DC signal. Note that any of the differential signals described herein may be designed as either a positive signal or a negative signal.

Those skilled in the art will recognize that the boundaries between functional blocks are merely illustrative and that alternative embodiments may merge functional blocks or circuit elements or impose an alternate decomposition of functionality upon various blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. For example, the induction coil and the resistor may be integrated into one element.

Any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality.

In addition, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Also, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. For example, all components of the oscillator circuit may be integrated on one substrate. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. For example, one or more of the output branches may be partially or completely provided on a different substrate from the substrate on which the oscillator core is provided.

Moreover, the examples, embodiments, or portions thereof, may be implemented as physical circuitry or may be translated into a soft or code representation of a logical representation of the physical circuitry, such as in any suitable type of hardware description language.

Moreover, the invention is not limited to physical devices or units implemented in non-programmable hardware, but can also be applied in programmable devices or units capable of performing the desired device functions by operating in accordance with suitable program code, such as mainframes, microcomputers, servers, workstations, personal computers, notebook computers, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, which are collectively referred to herein as a "computer system".

However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Furthermore, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an". The same holds true for the use of definite articles. Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.