阅读说明：本技术 在源极/漏极区中形成凹槽的方法和由此形成的器件 (Method of forming recesses in source/drain regions and devices formed thereby ) 是由 黄玉莲 于 2018-09-14 设计创作，主要内容包括：本文公开的实施例总体上涉及用于在外延源极/漏极区中形成用于形成导电部件的凹槽的方法。在一些实施例中,在两步蚀刻工艺中形成凹槽,两步蚀刻工艺包括各向异性蚀刻以形成垂直开口和各向同性蚀刻以横向和垂直地扩展垂直开口的端部。凹槽可以在源极/漏极区与导电部件之间具有增加的接触面积,并且可以实现其间的减小的电阻。本发明实施例涉及在源极/漏极区中形成凹槽的方法和由此形成的器件。(Embodiments disclosed herein generally relate to methods for forming recesses in epitaxial source/drain regions for forming conductive features. In some embodiments, the recess is formed in a two-step etching process that includes an anisotropic etch to form a vertical opening and an isotropic etch to laterally and vertically expand the end of the vertical opening. The recess may have an increased contact area between the source/drain region and the conductive feature and may enable a reduced resistance therebetween. Embodiments of the invention relate to methods of forming recesses in source/drain regions and devices formed thereby.)

1. A semiconductor structure, comprising:

An active region including source/drain regions;

A dielectric layer on the active region; and

A conductive member passing through the dielectric layer to and contacting the source/drain region, wherein the conductive member comprises:

A neck portion passing through the dielectric layer; and

An end portion extending in the source/drain region, wherein a width of the end portion is greater than a width of the neck portion.

2. The semiconductor structure of claim 1, wherein a width of the end portion is in a range of 5% to 50% greater than a width of the neck portion.

3. The semiconductor structure of claim 1, wherein the end extends in the source/drain region to a depth in a range of 5% to 50% of a height of the source/drain region.

4. The semiconductor structure of claim 3, wherein the depth is in a range of 10% to 50% of a height of the source/drain region.

5. The semiconductor structure of claim 1, wherein the end portion has a partially circular cross-sectional profile.

6. The semiconductor structure of claim 1, wherein the end portion has an elliptical cross-sectional profile.

7. The semiconductor structure of claim 1, further comprising:

A silicide layer disposed between the conductive member and the source/drain region, wherein the silicide layer has a partially spherical profile or an elliptical profile.

8. A method for semiconductor processing, the method comprising:

Forming a vertical opening through a dielectric layer over a source/drain region of an active region to expose a portion of an upper surface of the source/drain region; and

Expanding the vertical opening to form an expanded opening in the dielectric layer and the source/drain region, wherein the expanded opening comprises:

A neck portion passing through the dielectric layer, wherein the neck portion has a first width; and

An end portion in the source/drain region, wherein the end portion has a second width greater than the first width.

9. The method of claim 8, wherein forming the vertical opening comprises performing an anisotropic etch process.

10. A method for semiconductor processing, the method comprising:

forming source/drain regions in an active region on a substrate;

Forming a dielectric layer over the active region and the source/drain regions;

Anisotropically etching through the dielectric layer to form an opening that exposes at least a portion of an upper surface of the source/drain region;

Isotropically etching the source/drain regions through the openings to laterally and vertically expand ends of the openings; and

Forming a conductive member in the opening.

Technical Field

Embodiments of the invention relate to methods of forming recesses in source/drain regions and devices formed thereby.

Background

The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in generations of ICs, each of which has smaller and more complex circuits than previous generations of ICs. However, these advances increase the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required in order to achieve these advances. As semiconductor devices, such as fin field effect transistors (finfets), are scaled down by various technology nodes, various strategies have been employed to improve device performance, such as the use of high-k dielectric materials and metal gate electrode structures.

Disclosure of Invention

According to some embodiments of the present invention, there is provided a semiconductor structure comprising: an active region including source/drain regions; a dielectric layer on the active region; and a conductive member passing through the dielectric layer to and contacting the source/drain region, wherein the conductive member comprises: a neck portion passing through the dielectric layer; and an end portion extending in the source/drain region, wherein a width of the end portion is greater than a width of the neck portion.

There is also provided, in accordance with other embodiments of the present invention, a method for semiconductor processing, including: forming a vertical opening through a dielectric layer over a source/drain region of an active region to expose a portion of an upper surface of the source/drain region; and expanding the vertical opening to form an expanded opening in the dielectric layer and the source/drain region, wherein the expanded opening comprises: a neck portion passing through the dielectric layer, wherein the neck portion has a first width; and an end portion in the source/drain region, wherein the end portion has a second width greater than the first width.

There is also provided, in accordance with other embodiments of the present invention, a method for semiconductor processing, including: forming source/drain regions in an active region on a substrate; forming a dielectric layer over the active region and the source/drain regions; anisotropically etching through the dielectric layer to form an opening that exposes at least a portion of an upper surface of the source/drain region; isotropically etching the source/drain regions through the openings to laterally and vertically expand ends of the openings; and forming a conductive member in the opening.

Drawings

The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 and 2A-2B, 3A-3B, 4A-4B, 5A-5B, 6A-6B, and 7A-7B are three-dimensional schematic and cross-sectional views of a portion of a semiconductor device corresponding to various stages in an exemplary fabrication process, according to some embodiments.

fig. 8A-8B and 9A-9B are schematic cross-sectional views of a portion of a semiconductor device corresponding to various stages in another exemplary fabrication process, according to some embodiments.

fig. 10 illustrates a portion of the cross-sectional view of fig. 5A to further illustrate additional details according to some embodiments.

Fig. 11 illustrates a portion of the cross-sectional view of fig. 6A to further illustrate additional details, according to some embodiments.

Fig. 12 illustrates a portion of the cross-sectional view of fig. 7A to further illustrate additional details, according to some embodiments.

fig. 13 illustrates a portion of the cross-sectional view of fig. 8A to further illustrate additional details, according to some embodiments.

Fig. 14 illustrates a portion of the cross-sectional view of fig. 9A to further illustrate additional details, according to some embodiments.

Detailed Description

the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element (or other) component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Embodiments disclosed herein generally relate to methods for forming recesses in epitaxial source/drain regions to form conductive features. In some embodiments, the recess is formed in a two-step etching process including anisotropic etching and isotropic etching. The recess may have an increased contact area between the source/drain region and the conductive member, and may enable a reduction in resistance therebetween.

The foregoing has outlined some of the aspects of the embodiments described in the present disclosure in general. It is contemplated that the concepts of the present disclosure may be implemented for planar transistor devices or for three-dimensional transistor devices (e.g., semiconductor device 240 described in the present disclosure). Some example devices of aspects described herein include fin field effect transistors (finfets), Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, nanowire channel FETs, strained semiconductor devices, Silicon On Insulator (SOI) devices, or other devices.

fig. 1 shows an example of a semiconductor device 240 in a three-dimensional view. Fig. 2A-2B-7A-7B and 8A-8B-9A-9B are schematic cross-sectional views of a portion of a semiconductor device 240 corresponding to various stages of fabrication according to some embodiments. It is noted that any other semiconductor structure not presented herein may be formed utilizing the methods described herein. Those of ordinary skill in the art will recognize that the complete process and associated structures for forming semiconductor devices are not depicted in the drawings or described herein. While various operations are illustrated in the drawings and described herein, there is no intent to limit the order of such steps or the presence or absence of intervening steps. Operations shown or described as sequential are, unless explicitly stated otherwise, merely for explanatory purposes and do not exclude the possibility that individual steps may in fact be performed in parallel or overlapping, at least in part, if not entirely.

As shown in fig. 1, the semiconductor device 240 has a fin 274 formed on a semiconductor substrate 270. The semiconductor substrate 270 may be or include a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. In some embodiments, the semiconductor material of the semiconductor substrate 270 may include an elemental semiconductor comprising silicon (Si) or germanium (Ge); a compound semiconductor; an alloy semiconductor; or a combination thereof.

Each fin 274 provides an active region for forming one or more devices. The fins 274 are fabricated using suitable processes including masking, photolithography, and/or etching processes to form the trenches 253 in the substrate 270 such that the fins 274 extend upwardly from the substrate 270. The trench 253 can then be filled with an insulating material, such as an oxide (e.g., silicon oxide), nitride, or the like, or combinations thereof. Such as by recessing the insulating material using an acceptable etch process to form isolation regions 278. The insulating material is recessed such that the fins 274 protrude upward from between adjacent isolation regions 278.

The semiconductor device 240 includes a gate structure 251 formed over a top surface of the fin 274 and along sidewalls of the fin 274. The gate structure 251 extends longitudinally perpendicular to the fin 274. Each gate structure 251 includes a gate dielectric 280, a gate layer 282 over the gate dielectric 280, and a mask 284 over the gate layer 282. The semiconductor device 240 further includes source/drain regions 292 disposed in opposing regions of the fin 274 relative to the gate structure 251.

The gate structure 251 may be an operable gate stack in a previous gate process or may be a dummy gate stack in a replacement gate process. For simplicity, a replacement gate process is described herein; one of ordinary skill in the art will readily appreciate modifications to the processing described herein to achieve a gate first process. In a replacement gate process, the gate dielectric 280 may be an interface dielectric and the gate layer 282 may be a dummy gate. The gate dielectric 280, gate layer 282, and mask 284 for the gate structure 251 may be formed by sequentially forming the various layers, such as by suitable deposition techniques, and then patterning the layers into the gate structure 251, such as by suitable photolithography and etching processes. The interfacial dielectric may comprise or be silicon oxide, silicon nitride, etc., or multilayers thereof. The dummy gate may include or may be silicon (e.g., polysilicon) or another material. The mask may include or may be silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof.

Fig. 1 also shows a reference section used in later figures. Cross section AA is in a plane along the channel in fin 274 between, for example, opposing source/drain regions 292. Cross section BB is in a plane perpendicular to cross section AA and spans source/drain region 292 in fin 274. For clarity, the following figures refer to these reference sections. The following figures ending with an "a" mark show cross-sectional views in various cases of processing corresponding to section AA, and the following figures ending with a "B" mark show cross-sectional views in various cases of processing corresponding to section BB. Fig. 2A and 2B show respective cross-sectional views of the semiconductor device 240 depicted in the three-dimensional view of fig. 1.

In fig. 3A and 3B, gate spacers 286 are formed along sidewalls of the gate structure 251 (e.g., sidewalls of the gate dielectric 280, the gate layer 282, and the mask 284) and over the fin 274. The gate spacers 286 may be formed, for example, by conformally depositing one or more layers for the gate spacers 286 and anisotropically etching the one or more layers. One or more layers for gate spacers 286 may comprise a different material than the material used for gate structure 251. In some embodiments, the gate spacers 286 may include or may be a dielectric material such as silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof.

As shown in fig. 3A and 3B, source/drain regions 292 may be formed in the fin 274 after the gate spacers 286 are formed. In some examples, such as shown in the figures, a recess may be etched in fin 274 using gate structure 251 as a mask (such that recesses are formed on opposite sides of gate structure 251), and material may be epitaxially grown in the recess to form source/drain regions 292. Additionally or alternatively, the source/drain regions 292 may be formed by implanting dopants into the fin 274 and/or the epitaxial source/drain regions 292 using the gate structure 251 as a mask (such that the source/drain regions are formed on opposite sides of the gate structure 251).

Depending on the conductivity type of the transistor, the material for source/drain regions 292 may be selected to include or be silicon germanium, silicon carbide, silicon phosphorous, silicon carbon phosphorous, germanium, a group III-V compound semiconductor, a group II-VI compound semiconductor, or the like. In some examples, SiGe may be included in the source/drain region 292 for a p-type device, while SiCP or SiP may be included in the source/drain region 292 for an n-type device. As shown in fig. 3B, due to the blocking of the isolation region 278, the material in the source/drain region 292 first grows vertically in the recess, during which the source/drain region 292 does not grow horizontally. After completely filling the recess, the material of source/drain regions 292 may be grown vertically and horizontally to form facets, which may correspond to a crystallographic plane of semiconductor substrate 270. In some examples, different materials are used for the epitaxial source/drain regions of the p-type device and the n-type device. Appropriate masking during the recess or epitaxial growth process may allow different materials to be used for different devices.

as shown in fig. 3A, epitaxial source/drain regions 292 are formed between the gate structures 251 in place of the removed portions of the fin 274. In some embodiments, the cross-sectional area of epitaxial source/drain regions 292 along the AA line may be shaped like a hexagon, although other cross-sectional areas may be implemented, such as due to other shapes of the etching process used to recess fin 264. The cross-sectional area along line AA can have a height 292h and a width 292 w. In some embodiments, the height 292h may be in the range of about 40nm to about 50 nm. In some embodiments, the width 292w may be greater than 30nm, for example in the range of about 30nm to about 50 nm.

In fig. 3B, epitaxial source/drain regions 292 are epitaxially grown from the fin 274 along the grooves between the isolation regions 278. Epitaxial source/drain regions 292 extend upward from the recesses between isolation regions 278 and form a generally diamond shape along the BB lines due to the crystalline orientation of the material being grown, but may form other shapes. In some embodiments, epitaxial source/drain regions 292 may have a diamond-shaped cross-sectional area along line B-B, the diamond-shaped cross-sectional area having an apex angle 292Q. In some embodiments, the apex angle 292Q is in a range from about 60 degrees to about 160 degrees, such as from about 70 degrees to about 80 degrees.

In the example shown in fig. 3A and 3B, epitaxial source/drain regions 292 have varying widths along respective cross sections as epitaxial source/drain regions 292 traverse from respective bottom to top of the epitaxial source/drain regions. The width increases from the top of the respective epitaxial source/drain region 292 to a middle portion of the epitaxial source/drain region 292, and then decreases from the middle portion of the epitaxial source/drain region 292 to the bottom of the epitaxial source/drain region 292.

in fig. 4A and 4B, after forming the source/drain regions 292, a Contact Etch Stop Layer (CESL)296 is conformally formed on the surfaces of the source/drain regions 292, the sidewalls and top surfaces of the gate spacers 286, the top surface of the mask 284, and the top surface of the isolation regions 278. A first interlayer dielectric (ILD)297 is formed on CESL 296. CESL296 and the first ILD297 may be deposited using any suitable deposition technique. CESL296 may include or be silicon nitride, silicon carbonitride, silicon oxycarbide, carbonitride, the like, or combinations thereof. The first ILD297 may comprise or be silicon dioxide, a low-k dielectric material (e.g., a material having a dielectric constant lower than silicon dioxide), silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), Undoped Silicate Glass (USG), fluorosilicate glass (FSG), organosilicate glass (OSG), SiOxCy, spin-on glass, spin-on polymers, silicon carbon materials, combinations thereof. A Chemical Mechanical Polishing (CMP) process may then be performed to planarize the first ILD297 and CESL296 and remove the mask 284 of the gate structure 251, thereby making the top surfaces of the first ILD297 and CESL296 flush with the top surface of the gate layer 282.

After the CMP process, the gate structure 251 is removed using one or more etching processes such that replacement gate structures 228a, 228b may be formed in the recesses formed by removing the gate structure 251. When the gate structure 251 is removed, a recess is formed between the gate spacers 286 of the gate structure 251, which are removed, and a channel region of the fin 274 is exposed through the recess. Replacement gate structures 228a, 228b are then formed in the recesses where gate structure 251 was removed.

As shown in fig. 4A, replacement gate structures 228a, 228b may each include an interfacial dielectric 220, a gate dielectric layer 222, one or more optional conformal layers 224, and a gate metal fill 226. An interfacial dielectric 220 is formed on the top surface and sidewalls of the fin 274 along the channel region. Interface dielectric 220 may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), and/or another dielectric layer formed using any suitable deposition technique.

Gate dielectric layer 222 may be conformally deposited in the recesses where the gate stack is removed (e.g., on the sidewalls of interface dielectric 220 and gate spacers 286) and on the top surfaces of first ILD297, CESL296 and gate spacers 286. The gate dielectric layer 222 may be or include silicon oxide, silicon nitride, high-k dielectric materials, multilayers thereof, or other dielectric materials. The high-k dielectric material may have a k value greater than about 7.0, and may include a metal oxide or metal silicate of hafnium (Hf), aluminum (Al), zirconium (Zr), lanthanum (La), magnesium (Mg), barium (Ba), titanium (Ti), lead (Pb), multilayers thereof, or combinations thereof.

The one or more optional conformal layers 224 may include one or more barrier and/or capping layers and one or more work function adjusting layers. The one or more barrier and/or capping layers may comprise tantalum nitride, titanium nitride, the like, or combinations thereof. The one or more work function adjusting layers may comprise or be titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, the like, or combinations thereof. The materials for the one or more work function adjusting layers, barrier layers and/or capping layers are selected to achieve a desired threshold voltage (Vt) for the transistor, which may be a p-type transistor or an n-type transistor. A gate metal fill 226 is formed on the one or more conformal layers 224 and/or over the gate dielectric layer 222, if implemented. The gate metal fill 226 may fill the remaining recess in which the gate structure 251 is removed. The gate metal fill 226 may be or include a metal-containing material such as tungsten, cobalt, aluminum, ruthenium, copper, multilayers thereof, combinations thereof, and the like.

A planarization process like CMP may remove portions of the layers for the gate metal fill 226, the one or more conformal layers 224, and the gate dielectric layer 222 that are over the top surfaces of the first ILD297, CESL296 and the gate spacers 286. Accordingly, replacement gate structures 228 may be formed that include gate metal fill 226, one or more conformal layers 224, gate dielectric layer 222, and interfacial dielectric 220.

In fig. 5A and 5B, a second ILD230 is formed over the replacement gate structure 228, the first ILD297, the gate spacers 286 and the CESL296 after the planarization process. The second ILD230 may comprise or be silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOxCy, spin-on glass, spin-on polymer, silicon carbon material, compounds thereof, composites thereof, and the like, or combinations thereof and may be deposited using any acceptable deposition technique.

After forming the second ILD230, the first ILD297 and CESL296 are formed through the second ILD230 to source/drain contact openings to the source/drain regions 292 to expose at least a portion of the source/drain regions 292. According to some embodiments, the source/drain contact openings may be formed by a two-step etching process including an anisotropic etching process to form vertical openings 232 as shown in fig. 5A and 5B and an isotropic etching process to increase the surface area at the bottom of the vertical openings as shown in fig. 6A and 6B and fig. 8A and 8B.

In fig. 5A and 5B, vertical openings 232 are formed through the second ILD230, the first ILD297 and CESL296 using photolithography and one or more anisotropic etching processes. The one or more etching processes may be a dry etching process, a Deep Reactive Ion Etching (DRIE) process, or any suitable anisotropic etching process.

Fig. 10 is an enlarged view of area 300 in fig. 5A, showing details of the bottom of the vertical opening 232. Vertical opening 232 may be a hole or trench extending into epitaxial source/drain region 292. The sidewalls of the source/drain vertical openings 232 are substantially vertical, but may have a small slope angle. The vertical opening 232 has a width 232w near a bottom surface 232b of the vertical opening 232. In some embodiments, the width 232w may be in the range of about 10nm to about 40 nm. In some embodiments, width 232w may be in a range of about 33% to about 100% of width 292w of epitaxial source/drain region 292.

The vertical opening 232 extends into the epitaxial source/drain region 292 such that a bottom surface 232b of the vertical opening 232 is below a top 292t of the epitaxial source/drain region 292. Height 232h indicates the distance from the top 292t of epitaxial source/drain region 292 to the bottom surface 232b of vertical opening 232. In some embodiments, the height 232h may be in the range of greater than 0nm to about 20 nm. In some embodiments, the height 232h may be in the range of greater than 0% to about 50% of the height 292 h.

In the example shown in fig. 10, the width of the cross section of the source/drain region 292 in the AA section (or the cross section parallel to the yz plane in the xyz coordinate shown in fig. 1) increases from the top portion 292t to the middle portion, and decreases from the middle portion to the bottom portion 292 b. Centerline 292c indicates the vertical position of the cross-sectional area having the greatest width 292 w. The size and circumference of the cross section of the source/drain region 292 in the xy plane also increase from the top 292t to the centerline 292c and decrease from the centerline 292c to the bottom 292b, corresponding to the increase and decrease in width in the yz plane. According to some embodiments, the bottom surface 232b is located above the centerline 292 c.

The vertical openings 232 may be formed by one or more anisotropic etching processes. For example, a first anisotropic etch process may be performed to etch through the second ILD230, the first ILD297 and CESL296, and a second anisotropic etch process may be performed to form a recess of height 232h in the epitaxial source/drain regions 292. In some embodiments, the first anisotropic etch process and the second anisotropic etch process may be the same process performed together in a single operation. In other embodiments, the first anisotropic etch process and the second anisotropic process are different processes having different etch chemistries and/or process parameters.

In some examples, the first anisotropic etch process may be performed using an Inductively Coupled Plasma (ICP) or a Capacitively Coupled Plasma (CCP) containing oxygen, argon, and one or more fluorocarbon-based gases, such as hexafluorobutadiene (C ₄ F ₆), octafluorocyclobutane (C ₄ F ₈), or carbon tetrafluoride (CF ₄).

In some embodiments, the etchant may contain one or more fluorocarbon-based gases, such as carbon tetrafluoride (CF ₄), trifluoromethane (CHF ₃), one or more fluorine-based gases, such as nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), hexafluorobutadiene (C ₄ F ₆), and octafluorocyclobutane (C ₄ F ₈), chlorine-based gases, such as chlorine (Cl ₂), and/or bromine-based gases, such as hydrogen bromide (HBr).

In some examples, the vertical opening 232 is formed by sequentially performing a dry etching process using an inductively coupled plasma. The RF power of the plasma generator may be in the range of about 100W to about 2000W to induce and maintain a plasma of the etchant in the processing chamber. The process chamber can have a chamber pressure of about 3 mtorr to about 20 mtorr. A bias voltage of about 20 volts to about 1500 volts may be applied to the plasma to achieve the anisotropic etch. In some embodiments, the anisotropic etch process may be performed in a range of about 155 seconds to about 1800 seconds. For example, the etching process may be performed for a duration in a range of about 200 seconds to about 1200 seconds, such as about 150 seconds, to form openings through the second ILD230, the first ILD297 and CESL 296. After removing CESL296, an additional etch may be performed for a period ranging from about 5 seconds to about 1050 seconds to recess vertical opening 232 within epitaxial source/drain region 292 to a height 232 h.

after the vertical opening 232 is formed, the bottom of the vertical opening 232 is expanded by an etching process such as an isotropic etching process. As shown in fig. 6A and 6B, the expanded opening 234 is formed by the vertical opening 232 to allow electrical contact to the source/drain region 292 of the transistor.

in some embodiments, the expansion opening 234 is formed by an isotropic etch process with high etch selectivity between the epitaxial source/drain region 292 and the second ILD230, the first ILD297 and the CESL 296. As a result, the extension opening 234 and the vertical opening 232 are substantially the same size in the second ILD230, the first ILD297, and the CESL296, while the extension opening 234 is deeper and has a greater width in the epitaxial source/drain regions 292 than the vertical opening 232.

FIG. 11 is an enlarged view of area 302 of FIG. 6A, showing details of the bottom of the expanded opening 234. The bottom of the vertical opening 232 is shown in phantom. The expansion opening 234 includes a neck 234n formed through the second ILD230, the first ILD297 and CESL296 and an end 234e formed in the epitaxial source/drain region 292. The end 234e may have a partially elliptical cross-sectional area along a cross-section AA (see fig. 1). End 234e may have a partially spherical shape with a partially spherical bottom surface 234cs formed in an epitaxial source/drain region 292. As discussed in fig. 10, the size and circumference of the cross-section of the source/drain region 292 in the xy plane also increases from the top 292t to the centerline 292c and decreases from the centerline 292c to the bottom 292 b. Isotropically etching source/drain region 292 after forming vertical opening 232 allows the size of bottom surface 234cs to be enlarged and, thus, allows the contact area between source/drain region 292 and the metal fill (to be filled in opening 234) to be increased.

Height 234h represents the distance from the top 292t of epitaxial source/drain region 292 to the bottom point 234b of the end 234e of extension opening 234. In some embodiments, the height 234h may be in the range of about 5nm to about 20 nm. In some embodiments, height 234h may be in a range of about 10% to about 50% of height 292h of epitaxial source/drain region 292. In some embodiments, in cross-section AA, bottom surface 234cs is located above centerline 292c of epitaxial source/drain region 292.

In some embodiments, the width 234w of the end portion 234e may be in a range from about 14nm to about 40 nm. In some embodiments, width 234w may be in a range of about 30% to about 80% of width 292w of epitaxial source/drain region 292.

The end portion 234e is formed by laterally expanding the vertical opening 232 in the epitaxial source/drain region 292 by a lateral expansion dw and vertically expanding the vertical opening 232 in the epitaxial source/drain region 292 by a vertical expansion dh. In some embodiments, the vertical extension dh may be in a range from about 5nm to about 20 nm. For example, for an n-type FinFET device, the vertical extension dh may be in the range of about 5nm to about 20 nm. For a p-type FinFET device, the vertical spread dh may be in a range from about 5nm to about 10 nm. In some embodiments, the lateral spread dw may range from about 2nm to about 10 nm. Accordingly, the width 234w of the end 234e may be in the range of about 4nm to about 20nm greater than the width 232w of the opening 234. In some examples, the width 234w of the end 234e is equal to or about 5% greater than the width 232w of the opening 234, such as in a range from about 5% to about 50% greater than the width 232w of the opening 234. The increased width 234w may increase the surface area of the conductive features contacting the source/drain regions 292. More specifically, for example, for an n-type FinFET device, the lateral spread dw may be in a range of about 2nm to about 10 nm. For a p-type FinFET device, the lateral spread dw may range from about 2nm to about 5 nm. In some embodiments, the source/drain regions 292 in the n-type device and the p-type device may have different dimensions (e.g., widths and/or heights) due to the epitaxial growth of different materials as the source/drain regions 292. For example, the height and width of the source/drain region 292 of the p-type device may be less than the height and width of the source/drain region 292 of the n-type device, and thus, the vertical extension dh and the lateral extension dw in the source/drain region 292 of the p-type device may be less than the vertical extension dh and the lateral extension dw in the source/drain region 292 of the n-type device.

In some embodiments, the lateral spread dw and the vertical spread dh may be achieved by an isotropic etching process, such as an isotropic dry etching process or an isotropic wet etching process.

The etchant may include a fluorocarbon based gas such as carbon tetrafluoride (CF ₄), trifluoromethane (CHF ₃), one or more fluorine based gases such as nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), chlorine based gases such as chlorine (Cl ₂), and/or bromine based gases such as hydrogen bromide (HBr). the RF power of the plasma generator may be in the range of about 100W to about 2000W to induce and maintain a plasma of the etchant in the process chamber.

In some embodiments, the isotropic dry etch process may be performed in the same dry etch chamber in which the anisotropic dry etch process is performed. In forming the vertical opening 232 shown in fig. 5A and 5B, the process parameters of the dry etching chamber are adjusted to perform isotropic dry etching to form the end 234e of the expanded opening 234.

In some embodiments, the lateral spread dw and the vertical spread dh may be achieved by a wet etching process, for example, a wet etching process using an ammonium hydroxide-hydrogen peroxide water mixture (APM), such as a wet etching solution having ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂), and deionized water (H ₂ O) in a ratio of about 1:1:8000 to about 1:1:100 (NH ₄ OH: H ₂ O ₂: H ₂ O).

After forming the flared openings 234, a pre-silicide cleaning process may be performed to remove native oxide (e.g., SiO ₂) from the surface of the exposed source/drain regions 292, which may be formed as a result of exposure to various etchants during formation of the flared openings 234.

a conformal metal layer (not shown) is formed on the surface of the exposed source/drain regions 292 (e.g., the partial spherical bottom surface 234cs) and over the second ILD230, the first ILD297 and the CESL 296. In some embodiments, the conformal metal layer may comprise a single layer of titanium, tantalum, or the like. In other embodiments, the conformal metal layer may be a multi-layer stack (e.g., a bilayer), such as a first layer comprising titanium, tantalum, etc., and a second layer comprising titanium nitride, titanium oxide, tantalum nitride, tantalum oxide. The metal layer may be deposited by Atomic Layer Deposition (ALD), Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or any suitable deposition technique.

After the metal layer is formed, a silicide layer 214 is formed on the source/drain region 292 by reacting an upper portion of the source/drain region 292 with the metal layer, as shown in fig. 7A and 7B. The substrate 270 is heated, for example by performing an annealing process, to cause a silicidation reaction to occur wherever the metal layer makes contact with the source/drain regions 292. For example, the annealing process may be a Rapid Thermal Anneal (RTA) performed at a temperature of about 400 ℃ to about 650 ℃, such as about 500 ℃, for a duration of about 10 seconds to about 60 seconds. The unreacted metal layer 210 may be removed by a selective etching process that attacks the unreacted metal layer 210 but does not attack the silicide layer 214, or may remain as, for example, an adhesion and/or barrier layer.

As shown in fig. 7A and 7B, the barrier layer 219 is conformally deposited in the expanded opening 234 on the silicide layer 214 and over the second ILD230, the first ILD297 and the CESL 296. The barrier layer 219 may have a thickness of about 2nm or less, such as about 1.8nm or less, for example about 1.6 nm. The barrier layer 219 may be or include titanium nitride, titanium oxide, tantalum nitride, tantalum oxide, any suitable transition metal nitride or oxide, or the like, or any combination thereof, and may be deposited by ALD, CVD, PECVD, HDP-CVD, low pressure CVD (lpcvd), or Physical Vapor Deposition (PVD), or any suitable deposition technique. In some examples, the barrier layer is TiN deposited by ALD.

A conductive material 236 (e.g., a contact metal) may be deposited on the barrier layer 219 and fill the expanded opening 234. The conductive material 236 may be or include cobalt, tungsten, copper, ruthenium, aluminum, gold, silver, alloys thereof, or the like, or combinations thereof, and may be deposited by CVD, ALD, PVD, or any suitable deposition technique. After depositing the conductive material 236, the excess conductive material 236 and the barrier layer 219 may be removed, for example, by using a planarization process (e.g., CMP). As shown in fig. 7A and 7B, the planarization process may remove the excess conductive material 236 and the barrier layer 219 from over the top surface of the second ILD 230.

fig. 12 is an enlarged view of region 303 in fig. 7A, showing details of the conductive material and the silicide layer 214. Silicide layer 214 corresponds to a partially spherical bottom surface 234cs of end 234e in expanded opening 234 and thus has an increased surface area. The increased surface area of the silicide layer 214 may reduce the resistance between the epitaxial source/drain regions 292 and the contacts formed in the extension openings 234.

The conductive material 236 includes a neck 236n formed through the second ILD230, the first ILD297 and CESL296, and an end 236e formed on the epitaxial source/drain region 292. The neck 236n may be a groove or a cylinder with substantially vertical walls. The width of the neck 236n may be in the range of about 10nm to about 50 nm. The end 236e may have a partially elliptical cross-sectional area along the section a-a (see fig. 1). The end portion 236e may have a partial spherical shape facing the partial spherical bottom surface of the silicide layer 214.

The height 236h of the end portion 236e may be in the range of about 5nm to about 25 nm. The width 236w of the end portion 234e may range from about 15nm to about 50 nm. In some embodiments, the width 236w of the end portion 236e may be greater than the width of the neck portion 263n by an amount of about 2nm to about 20 nm. The depth and width of end portion 236e may enable an increased contact surface of end portion 236e to epitaxial source/drain region 292, and thus may enable a reduction in resistance therebetween.

The expansion opening may have various shapes depending on, for example, (i) the size of the epitaxial source/drain regions 292, (ii) the size of the vertical opening 232, (iii) whether a passivation process is performed prior to the isotropic etch, and/or (iv) the isotropic etch chemistry, each of which may affect the lateral expansion dw and the vertical expansion dh. For example, the end 234e may be a partial spheroid, such as a partial sphere, a partial ellipse, or the like.

Fig. 8A and 8B illustrate the expanded opening 244 having a different shape than the expanded opening 234. Similar to the expanded openings 234 of fig. 6A and 6B, expanded openings 244 are formed by expanding the vertical openings 232 of fig. 5A and 5B by an isotropic etching process as described in fig. 6A.

Fig. 13 is an enlarged view of region 304 in fig. 8A, showing details of the expanded opening 244. The bottom of the vertical opening 232 is shown in phantom. The expansion opening 244 includes a neck 244n formed through the upper portions of the second ILD230, the first ILD297, CESL296 and the epitaxial source/drain region 292, and an end 244e formed in the epitaxial source/drain region and below the top 292t of the epitaxial source/drain region 292. The neck 244n may be a groove or a cylinder having substantially vertical walls. The neck 244n may have a width substantially similar to the width 232w of the vertical opening 232. The bottom 244nb of the neck 244n is lower than the top 292t of the epitaxial source/drain region 292.

End 244e may have an elliptical cross-sectional area along section a-a (see fig. 1). End 244e may have an elliptical shape with an elliptical surface 244cs formed in epitaxial source/drain region 292.

Height 244h indicates the distance from the top 292t of epitaxial source/drain region 292 to the bottom point 244b of extension opening 244. In some embodiments, the height 244h may be in a range from about 2nm to about 20 nm. In some embodiments, height 244h may be in a range of about 5% to about 50% of height 292h of epitaxial source/drain region 292. The height 244eh indicates the height of the end 244e, e.g., the distance from the bottom 244nb of the neck 244n to the bottom point 244b of the expanded opening 244. Height 244eh is less than height 244 h.

In some embodiments, the width 244w of the end 244e can be in a range from about 14nm to about 40 nm. In some embodiments, width 244w may be in a range of about 10% to about 50% of width 292w of epitaxial source/drain region 292.

The end 244e is formed by laterally expanding the vertical opening 232 in the epitaxial source/drain region 292 by a lateral expansion dw2 and vertically expanding the vertical opening 232 in the epitaxial source/drain region 292 by a vertical expansion dh 2. In some embodiments, the vertical extension dh2 may be in a range from about 2nm to about 20 nm. For example, for an n-type FinFET device, the vertical extension dh2 may be in the range of about 2nm to about 20 nm. For a p-type FinFET device, the vertical extension dh2 may be in the range of about 2nm to about 10 nm. In some embodiments, the lateral expansion dw2 may be in a range from about 2nm to about 10 nm. Accordingly, the width 244w of the end 244e may be in the range of about 4nm to about 20nm greater than the width 232w of the opening 244. In some examples, the width 244w of the end 244e is equal to or about 5% greater than the width 232w of the opening 244, such as about 5% to about 50% greater than the width 232w of the opening 244. The increased width 244w may increase the surface area that the conductive features may contact the source/drain regions 292. More specifically, for example, for an n-type FinFET device, the lateral extension dw2 may be in a range from about 2nm to about 10 nm. For a p-type FinFET device, the lateral spread dw2 may range from about 2nm to about 5 nm. In some embodiments, the source/drain regions 292 in the n-type device and the p-type device may have different dimensions (e.g., widths and/or heights) due to the epitaxial growth of different materials as the source/drain regions 292. For example, the height and width of the source/drain region 292 of the p-type device may be less than the height and width of the source/drain region 292 of the n-type device, and thus, the vertical extension dh2 and the lateral extension dw2 in the source/drain region 292 of the p-type device may be less than the vertical extension dh2 and the lateral extension dw2 in the source/drain region 292 of the n-type device.

in some embodiments, one or more of the anisotropic etch processes described above with respect to fig. 5A and 5B may passivate the surfaces of the vertical openings 232. in some examples, the passivated surfaces have C _x H _y F _z formed thereon as a result of the anisotropic etch process after the anisotropic etch process of fig. 5A and 5B, additional anisotropic etch processes, such as using a plasma formed from oxygen (O ₂), hydrogen (H ₂), and the like, may penetrate or remove the passivated surface on the bottom of each vertical opening 232.

In fig. 9A and 9B, silicide layer 248 is formed on the surface of epitaxial source/drain regions 292 in extension openings 244; conformally forming a barrier layer 219 in the extension opening 244; and a conductive material 246 is formed over the barrier layer 219 and the conductive material 246 fills the expanded opening 244, as described with respect to fig. 7A and 7B.

Fig. 14 is an enlarged view of region 305 in fig. 9A, showing details of conductive material 246 and silicide layer 248. The silicide layer 248 corresponds to the elliptical surfaces 244cs of the end portions 244e in the extension openings 244 and the sidewalls of the epitaxial source/drain regions 292 formed by the neck portions 244n of the extension openings 244, and thus the silicide layer 248 may have an increased surface area. The increased surface area of the silicide layer 248 may reduce the resistance between the epitaxial source/drain regions 292 and the contacts formed in the extension openings 244.

The conductive material 246 includes a neck 246n formed through the second ILD230, the first ILD297, CESL296 and a portion of the epitaxial source/drain region 292 and an end 246e formed at the epitaxial source/drain region 292. The neck 246n may be a groove or a cylinder having substantially vertical walls. The width of the neck 246n may be in the range of about 10nm to about 50 nm. End 246e may have an elliptical cross-sectional area along section A-A (see FIG. 1). The end portion 246e may have an elliptical shape having an elliptical surface facing the silicide layer 248.

The height 246eh of the end 246e may range from about 2nm to about 20 nm. The width 246w of the end portion 244e may range from about 10nm to about 50 nm. In some embodiments, the width 246w of the end portion 246e may be greater than the width of the neck portion 246n by an amount in the range of about 2nm to about 20 nm. The depth and width of end 246e may enable an increased contact surface of end 246e to epitaxial source/drain region 292, and thus may reduce the resistance therebetween.

The combination of anisotropic etching and isotropic etching described herein may expose an increased surface area of the source/drain regions and may thus increase the contact area between the source/drain regions and the contact features. The increased contact area may reduce the resistance between the contact feature and the source/drain region, and thus, may improve the performance of the device.

in an embodiment, a structure is provided. The structure includes: an active region including source/drain regions; a dielectric layer disposed on the active region; and a conductive member passing through the dielectric layer to and contacting the source/drain region. The conductive member includes: a neck portion through the dielectric layer; and an end portion extending in the source/drain region. The width of the end portion is greater than the width of the neck portion.

in another embodiment, a method is provided. The method comprises the following steps: forming a vertical opening through the dielectric layer over the source/drain region of the active region to expose a portion of an upper surface of the source/drain region; and expanding the vertical opening to form an expanded opening in the dielectric layer and the source/drain region. The expansion opening includes: a neck through the dielectric layer and an end in the source/drain region. The neck portion has a first width and the end portion has a second width greater than the first width.

In yet another embodiment, a method for semiconductor processing is provided. The method comprises the following steps: forming source/drain regions in an active region on a substrate; forming a dielectric layer over the active region and the source/drain regions; anisotropically etching through the dielectric layer to form an opening exposing at least a portion of an upper surface of the source/drain region; isotropically etching the source/drain regions through the openings to laterally and vertically expand the ends of the openings; and forming a conductive member in the opening.

According to some embodiments of the present invention, there is provided a semiconductor structure comprising: an active region including source/drain regions; a dielectric layer on the active region; and a conductive member passing through the dielectric layer to and contacting the source/drain region, wherein the conductive member comprises: a neck portion passing through the dielectric layer; and an end portion extending in the source/drain region, wherein a width of the end portion is greater than a width of the neck portion.

In the above semiconductor structure, the width of the end portion is larger than the width of the neck portion by a range of 5% to 50%.

In the above semiconductor structure, the end portion extends in the source/drain region to a depth in a range of 5% to 50% of a height of the source/drain region.

In the above semiconductor structure, the depth is in a range of 10% to 50% of a height of the source/drain region.

In the above semiconductor structure, the end portion has a partially circular cross-sectional profile.

In the above semiconductor structure, the end portion has an elliptical cross-sectional profile.

In the above semiconductor structure, further comprising: a silicide layer disposed between the conductive member and the source/drain region, wherein the silicide layer has a partially spherical profile or an elliptical profile.

There is also provided, in accordance with other embodiments of the present invention, a method for semiconductor processing, including: forming a vertical opening through a dielectric layer over a source/drain region of an active region to expose a portion of an upper surface of the source/drain region; and expanding the vertical opening to form an expanded opening in the dielectric layer and the source/drain region, wherein the expanded opening comprises: a neck portion passing through the dielectric layer, wherein the neck portion has a first width; and an end portion in the source/drain region, wherein the end portion has a second width greater than the first width.

In the above method, forming the vertical opening includes performing an anisotropic etching process.

In the above method, the anisotropic etching process is a dry etching process using a plasma of etching chemicals including fluorine-based gas, chlorine gas, hydrogen bromide gas, or a combination thereof.

In the above method, expanding the vertical opening comprises isotropically etching the source/drain region through the vertical opening.

In the above method, isotropically etching the source/drain region includes performing a dry etching process, wherein the dry etching process is performed using an etching chemistry including a fluorine-based gas, a chlorine gas, a hydrogen bromide, or a combination thereof.

In the above method, isotropically etching the source/drain region includes performing a wet etching process, wherein the wet etching process is performed using an etching solution including ammonium hydroxide, hydrogen peroxide, and water.

In the above method, expanding the vertical opening comprises vertically expanding the vertical opening into the source/drain region to a depth in a range of 5% to 50% of a height of the source/drain region.

In the above method, expanding the vertical opening comprises laterally expanding a bottom of the vertical opening to the first width, wherein the first width is in a range of 5% to 50% more than the second width.

There is also provided, in accordance with other embodiments of the present invention, a method for semiconductor processing, including: forming source/drain regions in an active region on a substrate; forming a dielectric layer over the active region and the source/drain regions; anisotropically etching through the dielectric layer to form an opening that exposes at least a portion of an upper surface of the source/drain region; isotropically etching the source/drain regions through the openings to laterally and vertically expand ends of the openings; and forming a conductive member in the opening.

In the above method, the source/drain region is isotropically etched to laterally expand the end portion of the opening by an amount in a range of 2nm to 20nm and to vertically expand the end portion of the opening by an amount in a range of 2nm to 20 nm.

In the above method, anisotropically etching through the dielectric layer includes performing a dry etch process using an etchant comprising at least one of carbon tetrafluoride (CF ₄), trifluoromethane (CHF ₃), nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), chlorine (Cl ₂), hydrogen bromide (HBr), or combinations thereof.

In the above method, anisotropically etching through the dielectric layer includes performing a dry etch process using an etchant comprising at least one of carbon tetrafluoride (CF ₄), trifluoromethane (CHF ₃), nitrogen trifluoride (NF ₃), sulfur hexafluoride (SF ₆), hexafluorobutadiene (C ₄ F ₆), and octafluorocyclobutane (C ₄ F ₈), chlorine (Cl ₂), hydrogen bromide (HBr), or a combination thereof.

In the above method, isotropically etching the source/drain region includes performing a wet etching process using ammonium hydroxide: hydrogen peroxide: an etching solution of ammonium hydroxide, hydrogen peroxide and water in a ratio of water in the range of 1:1:8000 to 1:1: 100.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.