阅读说明：本技术 半导体器件及制造方法 (Semiconductor device and method of manufacturing the same ) 是由 裴风丽 于 2018-06-01 设计创作，主要内容包括：本申请实施例提供的半导体器件及其制造方法。所述半导体器件包括：衬底；设置于衬底上的半导体层；半导体层上设置有源极、栅极和漏极,其中源极和漏极与半导体层欧姆接触；栅极与漏极之间,及栅极与源极之间设置有介质层,所述介质层位于所述半导体层之上；栅极与半导体层及栅极与介质层之间设置有隔离层。通过在栅极与漏极之间,及栅极与源极之间设置介质层,并在栅极与半导体层,及栅极与介质层之间设置隔离层。通过上述设置的隔离层将在制造半导体器件过程中残留在所述介质层表面的污染物或空隙与所述栅极隔离开,大大增强了栅极能承受的电压和器件承受的击穿电压,提高半导体器件的整体可靠性。(the embodiment of the application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a substrate; a semiconductor layer disposed on the substrate; a source electrode, a grid electrode and a drain electrode are arranged on the semiconductor layer, wherein the source electrode and the drain electrode are in ohmic contact with the semiconductor layer; dielectric layers are arranged between the grid electrode and the drain electrode and between the grid electrode and the source electrode, and the dielectric layers are positioned on the semiconductor layer; isolation layers are arranged between the grid and the semiconductor layer and between the grid and the dielectric layer. By arranging the dielectric layers between the grid and the drain and between the grid and the source, and arranging the isolation layers between the grid and the semiconductor layer and between the grid and the dielectric layers. The isolating layer isolates pollutants or gaps remained on the surface of the dielectric layer in the process of manufacturing the semiconductor device from the grid electrode, so that the voltage born by the grid electrode and the breakdown voltage born by the device are greatly enhanced, and the overall reliability of the semiconductor device is improved.)

1. a semiconductor device, characterized in that the semiconductor device comprises:

A substrate;

A semiconductor layer disposed on the substrate;

A source electrode, a gate electrode, and a drain electrode disposed on the semiconductor layer, wherein the source electrode and the drain electrode are in ohmic contact with the semiconductor layer;

The dielectric layers are arranged between the grid electrode and the drain electrode and between the grid electrode and the source electrode, and are positioned on the semiconductor layer;

And the isolation layer is arranged between the grid electrode and the semiconductor layer and between the grid electrode and the dielectric layer.

2. The semiconductor device of claim 1, wherein the dielectric layer comprises a recess for receiving the gate, the isolation layer covers at least an inner wall of the recess, and the gate partially or completely covers the isolation layer.

3. The semiconductor device according to claim 1, wherein when the gate is an insulated gate, the isolation layer contains a metal.

4. the semiconductor device according to any one of claims 1 to 3, wherein a thickness of the spacer is not less than 5nm and not more than 1/10 a of the gate length.

5. The semiconductor device according to claim 1, wherein the metal of the gate is one of Ni, a combination of Ni and another metal.

6. The semiconductor device of claim 1, wherein when the gate is an insulated gate, the isolation layer is comprised of a dielectric comprising one or more of Al ₂ O ₃, AlON, SiN, SiON, SiO ₂, HfAlO, TiO2, NiO, HfO ₂, AlN, SiAlN, BN, and graphene.

7. The semiconductor device according to claim 1, wherein when the gate is a schottky gate, the isolation layer is formed of a semiconductor or a metal.

8. The semiconductor device according to claim 7, wherein when the isolation layer is a metal, a work function thereof is larger than a work function of the semiconductor layer.

9. The semiconductor device according to claim 7, wherein when the isolation layer is a semiconductor, a difference between a band gap of the isolation layer and a band gap of a semiconductor layer in contact with the isolation layer is equal to or larger than a predetermined difference.

10. The semiconductor device according to claim 1, wherein the isolation layer is a single-layer or multi-layer structure.

11. The semiconductor device of claim 2, wherein a cross-sectional shape of the recess comprises one of a rectangle, a trapezoid, an arc, or a combination thereof.

12. A method of manufacturing a semiconductor device, the method comprising:

Forming a semiconductor layer on a surface of a substrate;

Forming a dielectric layer on the surface of the semiconductor layer far away from the substrate;

Forming a source electrode and a drain electrode which are in ohmic contact with the semiconductor layer on the surface of the semiconductor layer far away from the substrate;

Processing the dielectric layer to form a groove;

Depositing an isolation layer with a preset thickness to cover the groove;

And forming a grid electrode in the groove.

13. The method of claim 12, wherein during the formation of the dielectric layer on the surface of the semiconductor layer away from the substrate, the dielectric layer is formed in-situ by chemical vapor deposition of a metal organic compound or molecular beam epitaxy, or at least one of low pressure chemical vapor deposition, atomic layer deposition, or plasma enhanced chemical vapor deposition.

Technical Field

The present disclosure relates to the field of semiconductor and semiconductor manufacturing technologies, and in particular, to a semiconductor device and a manufacturing method thereof.

background

in a planar channel field effect Transistor (fet) of a High Electron Mobility Transistor (HEMT), such as a gallium nitride HEMT (GaN HEMT) and a gallium arsenide HEMT (GaAs HEMT), which includes a Source (Source, S), a Gate (Gate, G) and a Drain (Drain, D), an electric field is concentrated at an edge of the Gate close to the Drain, forming an electric field spike. When the voltage applied between the gate and drain is increased in steps and the electric field at the peak of this electric field spike is caused to be higher than the critical electric field of the semiconductor material, the device breaks down and fails. Meanwhile, as the breakdown voltage (bearing) borne by the device is the integral of the electric field between the grid electrode and the drain electrode, compared with an evenly distributed electric field, the sharper the peak value of the electric field peak of the device at the edge of the grid electrode is, the smaller the breakdown voltage borne by the device is.

In the actual design and manufacturing process of the device, the grid electrode and the surface dielectric layer are both positioned on the semiconductor layer, and in the process of manufacturing the grid electrode, a groove needs to be etched in the surface dielectric layer firstly, then the grid electrode is deposited in the groove, and the grid electrode is in direct contact with the surface dielectric layer. In the process of etching the groove, pollutants such as impurity particles and the like are inevitably formed on the inner wall of the groove, the inner wall of the groove is rough, after the grid is deposited in the groove, the pollutants such as the impurity particles and the like exist between the grid and the surface dielectric layer, and the defects such as gaps (the gap in the dielectric layer can reduce the performance of the grid when the gap moves to the grid) and the like also exist.

disclosure of Invention

in view of the above, the present application is directed to a semiconductor device and a method for manufacturing the same, so as to solve the above-mentioned problems.

In a first aspect, an embodiment of the present application provides a semiconductor device, including:

a substrate;

a semiconductor layer disposed on the substrate;

a source electrode, a gate electrode, and a drain electrode disposed on the semiconductor layer, wherein the source electrode and the drain electrode are in ohmic contact with the semiconductor layer;

The dielectric layers are arranged between the grid electrode and the drain electrode and between the grid electrode and the source electrode, and are positioned on the semiconductor layer;

And the isolation layer is arranged between the grid electrode and the semiconductor layer and between the grid electrode and the dielectric layer.

Optionally, in this embodiment, the dielectric layer includes a groove for accommodating the gate, the isolation layer at least covers an inner wall of the groove, and the gate partially or completely covers the isolation layer.

Optionally, in this embodiment, when the gate is an insulated gate, the isolation layer contains a metal.

Optionally, in this embodiment, the metal of the gate is one of Ni, a combination of Ni and other metals.

Optionally, in this embodiment, when the gate is an insulated gate, the isolation layer is composed of a dielectric including one or more of Al ₂ O ₃, AlON, SiN, SiON, SiO ₂, HfAlO, TiO ₂, NiO, HfO ₂, AlN, SiAlN, BN, and graphene.

Optionally, in this embodiment, when the gate is an insulated gate, the isolation layer contains a metal.

Optionally, in this embodiment, when the gate is a schottky gate, the isolation layer is made of a semiconductor or a metal.

Optionally, in this embodiment, when the isolation layer is made of metal, the work function of the isolation layer is larger than that of the semiconductor layer.

optionally, in this embodiment, when the isolation layer is a semiconductor, a forbidden bandwidth of the isolation layer is equivalent to a forbidden bandwidth of a semiconductor layer in contact with the isolation layer or a difference between the forbidden bandwidths is greater than a preset difference.

Optionally, in this embodiment, the isolation layer is a single-layer or multi-layer structure.

optionally, in this embodiment, the thickness of the isolation layer is not less than 5nm and not greater than 1/10 of the gate length.

Optionally, in this embodiment, a groove for accommodating the gate is formed between the dielectric layer between the gate and the drain and the dielectric layer between the gate and the source, and a cross-sectional shape of the groove along a direction perpendicular to the semiconductor layer includes one of a rectangle, a trapezoid, and an arc, or a combination thereof.

in a second aspect, embodiments of the present application further provide a manufacturing method for manufacturing the semiconductor device in the first aspect, the method including:

forming a semiconductor layer on the surface of the substrate;

Forming a dielectric layer on the surface of the semiconductor layer far away from the substrate;

Forming a source electrode and a drain electrode which are in ohmic contact with the semiconductor layer on the surface of the semiconductor layer far away from the substrate;

Processing the dielectric layer to form a groove;

Depositing an isolation layer with a preset thickness to cover the groove;

And forming a grid electrode in the groove.

Optionally, in this embodiment, in the process of forming the dielectric layer on the surface of the semiconductor layer away from the substrate, the dielectric layer is generated in situ by using chemical vapor deposition of a metal organic compound or molecular beam epitaxy, or the dielectric layer is generated by using at least one of a low-pressure chemical vapor deposition method, an atomic layer deposition method, or a plasma-enhanced chemical vapor deposition method.

the embodiment of the application provides a semiconductor device and a manufacturing method thereof. By arranging the dielectric layers between the grid and the drain and between the grid and the source, and arranging the isolation layers between the grid and the semiconductor layer and between the grid and the dielectric layers. The isolating layer isolates pollutants or gaps remained on the surface of the dielectric layer in the process of manufacturing the semiconductor device from the grid electrode, so that the voltage born by the grid electrode and the breakdown voltage born by the device are greatly enhanced, and the overall reliability of the semiconductor device is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the application and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.

Fig. 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

FIGS. 2A-2F are schematic views of various alternative structures of the semiconductor device of FIG. 1;

Fig. 3 is a schematic flow chart of manufacturing the semiconductor device in fig. 1 according to an embodiment of the present disclosure.

Fig. 4A-4F are process diagrams of the semiconductor device of fig. 1 according to the present embodiment.

Icon: 10-a semiconductor device; 11-a substrate; 12-a semiconductor layer; 13-a source electrode; 14-a drain electrode; 15-a gate; 16-a dielectric layer; 17-an isolation layer; 171-a first isolation layer; 172-second barrier layer.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the described embodiments are merely a few embodiments of the present application and not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

In the description of the present invention, it should be noted that the terms "upper", "lower", and the like refer to orientations or positional relationships based on the orientations or positional relationships shown in the drawings or orientations or positional relationships that the products of the present invention are conventionally placed in use, and are used for convenience in describing the present invention and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.

Referring to fig. 1, fig. 1 illustrates a schematic structural diagram of a semiconductor device 10 according to an embodiment of the present disclosure. The semiconductor device 10 includes a substrate 11, a semiconductor layer 12, a gate electrode 15, a source electrode 13, a drain electrode 14, a dielectric layer 16, and an isolation layer 17. The semiconductor layer 12 is formed on the upper surface of the substrate 11, and the gate electrode 15, the source electrode 13, and the drain electrode 14 are disposed on a side of the semiconductor layer 12 away from the substrate 11. Wherein the source and drain electrodes 13 and 14 are in ohmic contact with the semiconductor layer 12.

the dielectric layer 16 is disposed on a side of the semiconductor layer 12 away from the substrate 11, and the dielectric layer 16 is located between the gate 15 and the drain 14, and between the gate 15 and the source 13. The isolation layer 17 isolates the gate electrode 15 from the semiconductor layer 12, and the isolation layer 17 also isolates the gate electrode 15 from the dielectric layer 16.

in this embodiment, a recess is disposed on the dielectric layer 16, the gate 15 is located in the recess, and the isolation layer 17 is disposed between the recess and the gate 15. The provision of the spacer 17 blocks impurities, voids, etc. in the recess from contacting the gate 15, reducing the possibility of the dielectric layer 16 or voids in the recess moving to the gate 15. Therefore, the technical problems that the grid 15 is easy to fall off and burn off under the condition of long-time work at high temperature are solved, the voltage born by the grid 15 and the breakdown voltage born by the semiconductor device 10 are increased, and the overall reliability of the semiconductor device 10 is improved.

In this embodiment, the material of the substrate 11 may be one of sapphire, silicon carbide, silicon, lithium titanate, silicon-on-insulator, gallium nitride, or aluminum nitride.

The material of the semiconductor layer 12 may be GaN, SiC, or GaAs. The semiconductor layer 12 may include a channel layer and a barrier layer, the interface of which is formed with a conductive channel, which are well known in the art and will not be described in detail herein. When the material of the semiconductor layer 12 is GaN, the semiconductor layer 12 may include a GaN channel layer and an AlGaN barrier layer.

The dielectric layer 16 is of a single-layer or multi-layer structure, wherein the dielectric layer 16 is one or more of SiN, SiO ₂, SiON, Al ₂ O ₃, HfO ₂, HfAlO, AlN, BN, graphene and the like, and the portion which is in contact with the semiconductor layer 12 is preferably SiN or AlN.

In an embodiment of the present application, the metal of the gate 15 may be one of Ni or a combination of Ni and other metals. The gate electrode 15 may be made of Ni and another metal, or the gate electrode 15 may be made of Ni and another metal. Taking Ni and a single metal Au as an example to form the gate electrode 15, in the process of forming the gate electrode 15, a layer of Ni may be plated first, and then a layer of Au may be plated after the Ni plating, so as to finally form the gate electrode 15.

In the embodiment of the present application, the gate 15 of the semiconductor device 10 may be a schottky gate or an insulated gate. When the Schottky gate is adopted, the gate metal is directly contacted with the semiconductor, and the formed contact is Schottky contact; when the gate is an insulated gate, the gate metal and the semiconductor are not in direct contact, and a dielectric layer is formed between the gate metal and the semiconductor.

When the gate electrode 15 is a schottky gate, the isolation layer 17 may be a semiconductor or a metal. When the isolation layer 17 is a semiconductor, the forbidden bandwidth (Band gap) of the semiconductor in the isolation layer 17 can be equivalent to that of the semiconductor in the semiconductor layer 12 in contact therewith, such as: GaN, AlGaN, AlN, the forbidden bandwidth of the semiconductor in the isolation layer 17 may also be different from that of the semiconductor in the semiconductor layer 12, that is, the forbidden bandwidth of the isolation layer 17 and the forbidden bandwidth of the semiconductor layer 12 in contact with the isolation layer 17 are greater than a preset difference, such as: the particular choice of Si depends on the requirements of the device to be fabricated. When the spacer 17 is a metal, it has a work function larger than that of the semiconductor in the semiconductor layer 12, and Ni, Pt, and Mo are preferable. The forbidden band width is a band gap width (unit is electron volt (ev)), the energy of electrons in a solid cannot be continuously taken, but is discontinuous energy bands, free electrons or holes exist for conduction, the energy band where the free electrons exist is called a conduction band (energy conduction), and the energy band where the free holes exist is called a valence band (energy conduction). The bound electron must acquire enough energy to transition from the valence band to the conduction band to become a free electron or hole, and the minimum value of this energy is the forbidden bandwidth.

when the gate electrode 15 is an insulated gate, the isolation layer 17 is composed of a dielectric including one or more of Al ₂ O ₃, AlON, SiN, SiON, SiO ₂, HfAlO, TiO ₂, NiO, HfO ₂, AlN, SiAlN, BN, and graphene, and the isolation layer 17 may have a single-layer structure or a multi-layer structure.

In this embodiment, the thickness of the isolation layer 17 should be appropriate, the advantage of the isolation barrier is not obvious when the thickness of the isolation layer 17 is too thin, and the performance of the gate 15 may be affected or even reduced when the thickness of the isolation layer 17 is too thick. Preferably, in this embodiment, the spacer 17 is no less than 5nm thick and no greater than 1/10 a of the gate length.

in this embodiment, the recess is used to accommodate the gate 15, the isolation layer 17 at least covers the inside of the recess, and the gate 15 partially or completely covers the isolation layer 17. Next, various modified structures of the semiconductor device 10 provided in the present embodiment will be described.

Referring to fig. 2A, fig. 2A is substantially the same as the semiconductor device 10 provided in fig. 1, except that in fig. 2A, the isolation layer 17 is completely covered by the gate 15. In fig. 2A, the gate 15 may have a trapezoid shape or an arc shape, and in this embodiment, the trapezoid shape, and the isolation layer 17 is completely covered by the gate 15, so that the influence of the defect, such as a contamination particle or a void, on the gate 15 can be reduced, and the performance of the gate 15 can be improved.

Referring to fig. 2B, fig. 2B provides a semiconductor device 10 substantially the same as fig. 2A, except that the isolation layer 17 is not completely covered by the gate 15, and the isolation layer 17 covers the dielectric layer 16, so as to further reduce the influence of the recess etching process on the performance of the semiconductor device 10.

Referring to fig. 2C, fig. 2C is a modification of fig. 2B, in fig. 2C, the shape of the groove may be an inverted trapezoid, so that the shape of the groove can reduce the peak electric field at the edge of the gate 15, and improve the voltage endurance of the gate 15.

Referring to fig. 2D, the cross-sectional shape of the groove in fig. 2D perpendicular to the semiconductor layer 12 is a combination of a rectangle and an inverted trapezoid, and the groove is located in the semiconductor layer 12, so that the frequency characteristic of the gate 15 can be improved.

Referring to fig. 2E and 2F, fig. 2E and 2F show schematic diagrams of the isolation layer 17 having a multi-layer structure when the gate 15 is an insulated gate, and taking the isolation layer 17 as a two-layer structure as an example, the isolation layer 17 includes a first isolation layer 171 and a second isolation layer 172. Specifically, in fig. 2E, a second isolation layer 172 is added on the basis of an isolation layer 17 (corresponding to the first isolation layer 171 in fig. 2E) in comparison with fig. 1, wherein the material of the second isolation layer 172 may be the same as the material of the dielectric layer 16, or may be formed by using a dielectric different from the material of the dielectric layer 16. The above arrangement can further reduce the influence of the defects such as impurity particles and voids in the groove on the gate electrode 15, and can also be used as a gate dielectric of the insulated gate. The isolation layer 17 in fig. 2F is also a two-layer structure, that is, the isolation layer 17 in fig. 2F includes a first isolation layer 171 and a second isolation layer 172, and compared with fig. 2E, the first isolation layer 171 covers a part of the dielectric layer 16, and when the semiconductor device in fig. 2F is manufactured, the part of the first isolation layer 171 covered on the dielectric layer 16 does not need to be disposed, and the semiconductor device in fig. 2F is manufactured with fewer process steps than the semiconductor device in fig. 2E, which is more cost-effective.

Referring to fig. 3, the present embodiment further provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device 10 of the above embodiment, and the method includes the following specific steps:

In step S310, referring to fig. 4A, a semiconductor layer 12 is formed on the surface of the substrate 11.

In step S320, referring to fig. 4B, a dielectric layer 16 is formed on the surface of the semiconductor layer 12 away from the substrate 11.

The dielectric layer 16 may be grown a single time or multiple times. In the present embodiment, the dielectric layer 16 is formed by performing in-situ growth by Metal-organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE), or by growing by Low Pressure Chemical Vapor Deposition (LPCVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), or by a combination thereof. Compared with the prior art, the in-situ grown dielectric layer has better passivation effect, and is beneficial to reducing the current collapse effect of the device and reducing the leakage current. Therefore, in this embodiment, it may be preferable to perform in-situ growth of the dielectric layer 16.

In step S330, referring to fig. 4C, a source 13 and a drain 14 are formed on the surface of the semiconductor layer 12 away from the substrate 11, wherein the source 13 and the drain 14 are in ohmic contact with the semiconductor layer 12.

In step S340, referring to fig. 4D, the dielectric layer 16 is processed to form a groove.

in step S350, referring to fig. 4E, an isolation layer 17 with a predetermined thickness is deposited to cover the groove.

In step S360, referring to fig. 4F, a gate 15 is formed in the recess.

In summary, the semiconductor device and the manufacturing method thereof provided by the embodiments of the present application are provided. By arranging the dielectric layers between the grid and the drain and between the grid and the source, and arranging the isolation layers between the grid and the semiconductor layer and between the grid and the dielectric layers. The isolating layer isolates pollutants or gaps remained on the surface of the dielectric layer in the process of manufacturing the semiconductor device from the grid electrode, so that the voltage born by the grid electrode and the breakdown voltage born by the device are greatly enhanced, and the overall reliability of the semiconductor device is improved.

the above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.