阅读说明：本技术 一种射频毫米波亚采样级联的dac反馈锁相环 (Cascaded DAC feedback phase-locked loop of radio frequency millimeter wave subsampling ) 是由 刘马良 肖金海 朱樟明 杨银堂 于 2019-07-25 设计创作，主要内容包括：本发明涉及一种射频毫米波亚采样级联的DAC反馈锁相环,包括：第一级锁相环和第二级锁相环,其中,所述第一级锁相环用于实现m分频的功能,包括分频模块和数字模拟转换器,所述分频模块用于对输入信号进行分频,分频后的信号作为所述数字模拟转换器的时钟信号,所述数字模拟转换器作为反馈电路根据所述时钟信号输出第一反馈信号；所述第二级锁相环用于实现n分频的功能；所述第二级锁相环的输入端与所述第一级锁相环的输出端连接,使得所述DAC反馈锁相环实现m*n分频的功能,其中m、n均为≥1的整数。(the invention relates to a radio frequency millimeter wave sub-sampling cascaded DAC feedback phase-locked loop, which comprises: the frequency division module is used for dividing the frequency of an input signal, the divided signal is used as a clock signal of the digital-to-analog converter, and the digital-to-analog converter is used as a feedback circuit to output a first feedback signal according to the clock signal; the second-stage phase-locked loop is used for realizing the function of n frequency division; the input end of the second-stage phase-locked loop is connected with the output end of the first-stage phase-locked loop, so that the DAC feedback phase-locked loop realizes the function of m x n frequency division, wherein m and n are integers which are not less than 1.)

1. a cascaded DAC feedback phase-locked loop of radio frequency millimeter wave subsampling, comprising: a first stage phase locked loop (1) and a second stage phase locked loop (2), wherein,

the first-stage phase-locked loop (1) is used for realizing the function of m frequency division, and comprises a frequency division module (106) and a digital-to-analog converter (107), wherein the frequency division module (106) is used for dividing the frequency of an input signal, the divided signal is used as a clock signal of the digital-to-analog converter (107), and the digital-to-analog converter (107) is used as a feedback circuit to output a first feedback signal according to the clock signal;

The second-stage phase-locked loop (2) is used for realizing the function of n frequency division;

the input end of the second-stage phase-locked loop (2) is connected with the output end of the first-stage phase-locked loop (1), so that the DAC feedback phase-locked loop realizes the function of m x n frequency division, wherein m and n are integers which are not less than 1.

2. the cascaded DAC feedback phase-locked loop of claim 1, wherein the first stage phase-locked loop (1) comprises a first sub-sampling phase detector (101), a first amplifier (102), a first voltage/current conversion amplifier (103), a first low-pass filter (104), a first voltage-controlled oscillator (105), the frequency-dividing module (106) and the digital-to-analog converter (107) connected in sequence to form a loop, wherein,

The first sub-sampling phase detector (101) is used for generating a first phase difference signal according to an external reference signal and the first feedback signal output by the digital-to-analog converter (107), the first phase difference signal sequentially passes through the first amplifier (102), the first voltage/current conversion amplifier (103) and the first low-pass filter (104) to obtain a first control signal, and the first control signal adjusts the frequency of an output signal of the first voltage-controlled oscillator (105).

3. The RF millimeter wave sub-sampled cascaded DAC feedback phase-locked loop of claim 2, wherein the second stage phase-locked loop (2) comprises a second sub-sampled phase detector (201), a second amplifier (202), a second voltage/current conversion amplifier (203), a second low-pass filter (204) and a second voltage-controlled oscillator (205) connected in sequence to form a loop, wherein,

The input end of the second sub-sampling phase detector (201) is connected with the output end of the first voltage-controlled oscillator (105);

The second sub-sampling phase detector (201) is configured to generate a second phase difference signal according to the output signal of the first voltage-controlled oscillator (105) and a second feedback signal output by the second voltage-controlled oscillator (205), where the second phase difference signal sequentially passes through the second amplifier (202), the second voltage/current conversion amplifier (203), and the second low-pass filter (204) to obtain a second control signal, the second control signal adjusts the frequency of the output signal of the second voltage-controlled oscillator (205), and the output signal of the second voltage-controlled oscillator (205) is used as the output signal of the DAC feedback phase-locked loop.

4. The cascaded DAC feedback phase-locked loop of claim 3, wherein the first sub-sampling phase detector (101) and the second sub-sampling phase detector (201) have the same structure and each comprise: a first NMOS transistor (Mn1), a second NMOS transistor (Mn2), a third NMOS transistor (Mn3), a fourth NMOS transistor (Mn4), a fifth NMOS transistor (Mn5), a sixth NMOS transistor (Mn6), a seventh NMOS transistor (Mn7), an eighth NMOS transistor (Mn8), a ninth NMOS transistor (Mn9), a tenth NMOS transistor (Mn10), an eleventh NMOS transistor (Mn11), a twelfth NMOS transistor (Mn12), a first capacitor (C1), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a first selector (MUX1) and a second selector (MUX2), wherein,

The source electrode of the first NMOS tube (Mn1) serves as a first input end (In1) and is connected with the source electrode of the fourth NMOS tube (Mn4), the drain electrode of the first NMOS tube (Mn1) is connected with the source electrode of the second NMOS tube (Mn2), and the gate electrode of the first NMOS tube (Mn1) serves as a second input end (In 2);

the drain electrode of the second NMOS transistor (Mn2) is respectively connected with the source electrode of the second NMOS transistor (Mn2) and the first selector (MUX1), the gate electrode of the second NMOS transistor (Mn2) serves as a third input end (In3), and the first capacitor (C1) is connected between the drain electrode of the second NMOS transistor (Mn2) and a ground end (GND);

The source electrode of the third NMOS transistor (Mn3) is connected with the source electrode of the fifth NMOS transistor (Mn5), the drain electrode of the third NMOS transistor (Mn3) is connected with the source electrode of the second NMOS transistor (Mn2), and the gate electrode of the third NMOS transistor (Mn3) is connected with the ground terminal (GND);

the drain electrode of the fourth NMOS transistor (Mn4) is connected with the drain electrode of the fifth NMOS transistor (Mn5), and the gate electrode of the fourth NMOS transistor (Mn4) is connected with the ground terminal (GND);

The source electrode of the fifth NMOS transistor (Mn5) serves as a fourth input end (In4) and is connected with the source electrode of the seventh NMOS transistor (Mn7), the drain electrode of the fifth NMOS transistor (Mn5) is connected with the source electrode of the sixth NMOS transistor (Mn6), and the gate electrode of the fifth NMOS transistor (Mn5) serves as a fifth input end (In 5);

the drain electrode of the sixth NMOS transistor (Mn6) is respectively connected with the source electrode of the sixth NMOS transistor (Mn6) and the second selector (MUX2), the gate electrode of the sixth NMOS transistor (Mn6) serves as a sixth input end (In6), and the second capacitor (C2) is connected between the drain electrode of the sixth NMOS transistor (Mn6) and a ground end (GND);

The drain electrode of the seventh NMOS transistor (Mn7) is connected with the source electrode of the eighth NMOS transistor (Mn8), and the gate electrode of the seventh NMOS transistor (Mn7) serves as a seventh input end (In 7);

the drain electrode of the eighth NMOS transistor (Mn8) is connected to the source electrode of the eighth NMOS transistor (Mn8) and the first selector (MUX1), respectively, the gate electrode of the eighth NMOS transistor (Mn8) serves as an eighth input terminal (In8), and the third capacitor (C3) is connected between the drain electrode of the eighth NMOS transistor (Mn8) and a ground terminal (GND);

the source electrode of the ninth NMOS transistor (Mn9) is used as a ninth input end (In9) and is connected with the source electrode of the eleventh NMOS transistor (Mn11), the drain electrode of the ninth NMOS transistor (Mn9) is connected with the source electrode of the eighth NMOS transistor (Mn8), and the gate electrode of the ninth NMOS transistor (Mn9) is connected with the ground end (GND);

The source electrode of the tenth NMOS transistor (Mn10) is connected with the source electrode of the seventh NMOS transistor (Mn7), the drain electrode of the tenth NMOS transistor (Mn10) is connected with the drain electrode of the eleventh NMOS transistor (Mn11), and the gate electrode of the tenth NMOS transistor (Mn10) is connected with the ground terminal (GND);

the drain electrode of the eleventh NMOS tube (Mn11) is connected with the source electrode of the twelfth NMOS tube (Mn12), and the gate electrode of the eleventh NMOS tube (Mn11) serves as a tenth input end (In 10);

The drain electrode of the twelfth NMOS tube (Mn12) is respectively connected with the source electrode of the twelfth NMOS tube (Mn12) and the second selector (MUX2), the gate electrode of the twelfth NMOS tube (Mn12) serves as an eleventh input end (In11), and the fourth capacitor (C4) is connected between the drain electrode of the twelfth NMOS tube (Mn12) and the ground end (GND);

The first selector (MUX1) and the second selector (MUX2) both input the reference signal.

5. the DAC feedback phase-locked loop of the radio frequency millimeter wave sub-sampling cascade of claim 4, wherein In the first sub-sampling phase detector (101), the first input terminal (In1), the fourth input terminal (In4) and the ninth input terminal (In9) input the first feedback signal, the first feedback signal is a differential signal, the phase difference between the input signal of the first input terminal (In1) and the input signal of the fourth input terminal (In4) is 180 degrees, and the phase of the input signals of the first input terminal (In1) and the ninth input terminal (In9) is the same;

the reference signals are input to the second input terminal (In2), the third input terminal (In3), the fifth input terminal (In5), the sixth input terminal (In6), the seventh input terminal (In7), the eighth input terminal (In8), the tenth input terminal (In10), and the eleventh input terminal (In11), the reference signals are differential signals, the phases of the input signals to the second input terminal (In2), the fifth input terminal (In5), the eighth input terminal (In8), and the eleventh input terminal (In11) are the same, the phases of the input signals to the third input terminal (In3), the sixth input terminal (In6), the seventh input terminal (In7), and the tenth input terminal (In10) are the same, and the phase difference between the two signals is 180 °.

6. The DAC feedback phase-locked loop of the radio frequency millimeter wave sub-sampling cascade of claim 4, wherein In the second sub-sampling phase detector (201), the first input terminal (In1), the fourth input terminal (In4) and the ninth input terminal (In9) input the second feedback signal, the second feedback signal is a differential signal, the phase difference between the input signal of the first input terminal (In1) and the input signal of the fourth input terminal (In4) is 180 degrees, and the phase of the input signals of the first input terminal (In1) and the ninth input terminal (In9) is the same;

the second input terminal (In2), the third input terminal (In3), the fifth input terminal (In5), the sixth input terminal (In6), the seventh input terminal (In7), the eighth input terminal (In8), the tenth input terminal (In10), and the eleventh input terminal (In11) input the output signal of the first voltage-controlled oscillator (105), the output signal of the first voltage-controlled oscillator (105) is a differential signal, the phases of the input signals of the second input terminal (In2), the fifth input terminal (In5), the eighth input terminal (In8), and the eleventh input terminal (In11) are the same, the phases of the input signals of the third input terminal (In3), the sixth input terminal (In6), the seventh input terminal (In7), and the tenth input terminal (In10) are the same, and the phase difference between the two signals is 180 °.

Technical Field

The invention belongs to the technical field of analog-digital hybrid integrated circuits, and particularly relates to a radio frequency millimeter wave sub-sampling cascaded DAC feedback phase-locked loop.

Background

The phase-locked loop is a feedback loop of a locked phase, and is a typical feedback control circuit, which uses an externally input reference signal to control the frequency and phase of an internal oscillation signal of the loop, so as to realize automatic tracking of an output signal frequency to an input signal frequency, and is generally used for a closed-loop tracking circuit. Poor spurious and phase noise can cause the spectrum aliasing of adjacent channel signals, and the signal-to-noise ratio is reduced, and with the development of 5G, the frequency and phase noise requirements of the phase-locked loop are higher and higher in the industry.

The structure of a conventional Phase-locked loop is shown in fig. 1, and its main modules include a Phase Detector (PD), a low-pass filter, and a voltage-controlled oscillator (VCO). The phase detector has two input signals, which are respectively a reference signal and an output signal of the VCO, converts a phase difference signal of the reference signal and the output signal of the VCO into a voltage signal, and transmits the voltage signal to the low-pass filter, and after the low-pass filter filters out high-frequency noise, the remaining signal is a control signal of the VCO. Therefore, the output signal of the phase-locked loop is continuously compared with the reference signal after frequency division, and then the oscillation frequency of the VCO is changed until the frequencies of the two signals are the same, so that the phase-locked loop enters a locked state. In the locked state, the change of the VCO output caused by external interference can be timely fed back to the control voltage of the VCO for timely correction, and finally a stable output signal is obtained.

Commonly used Phase detectors include a multiplier type Phase Detector, an exclusive or gate type Phase Detector, a timing type Phase Detector, and a Phase Frequency Detector (PFD). The frequency difference existing between input signals of the PFD can contribute to output signals, the capturing process of a loop is accelerated, the loop is not limited by a capturing range, and the frequency discrimination range is-2 pi and 2 pi. Considering a circuit using a passive lead-lag network together with a PFD, when the initial frequency of the VCO is different, its transmission characteristic will include a pole located at s-0, which is helpful for capturing the loop, but in this case, the gain of the PFD varies with the average output of the low-pass filter, and when the initial frequency of the VCO is different, the average output of the low-pass filter is also different, which is generally solved by adopting a structure of the PFD and a charge pump, but the mismatch of the charge and discharge currents of the charge pump may cause the generation of spurs in the phase-locked loop.

In addition, in the conventional phase-locked loop, a frequency divider is introduced for frequency multiplication of signals, and due to the introduction of the frequency divider, phase noise is amplified by N²and this phase noise is difficult to overcome over a long period of time. After the traditional phase-locked loop introduces the sub-sampling phase discriminator, a frequency divider in a high-frequency range can be omitted, so that the phase-locked loop can be applied in a higher-frequency range, and if the phase-locked loop is applied in a lower frequency, the phase-locked loop is easy to lock other harmonic components of a set frequency, and a frequency-locked loop is additionally added.

disclosure of Invention

In order to solve the problems in the prior art, the invention provides a radio frequency millimeter wave sub-sampling cascaded DAC feedback phase-locked loop. The technical problem to be solved by the invention is realized by the following technical scheme:

The invention provides a radio frequency millimeter wave sub-sampling cascaded DAC feedback phase-locked loop, which comprises: a first stage phase locked loop and a second stage phase locked loop, wherein,

The first-stage phase-locked loop is used for realizing the function of m frequency division and comprises a frequency division module and a digital-to-analog converter, wherein the frequency division module is used for dividing the frequency of an input signal, the divided signal is used as a clock signal of the digital-to-analog converter, and the digital-to-analog converter is used as a feedback circuit to output a first feedback signal according to the clock signal;

the second-stage phase-locked loop is used for realizing the function of n frequency division;

the input end of the second-stage phase-locked loop is connected with the output end of the first-stage phase-locked loop, so that the DAC feedback phase-locked loop realizes the function of m x n frequency division, wherein m and n are integers which are not less than 1.

in one embodiment of the present invention, the first stage phase locked loop includes a first sub-sampling phase detector, a first amplifier, a first voltage/current conversion amplifier, a first low pass filter, a first voltage controlled oscillator, the frequency division module, and the digital-to-analog converter, which are connected in sequence to form a loop, wherein,

the first sub-sampling phase discriminator is used for generating a first phase difference signal according to an external reference signal and the first feedback signal output by the digital-to-analog converter, the first phase difference signal sequentially passes through the first amplifier, the first voltage/current conversion amplifier and the first low-pass filter to obtain a first control signal, and the first control signal adjusts the frequency of an output signal of the first voltage-controlled oscillator.

In one embodiment of the invention, the second stage phase locked loop comprises a second sub-sampling phase detector, a second amplifier, a second voltage/current conversion amplifier, a second low pass filter and a second voltage controlled oscillator, which are connected in sequence to form a loop, wherein,

the input end of the second sub-sampling phase discriminator is connected with the output end of the first voltage-controlled oscillator;

The second sub-sampling phase detector is configured to generate a second phase difference signal according to the output signal of the first voltage-controlled oscillator and a second feedback signal output by the second voltage-controlled oscillator, where the second phase difference signal sequentially passes through the second amplifier, the second voltage/current conversion amplifier, and the second low-pass filter to obtain a second control signal, the second control signal adjusts the frequency of the output signal of the second voltage-controlled oscillator, and the output signal of the second voltage-controlled oscillator is used as the output signal of the DAC feedback phase-locked loop.

In an embodiment of the present invention, the first sub-sampling phase detector and the second sub-sampling phase detector have the same structure, and both include: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first selector and a second selector, wherein,

The source electrode of the first NMOS tube is used as a first input end and is connected with the source electrode of the fourth NMOS tube, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the first NMOS tube is used as a second input end;

The drain electrode of the second NMOS tube is respectively connected with the source electrode of the second NMOS tube and the first selector, the grid electrode of the second NMOS tube is used as a third input end, and the first capacitor is connected between the drain electrode of the second NMOS tube and a ground end;

the source electrode of the third NMOS tube is connected with the source electrode of the fifth NMOS tube, the drain electrode of the third NMOS tube is connected with the source electrode of the second NMOS tube, and the grid electrode of the third NMOS tube is connected with the grounding end;

The drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the grounding end;

The source electrode of the fifth NMOS tube is used as a fourth input end and is connected with the source electrode of the seventh NMOS tube, the drain electrode of the fifth NMOS tube is connected with the source electrode of the sixth NMOS tube, and the grid electrode of the fifth NMOS tube is used as a fifth input end;

The drain electrode of the sixth NMOS tube is respectively connected with the source electrode of the sixth NMOS tube and the second selector, the grid electrode of the sixth NMOS tube is used as a sixth input end, and the second capacitor is connected between the drain electrode of the sixth NMOS tube and the ground end;

the drain electrode of the seventh NMOS tube is connected with the source electrode of the eighth NMOS tube, and the grid electrode of the seventh NMOS tube is used as a seventh input end;

the drain electrode of the eighth NMOS tube is respectively connected with the source electrode of the eighth NMOS tube and the first selector, the grid electrode of the eighth NMOS tube is used as an eighth input end, and the third capacitor is connected between the drain electrode of the eighth NMOS tube and the ground end;

a source electrode of the ninth NMOS tube is used as a ninth input end and is connected with a source electrode of the eleventh NMOS tube, a drain electrode of the ninth NMOS tube is connected with a source electrode of the eighth NMOS tube, and a grid electrode of the ninth NMOS tube is connected with a grounding end;

The source electrode of the tenth NMOS tube is connected with the source electrode of the seventh NMOS tube, the drain electrode of the tenth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the grid electrode of the tenth NMOS tube is connected with the ground terminal;

the drain electrode of the eleventh NMOS tube is connected with the source electrode of the twelfth NMOS tube, and the grid electrode of the eleventh NMOS tube is used as a tenth input end;

The drain electrode of the twelfth NMOS tube is respectively connected with the source electrode of the twelfth NMOS tube and the second selector, the grid electrode of the twelfth NMOS tube is used as an eleventh input end, and the fourth capacitor is connected between the drain electrode of the twelfth NMOS tube and the ground end;

the first selector and the second selector both input the reference signal.

in one embodiment of the present invention, in the first sub-sampling phase detector, the first input terminal, the fourth input terminal and the ninth input terminal input the first feedback signal, the first feedback signal is a differential signal, the phase difference between the input signal at the first input terminal and the input signal at the fourth input terminal is 180 °, and the phase of the input signals at the first input terminal and the ninth input terminal is the same;

The reference signal is input to the second input end, the third input end, the fifth input end, the sixth input end, the seventh input end, the eighth input end, the tenth input end, and the eleventh input end, the reference signal is a differential signal, the phases of the input signals of the second input end, the fifth input end, the eighth input end, and the eleventh input end are the same, the phases of the input signals of the third input end, the sixth input end, the seventh input end, and the tenth input end are the same, and the phase difference between the two signals is 180 °.

In an embodiment of the present invention, in the second sub-sampling phase detector, the first input terminal, the fourth input terminal and the ninth input terminal input the second feedback signal, the second feedback signal is a differential signal, a phase difference between an input signal at the first input terminal and an input signal at the fourth input terminal is 180 °, and phases of input signals at the first input terminal and the ninth input terminal are the same;

The second input end, the third input end, the fifth input end, the sixth input end, the seventh input end, the eighth input end, the tenth input end, and the eleventh input end input an output signal of the first voltage-controlled oscillator, the output signal of the first voltage-controlled oscillator is a differential signal, input signals of the second input end, the fifth input end, the eighth input end, and the eleventh input end have the same phase, input signals of the third input end, the sixth input end, the seventh input end, and the tenth input end have the same phase, and a phase difference between the two signals is 180 °.

compared with the prior art, the invention has the beneficial effects that:

The invention relates to a radio frequency millimeter wave sub-sampling cascaded DAC feedback phase-locked loop which is provided with two stages of phase-locked loops connected in series, wherein a first stage phase-locked loop is used as a feedback loop by introducing a digital-analog converter, and a frequency division module is used for dividing the frequency of an output signal of the first stage phase-locked loop and then using the frequency divided output signal as a clock signal of the digital-analog converter, so that the first stage phase-locked loop can achieve the frequency division effect of m, the output of the first stage phase-locked loop directly samples an oscillator of a second stage phase-locked loop, the second stage phase-locked loop can achieve the frequency division effect of n, and the.

The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.

Drawings

Fig. 1 is a schematic structural diagram of a conventional phase-locked loop according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a feedback phase-locked loop of a radio frequency millimeter wave sub-sampling cascaded DAC according to an embodiment of the present invention;

fig. 3 is a circuit structure diagram of a sub-sampling phase detector according to an embodiment of the present invention;

Fig. 4 is a circuit diagram of a voltage/current conversion amplifier according to an embodiment of the present invention;

Fig. 5 is a schematic structural diagram of a low-pass filter according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a voltage controlled oscillator according to an embodiment of the present invention.

Detailed Description

in order to further explain the technical means and effects of the present invention adopted to achieve the predetermined object, a rf millimeter wave sub-sampling cascaded DAC feedback phase-locked loop according to the present invention is described in detail below with reference to the accompanying drawings and the detailed description.

the foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.