阅读说明：本技术 有机发光显示装置、制造其的方法和用于其的像素电路 (Organic light emitting display device, method of manufacturing the same, and pixel circuit for the same ) 是由 朴商镇 金永大 金贞善 李相振 李雅戀 于 2021-03-29 设计创作，主要内容包括：本发明涉及有机发光显示装置、制造其的方法和用于其的像素电路。该有机发光显示装置包括：有机发光二极管；驱动晶体管,被配置为控制从电力电压线到有机发光二极管的电流；补偿晶体管,被配置为响应于施加到补偿晶体管的补偿栅电极的电压而使驱动晶体管二极管连接；以及栅绝缘层,置于驱动晶体管的驱动有源区与驱动栅电极之间以及补偿晶体管的补偿有源区与补偿栅电极之间。栅绝缘层的在驱动有源区与驱动栅电极之间的第一部分中的介电常数大于栅绝缘层的在补偿有源区与补偿栅电极之间的第二部分中的介电常数。(The present invention relates to an organic light emitting display device, a method of manufacturing the same, and a pixel circuit used for the same. The organic light emitting display device includes: an organic light emitting diode; a driving transistor configured to control a current from a power voltage line to the organic light emitting diode; a compensation transistor configured to diode-connect the driving transistor in response to a voltage applied to a compensation gate electrode of the compensation transistor; and a gate insulating layer interposed between the driving active region of the driving transistor and the driving gate electrode and between the compensation active region of the compensation transistor and the compensation gate electrode. A dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode is greater than a dielectric constant of a second portion of the gate insulating layer between the compensation active region and the compensation gate electrode.)

1. An organic light emitting display device comprising:

an organic light emitting diode;

a first transistor configured to control an amount of current flowing from a second node connected to a power voltage line to the organic light emitting diode in response to a voltage applied to a first node connected to a first gate electrode of the first transistor;

a third transistor connected between the first node and a third node between the first transistor and the organic light emitting diode and configured to diode-connect the first transistor in response to a voltage applied to a third gate electrode of the third transistor; and

a gate insulating layer interposed between the first active region of the first transistor and the first gate electrode and between the third active region of the third transistor and the third gate electrode,

wherein a dielectric constant in a first portion of the gate insulating layer between the first active region and the first gate electrode is greater than a dielectric constant in a second portion of the gate insulating layer between the third active region and the third gate electrode.

2. The organic light emitting display device according to claim 1, wherein the second portion overlaps with the third gate electrode and the third active region.

3. The organic light-emitting display device according to claim 1, wherein an area of the second portion is the same as an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the third gate electrode.

4. The organic light-emitting display device according to claim 1, wherein an area of the second portion is larger than an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the third gate electrode.

5. The organic light emitting display device according to claim 1, wherein the gate insulating layer comprises silicon oxide, and a number of oxygen atoms per unit volume in the second portion is larger than a number of oxygen atoms per unit volume in the first portion.

6. An organic light-emitting display device according to claim 1, wherein the gate insulating layer comprises silicon oxide and the second portion comprises fluorine or carbon.

7. The organic light emitting display device of claim 1, further comprising:

a fourth transistor connected between the first node and a fourth voltage line and configured to initialize a voltage of the first gate electrode in response to a voltage applied to a fourth gate electrode of the fourth transistor;

wherein the gate insulating layer is interposed between a fourth active region of the fourth transistor and the fourth gate electrode,

wherein the dielectric constant in the first portion of the gate insulating layer between the first active region and the first gate electrode is greater than the dielectric constant in a third portion of the gate insulating layer between the fourth active region and the fourth gate electrode.

8. An organic light emitting display device according to claim 7, wherein the third portion overlaps with the fourth gate electrode and the fourth active region.

9. The organic light-emitting display device according to claim 7, wherein an area of the third portion is the same as an area of a portion of the fourth gate electrode overlapping with the fourth active region when viewed from a direction perpendicular to an upper surface of the fourth gate electrode.

10. The organic light-emitting display device according to claim 7, wherein an area of the third portion is larger than an area of a portion of the fourth gate electrode overlapping with the fourth active region when viewed from a direction perpendicular to an upper surface of the fourth gate electrode.

11. The organic light-emitting display device according to claim 7, wherein the gate insulating layer comprises silicon oxide, and a number of oxygen atoms per unit volume in the third portion is larger than a number of oxygen atoms per unit volume in the first portion.

12. An organic light-emitting display device according to claim 7, wherein the gate insulating layer comprises silicon oxide and the third portion comprises fluorine or carbon.

13. The organic light emitting display device of claim 1, further comprising:

a seventh transistor connected between the organic light emitting diode and a fourth voltage line and configured to initialize a voltage of a pixel electrode of the organic light emitting diode in response to a voltage applied to a seventh gate electrode of the seventh transistor,

wherein the gate insulating layer is interposed between a seventh active region of the seventh transistor and the seventh gate electrode,

wherein the dielectric constant in the first portion of the gate insulating layer between the first active region and the first gate electrode is greater than a dielectric constant in a fifth portion of the gate insulating layer between the seventh active region and the seventh gate electrode.

14. An organic light-emitting display device according to claim 13, wherein the fifth portion overlaps with the seventh gate electrode and the seventh active region.

15. The organic light-emitting display device according to claim 13, wherein an area of the fifth portion is the same as an area of a portion of the seventh gate electrode overlapping with the seventh active region when viewed from a direction perpendicular to an upper surface of the seventh gate electrode.

16. The organic light-emitting display device according to claim 13, wherein an area of the fifth portion is larger than an area of a portion of the seventh gate electrode overlapping with the seventh active region when viewed from a direction perpendicular to an upper surface of the seventh gate electrode.

17. The organic light-emitting display device according to claim 13, wherein the gate insulating layer comprises silicon oxide, and a number of oxygen atoms per unit volume in the fifth portion is larger than a number of oxygen atoms per unit volume in the first portion.

18. An organic light-emitting display device according to claim 13, wherein the gate insulating layer comprises silicon oxide and the fifth portion comprises fluorine or carbon.

19. A method of manufacturing an organic light emitting display device, the method comprising:

forming a semiconductor layer including a first active region and a third active region over a substrate;

forming a gate insulating layer covering the semiconductor layer;

implanting oxygen ions, fluorine ions, or carbon ions into a second portion of the gate insulating layer corresponding to the third active region;

forming a first gate electrode corresponding to the first active region and a third gate electrode corresponding to the third active region on the gate insulating layer to form a first transistor including the first active region and the first gate electrode and configured to control an amount of current flowing to an organic light emitting diode and a third transistor including the third active region and the third gate electrode and configured to diode-connect the first transistor in response to a voltage applied to the third gate electrode; and is

Forming the organic light emitting diode electrically connected to the first transistor.

20. The method of claim 19, wherein the first and second portions are selected from the group consisting of,

wherein the forming of the semiconductor layer comprises:

forming a semiconductor layer including the first active region, the third active region and a fourth active region over the substrate,

wherein the implanting of the oxygen ions, the fluorine ions, or the carbon ions comprises:

implanting the oxygen ions, the fluorine ions, or the carbon ions into the second portion of the gate insulating layer corresponding to the third active region and a third portion of the gate insulating layer corresponding to the fourth active region,

wherein the forming of the first transistor and the third transistor comprises:

forming the first gate electrode corresponding to the first active region, the third gate electrode corresponding to the third active region, and a fourth gate electrode corresponding to the fourth active region on the gate insulating layer to form the first transistor including the first active region and the first gate electrode and configured to control the amount of the current flowing to the organic light emitting diode, the third transistor including the third active region and the third gate electrode and configured to diode-connect the first transistor in response to the voltage applied to the third gate electrode, and a fourth transistor including the fourth active region and the fourth gate electrode and configured to initialize a voltage of the first gate electrode in response to a voltage applied to the fourth gate electrode.

21. The method of claim 19, wherein the forming of the gate insulating layer comprises:

forming the gate insulating layer including silicon oxide.

22. The method of claim 19, wherein the second portion overlaps the third gate electrode and the third active region.

23. The method according to claim 19, wherein an area of the second portion is the same as an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the semiconductor layer.

24. The method according to claim 19, wherein an area of the second portion is larger than an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the semiconductor layer.

25. A method of manufacturing an organic light emitting display device, the method comprising:

forming a semiconductor layer including a first active region and a third active region over a substrate;

forming a gate insulating layer covering the semiconductor layer;

implanting silicon ions into a first portion of the gate insulating layer corresponding to the first active region;

forming a first gate electrode corresponding to the first active region and a third gate electrode corresponding to the third active region on the gate insulating layer to form a first transistor including the first active region and the first gate electrode and configured to control an amount of current flowing to an organic light emitting diode and a third transistor including the third active region and the third gate electrode and configured to diode-connect the first transistor in response to a voltage applied to the third gate electrode; and is

Forming the organic light emitting diode electrically connected to the first transistor.

26. The method of claim 25, wherein the implanting of the silicon ions comprises:

implanting the silicon ions into a portion of the gate insulating layer other than a second portion of the gate insulating layer, the second portion corresponding to the third active region.

27. The method of claim 25, wherein the forming of the semiconductor layer comprises:

forming a semiconductor layer including the first active region, the third active region and a fourth active region over the substrate,

wherein the implanting of the silicon ions comprises:

implanting the silicon ions into a portion of the gate insulating layer other than a second portion and a third portion of the gate insulating layer, wherein the second portion corresponds to the third active region and the third portion corresponds to the fourth active region,

wherein the forming of the first transistor and the third transistor comprises:

forming the first gate electrode corresponding to the first active region, the third gate electrode corresponding to the third active region, and a fourth gate electrode corresponding to the fourth active region on the gate insulating layer to form the first transistor including the first active region and the first gate electrode and configured to control the amount of the current flowing to the organic light emitting diode, the third transistor including the third active region and the third gate electrode and configured to diode-connect the first transistor in response to the voltage applied to the third gate electrode, and a fourth transistor including the fourth active region and the fourth gate electrode and configured to initialize a voltage of the first gate electrode in response to a voltage applied to the fourth gate electrode.

28. The method of claim 25, wherein the forming of the gate insulating layer comprises:

forming the gate insulating layer including silicon oxide in which the number of oxygen atoms included per unit volume is 1.9 times or more the number of silicon atoms included per unit volume.

29. The method of claim 26, wherein the second portion of the gate insulating layer overlaps the third gate electrode and the third active region.

30. The method according to claim 26, wherein an area of the second portion of the gate insulating layer is the same as an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the semiconductor layer.

31. The method according to claim 26, wherein an area of the second portion of the gate insulating layer is larger than an area of a portion of the third gate electrode overlapping with the third active region when viewed from a direction perpendicular to an upper surface of the semiconductor layer.

32. A pixel circuit for an organic light emitting display device, comprising:

a driving transistor configured to control a current flowing from the power voltage line to the organic light emitting diode;

a compensation transistor configured to diode-connect the driving transistor in response to a voltage applied to a compensation gate electrode of the compensation transistor; and

a gate insulating layer interposed between a driving active region of the driving transistor and a driving gate electrode of the driving transistor and between a compensation active region of the compensation transistor and the compensation gate electrode,

wherein a dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode is greater than a dielectric constant of a second portion of the gate insulating layer between the compensation active region and the compensation gate electrode.

33. The pixel circuit according to claim 32, wherein an area of the second portion is the same as an area of a portion of the compensation gate electrode that overlaps the compensation active region.

34. The pixel circuit according to claim 32, wherein an area of the second portion is larger than an area of a portion of the compensation gate electrode overlapping the compensation active region.

Technical Field

The present disclosure relates to an organic light emitting display device and a method of manufacturing the same, and more particularly, to an organic light emitting display device capable of displaying high quality images and a method of manufacturing the same.

Background

Display devices such as Flat Panel Displays (FPDs) are electronic devices that people use to view content (e.g., still/moving images). FPD devices are lighter, thinner, and use less power than conventional Cathode Ray Tube (CRT) devices. The display device includes a plurality of pixels, wherein each pixel includes a display element and a pixel circuit for controlling an electric signal transmitted to the display element. The pixel circuit includes one or more transistors. The transistor may include a compensation transistor and a driving transistor. However, in a specific case, the compensation transistor is a cause of occurrence of a kickback voltage at the gate node of the driving transistor, which causes an afterimage to be perceived. Therefore, there is a need to improve the quality of images generated by display devices including pixel circuits.

Disclosure of Invention

According to an exemplary embodiment of the present disclosure, an organic light emitting display device includes an organic light emitting diode, a driving transistor, a compensation transistor, and a gate insulating layer. The driving transistor is configured to control an amount of current flowing from a second node connected to the power voltage line to the organic light emitting diode in response to a voltage applied to a first node connected to the driving gate electrode. The compensation transistor is connected between the third node and the first node, and is configured to diode-connect the driving transistor in response to a voltage applied to the compensation gate electrode. The third node is between the driving transistor and the organic light emitting diode. The gate insulating layer is interposed between the driving active region of the driving transistor and the driving gate electrode of the driving transistor and between the compensation active region of the compensation transistor and the compensation gate electrode. A dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode is greater than a dielectric constant of a second portion of the gate insulating layer between the compensation active region and the compensation gate electrode.

The second portion may overlap the compensation gate electrode and the compensation active region.

The area of the second portion may be the same as the area of a portion of the compensation gate electrode overlapping the compensation active region when viewed from a direction perpendicular to the upper surface of the compensation gate electrode.

The area of the second portion may be larger than the area of a portion of the compensation gate electrode overlapping the compensation active region when viewed from a direction perpendicular to the upper surface of the compensation gate electrode.

The gate insulating layer may include silicon oxide, and the number of oxygen atoms per unit volume in the second portion may be greater than the number of oxygen atoms per unit volume in the first portion.

The gate insulating layer may include silicon oxide, and the second portion may include fluorine or carbon.

The organic light emitting display device may further include an initialization transistor connected between the first node and an initialization voltage line and configured to initialize a voltage of the driving gate electrode in response to a voltage applied to the initialization gate electrode, wherein a gate insulating layer may be interposed between the initialization active region and the initialization gate electrode of the initialization transistor, wherein a dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode may be greater than a dielectric constant of a third portion of the gate insulating layer between the initialization active region and the initialization gate electrode.

The third portion may overlap the initialization gate electrode and the initialization active region.

The area of the third portion may be the same as the area of a portion of the initialization gate electrode overlapping the initialization active region when viewed from a direction perpendicular to the upper surface of the initialization gate electrode.

The area of the third portion may be larger than the area of a portion of the initialization gate electrode overlapping the initialization active region when viewed from a direction perpendicular to the upper surface of the initialization gate electrode.

The gate insulating layer may include silicon oxide, and the number of oxygen atoms per unit volume in the third portion may be greater than the number of oxygen atoms per unit volume in the first portion.

The gate insulating layer may include silicon oxide, and the third portion may include fluorine or carbon.

The organic light emitting display device may further include a second initializing transistor connected between the organic light emitting diode and an initializing voltage line and configured to initialize a voltage of a pixel electrode of the organic light emitting diode in response to a voltage applied to the second initializing gate electrode, wherein a gate insulating layer may be interposed between the second initializing active region of the second initializing transistor and the second initializing gate electrode, wherein a dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode may be greater than a dielectric constant of a fifth portion of the gate insulating layer between the second initializing active region and the second initializing gate electrode.

The fifth portion may overlap the second initializing gate electrode and the second initializing active region.

The area of the fifth portion may be the same as the area of a portion of the second initializing gate electrode overlapping with the second initializing active area when viewed from a direction perpendicular to the upper surface of the second initializing gate electrode.

The area of the fifth portion may be larger than that of a portion of the second initializing gate electrode overlapping the second initializing active area when viewed from a direction perpendicular to the upper surface of the second initializing gate electrode.

The gate insulating layer may include silicon oxide, and the number of oxygen atoms per unit volume in the fifth portion may be greater than the number of oxygen atoms per unit volume in the first portion.

The gate insulating layer may include silicon oxide, and the fifth portion may include fluorine or carbon.

According to an exemplary embodiment of the present disclosure, a method of manufacturing an organic light emitting display device includes: (i) forming a semiconductor layer including a driving active region and a compensation active region over a substrate; (ii) forming a gate insulating layer covering the semiconductor layer; (iii) implanting oxygen ions, fluorine ions, or carbon ions into a second portion of the gate insulating layer corresponding to the compensation active region; (iv) forming a driving gate electrode corresponding to the driving active region and a compensation gate electrode corresponding to the compensation active region on the gate insulating layer to form a driving transistor including the driving active region and the driving gate electrode and configured to control an amount of current flowing to the organic light emitting diode and a compensation transistor including the compensation active region and the compensation gate electrode and configured to diode-connect the driving transistor in response to a voltage applied to the compensation gate electrode; and (v) forming an organic light emitting diode electrically connected to the driving transistor.

The forming of the semiconductor layer may include: forming a semiconductor layer including a driving active region, a compensation active region, and an initialization active region over a substrate, wherein the implantation of oxygen ions, fluorine ions, or carbon ions may include: implanting oxygen ions, fluorine ions, or carbon ions into a second portion of the gate insulating layer corresponding to the compensation active region and a third portion of the gate insulating layer corresponding to the initialization active region, wherein the forming of the driving transistor and the compensation transistor may include: a driving gate electrode corresponding to the driving active region, a compensation gate electrode corresponding to the compensation active region, and an initialization gate electrode corresponding to the initialization active region are formed on the gate insulating layer to form a driving transistor including the driving active region and the driving gate electrode and configured to control an amount of current flowing to the organic light emitting diode, a compensation transistor including the compensation active region and the compensation gate electrode and configured to diode-connect the driving transistor in response to a voltage applied to the compensation gate electrode, and an initialization transistor including the initialization active region and the initialization gate electrode and configured to initialize a voltage of the driving gate electrode in response to a voltage applied to the initialization gate electrode.

The forming of the gate insulating layer may include: a gate insulating layer including silicon oxide is formed.

According to an exemplary embodiment of the present disclosure, a method of manufacturing an organic light emitting display device includes: (i) forming a semiconductor layer including a driving active region and a compensation active region over a substrate; (ii) forming a gate insulating layer covering the semiconductor layer; (iii) implanting silicon ions into a first portion of the gate insulating layer corresponding to the driving active region; (iv) forming a driving gate electrode corresponding to the driving active region and a compensation gate electrode corresponding to the compensation active region on the gate insulating layer to form a driving transistor including the driving active region and the driving gate electrode and configured to control an amount of current flowing to the organic light emitting diode and a compensation transistor including the compensation active region and the compensation gate electrode and configured to diode-connect the driving transistor in response to a voltage applied to the compensation gate electrode; and (v) forming an organic light emitting diode electrically connected to the driving transistor.

The implanting of the silicon ions may include: silicon ions are implanted into a portion other than a second portion of the gate insulating layer, the second portion corresponding to the compensation active region.

The forming of the semiconductor layer may include: forming a semiconductor layer including a driving active region, a compensation active region, and an initialization active region over a substrate, wherein the implanting of the silicon ions may include: implanting silicon ions into portions of the gate insulating layer other than the second portion and the third portion of the gate insulating layer, wherein the second portion may correspond to the compensation active region, and the third portion may correspond to the initialization active region, wherein the forming of the driving transistor and the compensation transistor may include: a driving gate electrode corresponding to the driving active region, a compensation gate electrode corresponding to the compensation active region, and an initialization gate electrode corresponding to the initialization active region are formed on the gate insulating layer to form a driving transistor including the driving active region and the driving gate electrode and configured to control an amount of current flowing to the organic light emitting diode, a compensation transistor including the compensation active region and the compensation gate electrode and configured to diode-connect the driving transistor in response to a voltage applied to the compensation gate electrode, and a fourth transistor including the initialization active region and the initialization gate electrode and configured to initialize a voltage of the driving gate electrode in response to a voltage applied to the initialization gate electrode.

The forming of the gate insulating layer may include: a gate insulating layer including silicon oxide in which the number of oxygen atoms included per unit volume is 1.9 times or more the number of silicon atoms included per unit volume is formed.

The second portion may overlap the compensation gate electrode and the compensation active region.

The area of the second portion of the gate insulating layer may be the same as the area of a portion of the compensation gate electrode overlapping the compensation active region when viewed from a direction perpendicular to the upper surface of the semiconductor layer.

The area of the second portion of the gate insulating layer may be larger than the area of a portion of the compensation gate electrode overlapping the compensation active region when viewed from a direction perpendicular to the upper surface of the semiconductor layer.

According to an exemplary embodiment of the present disclosure, a pixel circuit for an organic light emitting display device includes: a driving transistor, a compensation transistor, and a gate insulating layer. The driving transistor is configured to control a current flowing from the power voltage line to the organic light emitting diode. The compensation transistor is configured to diode connect the drive transistor in response to a voltage applied to a compensation gate electrode of the compensation transistor. The gate insulating layer is interposed between the driving active region of the driving transistor and the driving gate electrode of the driving transistor and between the compensation active region of the compensation transistor and the compensation gate electrode. A dielectric constant of a first portion of the gate insulating layer between the driving active region and the driving gate electrode is greater than a dielectric constant of a second portion of the gate insulating layer between the compensation active region and the compensation gate electrode.

In an embodiment, the area of the second portion is the same as the area of the portion of the compensation gate electrode overlapping the compensation active region. In an embodiment, the area of the second portion is larger than the area of the portion of the compensation gate electrode overlapping the compensation active region.

Drawings

The above and other aspects, features and elements of particular embodiments of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic conceptual diagram illustrating a display device according to an exemplary embodiment of the present disclosure;

fig. 2 is an equivalent circuit diagram illustrating a pixel included in the display device of fig. 1 according to an exemplary embodiment of the present disclosure;

fig. 3 is a schematic layout diagram illustrating the positions of a thin film transistor and a storage capacitor in the pixel of fig. 2 according to an exemplary embodiment of the present disclosure;

fig. 4 is a schematic layout diagram illustrating the semiconductor layer of fig. 3, according to an exemplary embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view illustrating a portion of FIG. 3 according to an exemplary embodiment of the present disclosure;

fig. 6 is a schematic cross-sectional view illustrating a portion of a display device according to an exemplary embodiment of the present disclosure; and is

Fig. 7 is a schematic cross-sectional view illustrating a portion of a display device according to an exemplary embodiment of the present disclosure.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Like reference numerals refer to like elements throughout the drawings and the description. In this regard, the present invention may be in different forms and should not necessarily be construed as limited to the description set forth herein. Accordingly, several exemplary embodiments described below by referring to the drawings are used to explain aspects of the description. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b and c" means all or a variation of only a, only b, only c, both a and b, both a and c, both b and c, a, b and c.

Since the present disclosure is susceptible to various modifications and alternative embodiments, specific embodiments will be shown in the drawings and described in the written description. The effects and features of one or more embodiments and methods of accomplishing the same will become apparent from the following detailed description of one or more embodiments when taken in conjunction with the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not necessarily be limited to the exemplary embodiments set forth herein.

In the embodiments described below, when a layer, film, region, or panel is referred to as being "on" another layer, film, region, or panel, the layer, film, region, or panel can be directly or indirectly on the other layer, film, region, or panel. That is, for example, there may be intervening layers, films, regions, or plates. The size of components in the drawings may be exaggerated or reduced for convenience of description. For example, since the sizes and thicknesses of components in the drawings may be illustrated for convenience of description, the following embodiments are not necessarily limited thereto.

In the embodiments described below, when the wiring is referred to as "extending in the first direction or the second direction", the wiring may extend in a straight line shape, or may extend in a zigzag or curved line in the first direction or the second direction.

In the embodiments described below, the phrase "in a plan view" refers to a case where the target portion is viewed from above, and the phrase "in a sectional view" refers to a case where a vertical section of the target portion is viewed from a side. In the embodiments described below, when a first component is referred to as being "overlapped" with a second component, the first component may be disposed above or below the second component.

Fig. 1 is a schematic conceptual diagram of a display device 1 according to an exemplary embodiment of the present disclosure.

The display device 1 according to the present embodiment may be implemented as an electronic device such as a smart phone, a mobile phone, a navigation device, a game machine, a Television (TV), a vehicle body, a notebook computer, a laptop computer, a tablet computer, a Personal Media Player (PMP), a Personal Digital Assistant (PDA), or the like. Further, the electronic device may be a flexible device.

As shown in fig. 1, the display device 1 according to the present embodiment has a display area DA and a peripheral area PA. The peripheral area PA may surround the display area DA. In the embodiment, the display area DA includes pixels for displaying an image, and the peripheral area PA does not include pixels. The display device 1 may include a substrate 101 (refer to fig. 5), and the shape of the substrate 101 is not limited to the rectangular shape (on the xy plane) shown in fig. 1, and may have various shapes such as a circular shape. Further, the substrate 101 may have a bending region and be bent in the bending region. For example, the display device 1 may be bendable.

The substrate 101 may include glass or metal. In addition, the substrate 101 may include various flexible or bendable materials. For example, the substrate 101 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

In an exemplary embodiment, the substrate 101 has a multilayer structure including two layers including the polymer resin described above and a barrier layer including an inorganic material between the two layers. For example, the barrier layer may include silicon oxide, silicon nitride, and/or silicon oxynitride.

A plurality of display elements may be arranged in the display area DA. For example, the display element may be an organic light emitting diode, and may emit red, green, blue, or white light. The (sub) pixels in the display area DA of the display device 1 of fig. 1 comprise such organic light emitting diodes and further comprise thin film transistors and capacitors configured to control the extent to which the organic light emitting diodes emit light.

Drivers and wirings (or lines) such as power supply wirings may be arranged in the peripheral area PA. In addition, the peripheral area PA may include a pad area, which is an area to which various electronic devices such as a driving Integrated Circuit (IC) or a printed circuit board are electrically attached. The pad region may include a pad (e.g., a conductive element). Various wirings for transmitting electrical signals to the display area DA, the printed circuit board, or the driving IC may be attached to the pads.

Fig. 2 is an equivalent circuit diagram illustrating (sub) pixels in the display area DA of the display device 1 of fig. 1 according to an exemplary embodiment of the present disclosure. A (sub-) pixel may refer to a pixel or a sub-pixel.

Referring to fig. 2, the (sub) pixel SPX includes an organic light emitting diode OLED as a display element and a pixel circuit PC (or a pixel circuit portion) connected to the organic light emitting diode OLED. The pixel circuit PC may include a plurality of thin film transistors and a storage capacitor Cst. For example, the thin film transistor may include first to seventh transistors T1 to T7. The first terminal of each of the first to seventh transistors T1 to T7 may be a source terminal or a drain terminal, and the second terminal of each of the first to seventh transistors T1 to T7 may be different from the first terminal, according to the type (p-type or n-type) of the transistor and/or the operating condition. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal. In an embodiment, the first to seventh transistors T1 to T7 may be implemented by p-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or p-channel metal oxide semiconductor (PMOS) transistors.

The first transistor T1 may be referred to as a driving transistor (or a driving thin film transistor). The second transistor T2 may be referred to as a switching transistor (or a switching thin film transistor). The third transistor T3 may be referred to as a compensation transistor (or a compensation thin film transistor). The fourth transistor T4 may be referred to as a first initialization transistor (or a first initialization thin film transistor). The fifth transistor T5 may be referred to as an operation control transistor (or an operation control thin film transistor). The sixth transistor T6 may be referred to as an emission control transistor (or an emission control thin film transistor). The seventh transistor T7 may be referred to as a second initialization transistor (or a second initialization thin film transistor). The thin film transistor and the storage capacitor Cst may be connected to signal lines (e.g., a scan line SL, a previous scan line SL-1, a next scan line SL +1, an emission control line EL, and a data line DL), a first initialization voltage line VL1, a second initialization voltage line VL2, and a power voltage line PL.

The signal lines (e.g., the scan line SL, the previous scan line SL-1, the next scan line SL +1, the emission control line EL, and the data line DL) may include a scan line SL configured to transmit a scan signal Sn, a previous scan line SL-1 configured to transmit the previous scan signal Sn-1 to the first initializing thin film transistor T4, a next scan line SL +1 configured to transmit the scan signal Sn to the second initializing thin film transistor T7, an emission control line EL configured to transmit the emission control signal En to the operation controlling thin film transistor T5 and the emission controlling thin film transistor T6, and a data line DL crossing the scan line SL and configured to transmit a data signal Dm. The power voltage line PL may be configured to transmit the driving voltage ELVDD to the driving thin film transistor T1. The first initializing voltage line VL1 may be configured to transmit an initializing voltage Vint to the first initializing thin film transistor T4. The second initializing voltage line VL2 may be configured to transmit the initializing voltage Vint to the second initializing thin film transistor T7. As shown in fig. 2 and 3, the first and second initializing voltage lines VL1 and VL2 may appear as the same line, i.e., the initializing voltage line VL. Specifically, fig. 3 shows a layout diagram of pixels in an nth row, and the first initialization voltage line VL1 in the nth row may be the second initialization voltage line VL2 in an n-1 th row.

The driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst. The driving source region S1 of the driving thin film transistor T1 is connected to the power voltage line PL by the operation control thin film transistor T5. The driving drain region D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission controlling thin film transistor T6. That is, in response to a voltage applied to the first node N1 (e.g., a voltage applied to the driving gate electrode G1), the driving thin film transistor T1 may control an amount of current flowing from the second node N2 connected to the power voltage line PL to the organic light emitting diode OLED. Accordingly, the driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and drives the current I_OLEDTo the organic light emitting diode OLED. The operation controlling thin film transistor T5 may be interposed between the second node N2 and the power voltage line PL.

The switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL. The switching source region S2 of the switching thin film transistor T2 is connected to the data line DL. The switching drain region D2 of the switching thin film transistor T2 is connected to the second node N2, and thus to the driving source region S1 of the driving thin film transistor T1, and is also connected to the power voltage line PL through the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the scan signal Sn received through the scan line SL to perform a switching operation for transmitting the data signal Dm transmitted through the data line DL to the driving source region S1 of the driving thin film transistor T1.

The compensation thin film transistor T3 may be connected between the third node N3 and the first node N1 between the driving thin film transistor T1 and the organic light emitting diode OLED to diode-connect the driving thin film transistor T1 in response to a voltage applied to the compensation gate electrode G3 of the compensation thin film transistor T3. The compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL. The compensation source region S3 of the compensation thin film transistor T3 is connected to the driving drain region D1 of the driving thin film transistor T1, and is also connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The compensation drain region D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain region D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on according to the scan signal Sn received through the scan line SL to electrically connect the driving gate electrode G1 and the driving drain region D1 of the driving thin film transistor T1 and diode-connect the driving thin film transistor T1.

The first initializing thin film transistor T4 may be connected between the first node N1 and the first initializing voltage line VL1 to initialize the voltage of the driving gate electrode G1 in response to the voltage applied to the first initializing gate electrode G4. The first initializing gate electrode G4 of the first initializing thin film transistor T4 is connected to the previous scan line SL-1. The first initializing source region S4 of the first initializing thin film transistor T4 is connected to the first initializing voltage line VL 1. The first initialization drain region D4 of the first initialization thin film transistor T4 is connected to the lower electrode CE1 of the storage capacitor Cst, the compensation drain region D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initializing thin film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SL-1 to perform an initializing operation for initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting an initializing voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

The operation control thin film transistor T5 may be connected between the second node N2 and the power voltage line PL, and turned on in response to a voltage applied to the operation control gate electrode G5. The operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL. The operation control source region S5 of the operation control thin film transistor T5 is connected to the power voltage line PL. The operation control drain region D5 of the operation control thin film transistor T5 is connected to the driving source region S1 of the driving thin film transistor T1 and the switching drain region D2 of the switching thin film transistor T2.

The emission control thin film transistor T6 may be connected between the third node N3 and the organic light emitting diode OLED, and turned on in response to a voltage applied from the emission control line EL to the emission control gate electrode G6. The emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL. The emission control source region S6 of the emission control thin film transistor T6 is connected to the driving drain region D1 of the driving thin film transistor T1 and the compensation source region S3 of the compensation thin film transistor T3. The emission control drain region D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source region S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

When the operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on (or turned on during the same period) according to the emission control signal En received through the emission control line EL, the driving voltage ELVDD is transmitted to the organic light emitting diode OLED, so that the driving current I is driven_OLEDFlows through the organic light emitting diode OLED.

The second initializing gate electrode G7 of the second initializing thin film transistor T7 is connected to the next scan line SL + 1. The second initializing source region S7 of the second initializing thin film transistor T7 is connected to the emission control drain region D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED. The second initializing drain region D7 of the second initializing thin film transistor T7 is connected to the second initializing voltage line VL 2.

In an embodiment in which the scan line SL and the next scan line SL +1 are electrically connected to each other, the same scan signal Sn is applied to the scan line SL and the next scan line SL + 1. Accordingly, the second initializing thin film transistor T7 may be turned on according to the scan signal Sn received through the next scan line SL +1 to perform an operation of initializing the pixel electrode of the organic light emitting diode OLED. In an exemplary embodiment, the second initializing thin film transistor T7 is omitted.

The upper electrode CE2 of the storage capacitor Cst is connected to the power voltage line PL, and the common electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Accordingly, the organic light emitting diode OLED may receive the driving current I from the driving thin film transistor T1_OLEDAnd emits light, thereby displaying an image. In an exemplary embodiment, the common voltage ELVSS is less than the driving voltage ELVDD.

Although fig. 2 shows the compensation thin film transistor T3 and the first initialization thin film transistor T4 having the double gate electrodes, in other embodiments, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may have one gate electrode.

Fig. 3 is a schematic layout diagram illustrating positions of a plurality of thin film transistors T1 through T7 and a storage capacitor Cst in the (sub) pixel SPX of fig. 2 according to an exemplary embodiment of the present disclosure. Fig. 4 is a schematic layout view of a semiconductor layer 1130 that is part of the display device 1 of fig. 3. FIG. 5 is a cross-sectional view of a portion of FIG. 3 taken along lines A-A ', B-B', C-C ', and D-D'. The size of each component in the sectional views has been exaggerated and/or reduced for convenience. This also applies to the cross-sectional views described below.

A driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initialization thin film transistor T7 are disposed along the semiconductor layer 1130. Some regions of the semiconductor layer 1130 may constitute semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. That is, some regions of the semiconductor layer 1130 may constitute an active region, a source region, or a drain region of the thin film transistor.

The semiconductor layer 1130 may be on the substrate 101. The buffer layer 111 may be on the substrate 101, and the semiconductor layer 1130 may be on the buffer layer 111.

The buffer layer 111 may reduce or prevent penetration of foreign substances, moisture, or external air from the bottom of the substrate 101, and may provide a flat surface on the substrate 101. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material, and may have a single layer or a multi-layer structure of the inorganic material and the organic material. For example, the buffer layer 111 may have a structure in which a first buffer layer 111a and a second buffer layer 111b are stacked, and the first buffer layer 111a and the second buffer layer 111b may include materials different from each other. For example, the first buffer layer 111a may include silicon nitride, and the second buffer layer 111b may include silicon oxide.

As described above, in the embodiment in which the first buffer layer 111a includes a silicon nitride material, the silicon nitride material includes hydrogen. Accordingly, carrier mobility of the semiconductor layer 1130 disposed on the buffer layer 111 may be improved, and thus, electrical characteristics of the thin film transistor may be improved. In an embodiment, the semiconductor layer 1130 may include a silicon material. In this embodiment, the interface bonding characteristic between the semiconductor layer 1130 including silicon and the second buffer layer 111b including silicon oxide may be improved, and thus, the electrical characteristics of the thin film transistor may be improved.

The semiconductor layer 1130 may include Low Temperature Polysilicon (LTPS). The polysilicon material has high electron mobility (100 cm)²Vs or higher) and thus has low power consumption and excellent reliability. As another example, the semiconductor layer 1130 may include amorphous silicon (a-Si) and/or an oxide semiconductor. Alternatively, some of the semiconductor layers of the plurality of thin film transistors may include LTPS, and other some of the semiconductor layers may include a-Si and/or an oxide semiconductor.

The source and drain regions of the semiconductor layer 1130 may be doped with impurities, and the impurities may include N-type impurities or P-type impurities. The source region and the drain region may correspond to the source electrode and the drain electrode, respectively. The source region and the drain region may be exchanged with each other according to the properties of the thin film transistor. Hereinafter, the terms "source region" and "drain region" are used instead of the source electrode and the drain electrode. The equivalent circuit diagram of fig. 2 shows a specific portion of the semiconductor layer 1130 doped with P-type impurities to implement a thin film transistor as a P-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a P-channel metal oxide semiconductor (PMOS) transistor. Other portions of the semiconductor layer 1130 may also be doped with impurities to serve as wirings configured to electrically connect the thin film transistors T1 to T7 and/or the storage capacitor Cst to each other.

The first gate insulating layer 112 may be disposed on the semiconductor layer 1130, and the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL may be disposed on the first gate insulating layer 112. The first gate insulating layer 112 may be disposed on the buffer layer 111. The first gate insulating layer 112 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO).

Regions of the scan line SL overlapping with the second active region a2 of the switching thin film transistor T2 and the third active region A3 of the compensating thin film transistor T3 may be a switching gate electrode G2 and a compensating gate electrode G3, respectively. A region of the previous scan line SL-1 overlapping the fourth active region a4 of the first initializing thin film transistor T4 may be the first initializing gate electrode G4. A region of the next scan line SL +1 overlapping with the seventh active region a7 (e.g., the second initializing active region) of the second initializing thin film transistor T7 may be the second initializing gate electrode G7. Regions of the emission control line EL overlapping with the fifth active region a5 of the operation controlling thin film transistor T5 and the sixth active region a6 of the emission controlling thin film transistor T6 may be the operation controlling gate electrode G5 and the emission controlling gate electrode G6, respectively.

The driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a multi-layer or single-layer structure including the above-described materials. For example, the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL may have a multi-layered structure of Mo/Al, or may have a multi-layered structure of Mo/Al/Mo.

The second gate insulating layer 113 may be disposed on the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL. The second gate insulating layer 113 may be disposed on the first gate insulating layer 112. The second gate insulating layer 113 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO).

The electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL2 may be disposed on the second gate insulating layer 113. The electrode voltage line HL may cover at least a portion of the driving gate electrode G1, and may constitute a storage capacitor Cst together with the driving gate electrode G1. In an exemplary embodiment, the electrode voltage line HL completely covers the driving gate electrode G1.

The lower electrode CE1 of the storage capacitor Cst may be integrally formed with the driving gate electrode G1 of the driving thin film transistor T1. For example, the driving gate electrode G1 of the driving thin film transistor T1 may serve as the lower electrode CE1 of the storage capacitor Cst. A region of the electrode voltage line HL overlapping the driving gate electrode G1 may be an upper electrode CE2 of the storage capacitor Cst. Accordingly, the second gate insulating layer 113 may function as a dielectric layer of the storage capacitor Cst.

The electrode voltage line HL, the first initializing voltage line VL1, and the second initializing voltage line VL2 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a multi-layer or single-layer structure including the above-described materials. For example, the electrode voltage line HL, the first initializing voltage line VL1 and the second initializing voltage line VL2 may have a multi-layered structure of Mo/Al or may have a multi-layered structure of Mo/Al/Mo.

The interlayer insulating layer 115 is disposed on the electrode voltage line HL, the first initialization voltage line VL1, and the second initialization voltage line VL 2. An interlayer insulating layer 115 may be disposed on the second gate insulating layer 113. The interlayer insulating layer 115 may includeSilicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO).

The data line DL, the power voltage line PL, the first and second initialization link lines 1173a and 1173b, the node link line 1174, and the connection metal 1175 may be disposed on the interlayer insulating layer 115. The data line DL, the power voltage line PL, the node connection line 1174, and the connection metal 1175 may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and may have a multi-layer or single-layer structure including the above-described materials. For example, the data line DL, the power voltage line PL, the node connection line 1174, and the connection metal 1175 may have a multilayer structure of Ti/Al/Ti.

The data line DL may be connected to the switching source region S2 of the switching thin film transistor T2 through the contact hole 1154. A portion of the data line DL may correspond to the switching source region S2.

The power voltage line PL may be connected to the upper electrode CE2 of the storage capacitor Cst through a contact hole 1158 formed in the interlayer insulating layer 115. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the power voltage line PL. In addition, the power voltage line PL may be connected to the operation control source region S5 through the contact hole 1155.

The first initializing voltage line VL1 may be connected to the first initializing thin film transistor T4 through the first initializing link 1173a, and the second initializing voltage line VL2 may be connected to the second initializing thin film transistor T7 through the second initializing link 1173b and the contact holes 1151 and 1152. The first and second initializing voltage lines VL1 and VL2 may have the same constant voltage (e.g., -2V, etc.).

In an exemplary embodiment, one end of the node connection line 1174 is connected to the compensation drain electrode D3 through the contact hole 1156, and the other end is connected to the driving gate electrode G1 through the contact hole 1157.

The connection metal 1175 is connected to the sixth active region a6 of the emission control thin film transistor T6 through a contact hole 1153 passing through (e.g., penetrating) the interlayer insulating layer 115, the second gate insulating layer 113, and the first gate insulating layer 112. The connection metal 1175 is connected to the pixel electrode 210 of the organic light emitting diode OLED through the contact hole 1163. Accordingly, the emission control thin film transistor T6 may be electrically connected to the pixel electrode 210 of the organic light emitting diode OLED.

The planarization layer 117 may be disposed on the data line DL, the power voltage line PL, the first and second initialization link lines 1173a and 1173b, the node link line 1174, and the connection metal 1175. The organic light emitting diode OLED may be disposed on the planarization layer 117.

Although fig. 2 shows one pixel circuit PC and fig. 3 shows the structure of one (sub) pixel SPX, a plurality of (sub) pixels SPX having the same pixel circuit PC may be arranged in the first direction (x-direction) and the second direction (y-direction). The plurality of (sub) pixels SPX may share a line. For example, the first initializing voltage line VL1, the previous scan line SL-1, the second initializing voltage line VL2, and the next scan line SL +1 may be shared by two pixel circuits PC adjacent to each other in the second direction (y direction).

That is, the first initializing voltage line VL1 and the previous scanning line SL-1 may be electrically connected to the second initializing thin film transistor of another pixel circuit PC arranged above (direction + y) the pixel circuit PC of fig. 3 in the second direction (y direction) based on the drawing. Accordingly, the previous scan signal applied to the previous scan line SL-1 may be transmitted to the second initializing thin film transistor of another pixel circuit PC as the next scan signal. In the same manner, the second initializing voltage line VL2 and the next scan line SL +1 may be electrically connected to the first initializing thin film transistor of another adjacent pixel circuit PC arranged below (direction-y) the pixel circuit PC of fig. 3 in the second direction (y direction) based on the drawing, and thus the previous scan signal and the initializing voltage may be transmitted to the first initializing thin film transistor of another pixel circuit PC.

Referring back to fig. 5, the planarization layer 117 may have a flat upper surface so that the pixel electrode 210 may be flat. The planarization layer 117 may include an organic material, and may have a single layer or a multi-layer structure. Flat and flatThe layer 117 may include general-purpose commercial polymers such as benzocyclobutene (BCB), polyimide, Hexamethyldisilane (HMDSO), poly (methyl methacrylate) (PMMA), or Polystyrene (PS), polymer derivatives having a phenol group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine polymers, p-xylene polymers, vinyl alcohol polymers, or blends thereof. In an exemplary embodiment, the planarization layer 117 includes an inorganic material. The planarization layer 117 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiON), aluminum oxide (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO). When the planarization layer 117 includes an inorganic material, chemical planarization polishing may be performed in some embodiments. In some embodiments, the planarization layer 117 may include both organic and inorganic materials.

The organic light emitting diode OLED may include a pixel electrode 210, a common electrode 230, and an intermediate layer 220 interposed between the pixel electrode 210 and the common electrode 230 and including an emission layer.

The pixel electrode 210 may be connected to a connection metal 1175 through a contact hole 1163, and the connection metal 1175 may be connected to the emission control drain region D6 through a contact hole 1153. The pixel electrode 210 may be a (semi-) transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may include a reflective film including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or translucent electrode layer disposed on the reflective film. The transparent or semitransparent electrode layer may include a material selected from the group consisting of Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), zinc oxide (ZnO), indium oxide (In)₂O₃) At least one of the group of Indium Gallium Oxide (IGO) and Aluminum Zinc Oxide (AZO). In some embodiments, the pixel electrode 210 may have a stacked structure of ITO/Ag/ITO.

The pixel defining layer 119 may be disposed on the planarization layer 117, and the pixel defining layer 119 may have an opening portion exposing a central portion of the pixel electrode 210. Thus, the pixel defining layer 119 may define an emission area of the (sub) pixel SPX. In addition, the pixel defining layer 119 may prevent an arc from occurring at the edge of the pixel electrode 210 by increasing a distance between the edge of the pixel electrode 210 and the common electrode 230 disposed over the pixel electrode 210. The pixel defining layer 119 may be formed by a method such as spin coating using an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenol resin.

The intermediate layer 220 may include an organic emission layer. The organic emission layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue or white light. The organic emission layer may include a low molecular weight organic material or a polymer organic material, and functional layers such as a Hole Transport Layer (HTL), a Hole Injection Layer (HIL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) may be further selectively disposed under and on the organic emission layer. The intermediate layer 220 may correspond to each of the plurality of pixel electrodes 210. However, embodiments of the present disclosure are not limited thereto, and a layer such as an HTL, an HIL, an ETL, or an EIL among layers included in the intermediate layer 220 may be integrally formed over the plurality of pixel electrodes 210.

The common electrode 230 may be a transmissive electrode or a reflective electrode. In an embodiment, the common electrode 230 may be a transparent or semi-transparent electrode, and may include a metal thin film having a low work function and including Li, Ca, LiF, Al, Ag, Mg, and compounds thereof. The common electrode 230 may further include, In addition to the metal thin film, for example, ITO, IZO, ZnO, or In₂O₃A Transparent Conductive Oxide (TCO) film of (a). The common electrode 230 may be integrally formed to correspond to the plurality of pixel electrodes 210.

An encapsulation layer 300 including a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 320, and an organic encapsulation layer 330 between the first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 may be disposed on the common electrode 230.

The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 320 may include silicon oxide (SiO)₂) Silicon nitride (SiN)_x) Silicon oxynitride (SiO)N), alumina (Al)₂O₃) Titanium oxide (TiO)₂) Tantalum oxide (Ta)₂O₅) Hafnium oxide (HfO)₂) Or zinc oxide (ZnO). The organic encapsulation layer 330 may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinylsulfonate, polyoxymethylene, polyarylate, HMDSO, acrylic resin (e.g., PMMA, polyacrylic acid, etc.), or any combination thereof.

As described above, the first gate insulating layer 112 may be disposed on the semiconductor layer 1130, and the driving gate electrode G1, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL may be disposed on the first gate insulating layer 112. As described above, the scan line SL, the previous scan line SL-1, the next scan line SL +1, and the emission control line EL include the switching gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the operation control gate electrode G5, the emission control gate electrode G6, and the second initialization gate electrode G7. Accordingly, the first gate insulating layer 112 is interposed between the driving gate electrode G1, the switching gate electrode G2, the compensation gate electrode G3, the first initialization gate electrode G4, the operation control gate electrode G5, the emission control gate electrode G6, the second initialization gate electrode G7, and the semiconductor layer 1130.

In a display device (e.g., an organic light emitting display device) according to an exemplary embodiment of the present disclosure, a dielectric constant of the first gate insulating layer 112 in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 (e.g., a driving active region) and the driving gate electrode G1 is greater than a dielectric constant of the first gate insulating layer 112 in the second portion 1122 of the third active region A3 (e.g., a compensation active region) and the compensation gate electrode G3.

As described above with reference to fig. 2, the driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and drives the current I_OLEDTo the organic light emitting diode OLED. That is, the voltage between the driving gate electrode G1 of the driving thin film transistor T1 and the driving source region S1 determines the driving current I flowing through the organic light emitting diode OLED_OLED. In this regard, when the threshold voltage V of the driving thin film transistor T1 of several pixels_thAre different from each otherWhen the same data signal Dm is applied to the plurality of pixels, the driving current I flowing through the organic light emitting diode OLED_OLEDAre also different from each other. Drive current I flowing through the organic light-emitting diode OLED_OLEDIn the case where the same data signal Dm is applied to the several pixels and is different from each other, the display apparatus may not display a high-quality image.

The compensating thin film transistor T3 may be connected to each of the driving thin film transistors T1 in the driving thin film transistor T1 to prevent the threshold voltage V in the driving thin film transistor T1_thThe influence of (c). Therefore, even if the threshold voltage V of the driving thin film transistor T1 of several pixels_thDifferent from each other, when the same data signal Dm is applied to the plurality of pixels, a driving current I flowing through the organic light emitting diode OLED_OLEDMay also be almost the same size as each other.

However, even with the compensation thin film transistor T3, the pixel may not be able to display a high quality image. The threshold voltage V in compensating for the voltage difference between the driving gate electrode G1 of the driving thin film transistor T1 and the driving source region S1_thThereafter, the compensation thin film transistor T3 is completely turned off to prevent the current flowing in the direction from the driving thin film transistor T1 to the organic light emitting diode OLED from flowing to the compensation thin film transistor T3 at the third node N3. However, even when the compensation thin film transistor T3 is turned off, there is a leakage current flowing from the compensation source region S3 of the compensation thin film transistor T3 to the compensation drain region D3. When the magnitudes of such leakage currents are different from each other in the compensation thin film transistor T3, even if the same data signal Dm is applied to several pixels, the driving current I flowing through the organic light emitting diode OLED_OLEDAre also different from each other. Drive current I flowing through the organic light-emitting diode OLED_OLEDIn the case where the same data signal Dm is applied to the several pixels and is different from each other, the display apparatus may not display a high-quality image.

In addition, a parasitic capacitance may exist between the third active region A3 of the compensating thin film transistor T3 and the compensating gate electrode G3, thereby causing a kickback phenomenon in the display device. The kickback phenomenon refers to a flickering phenomenon in which a screen of the display device flickers or a phenomenon in which a residual image remains on the screen.

However, in the organic light emitting display device according to at least one exemplary embodiment of the present disclosure, a dielectric constant of the first gate insulating layer 112 in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1 is greater than a dielectric constant of the first gate insulating layer 112 in the second portion 1122 of the third active region A3 and the compensation gate electrode G3. That is, the dielectric constant in the second portion 1122 of the first gate insulating layer 112 between the third active region A3 and the compensation gate electrode G3 is less than the dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1.

When the dielectric constant in the second portion 1122 of the first gate insulating layer 112 between the third active region A3 and the compensation gate electrode G3 is reduced, the parasitic capacitance between the third active region A3 and the compensation gate electrode G3 may be reduced, and thus, the kickback phenomenon may be prevented or reduced, and the magnitude of the leakage current in the compensation thin film transistor T3 may be reduced. When the magnitude of the leakage current in the compensating thin film transistor T3 is reduced, the difference in the magnitude of the leakage current in the compensating thin film transistor T3 is also reduced. Accordingly, the display device according to at least one exemplary embodiment of the present disclosure may display a high quality image.

In an exemplary embodiment, a dielectric constant in the fourth portion 1124 of the first gate insulating layer 112 between the sixth active region a6 and the emission control gate electrode G6 is the same as a dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the drive gate electrode G1. This also applies to the embodiments described later and modifications thereof.

As shown in fig. 5, the second portion 1122 of the first gate insulating layer 112 between the third active region A3 and the compensation gate electrode G3 may be a portion in which the compensation gate electrode G3 and the third active region A3 overlap each other. When the compensation gate electrode G3 and the third active region A3 are referred to as overlapping each other, this means that the compensation gate electrode G3 and the third active region A3 overlap each other when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the compensation gate electrode G3. As shown in fig. 3 to 5, when the compensation thin film transistor T3 has a dual gate electrode, the first gate insulating layer 112 may have two second portions 1122 spaced apart from each other in the compensation thin film transistor T3.

As described above, the parasitic capacitance in the compensation thin film transistor T3 occurs between the compensation gate electrode G3 and the third active region A3. Therefore, the area of the second portion 1122 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 may be at least the same as the area of the portion of the compensation gate electrode G3 overlapping with the third active region A3 when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the compensation gate electrode G3.

In two components arranged on different layers, parasitic capacitance occurs not only between portions of the components that overlap each other in a direction perpendicular to the substrate 101. Therefore, in order to reduce parasitic capacitance, as shown in fig. 6, fig. 6 is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment, when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the compensation gate electrode G3, the area of the second portion 1122 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is larger than the area of the portion of the compensation gate electrode G3 overlapping with the third active region A3.

Further, as shown in fig. 7, fig. 7 is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment, in the compensation thin film transistor T3 having a dual gate electrode, the second portion 1122 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 may correspond not only to the compensation gate electrode G3 spaced apart from each other but also to a portion between the compensation gate electrodes G3 (i.e., a region A3a between two third active regions A3).

Accordingly, the kickback phenomenon in the compensation thin film transistor T3 may be prevented or reduced, and the magnitude of the leakage current in the compensation thin film transistor T3 may be reduced. When the magnitude of the leakage current in the compensating thin film transistor T3 is reduced, the difference in the magnitude of the leakage current in the compensating thin film transistor T3 is also reduced. Accordingly, the display device according to at least one exemplary embodiment of the present disclosure may display a high quality image.

In exemplary embodiments of the present disclosure, by various methods, a dielectric constant in the second portion 1122 of the first gate insulating layer 112 between the third active region A3 and the compensation gate electrode G3 is less than a dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1.

When the first gate insulating layer 112 includes silicon oxide, the number of oxygen atoms per unit volume in the second portion 1122 may be larger than the number of oxygen atoms per unit volume in the first portion 1121, so that the dielectric constant in the second portion 1122 is smaller than the dielectric constant in the first portion 1121. Silicon oxide may be referred to as SiOx, where x is the number of oxygen atoms per silicon atom. When x is 1.6 to 1.8 in SiOx, the dielectric constant of silicon oxide is 4.6 to 4.7. When x is 1.9 to 2.0 in SiOx, the dielectric constant of silicon oxide is 4.0 or less. Therefore, as the number of oxygen atoms per unit volume in the silicon oxide layer increases, the dielectric constant of the silicon oxide layer decreases, and as a result, the size of the parasitic capacitance may be reduced. The reason why the dielectric constant of the silicon oxide layer decreases as the number of oxygen atoms per unit volume in the silicon oxide layer increases is that the binding energy increases and a polarization phenomenon due to a decrease in the electric field as the amount of oxygen increases.

When the first gate insulating layer 112 includes silicon oxide, the second portion 1122 may include fluorine or carbon so that a dielectric constant in the second portion 1122 is smaller than that in the first portion 1121. That is, the first portion 1121 of the first gate insulating layer 112 may include SiOx, and the second portion 1122 may include SiOF or SiOC. In SiO₂In the case of SiOF or SiOC, the dielectric constant is about 4.2, and in the case of SiOF or SiOC, if the atomic percent of F or C is 3.1, the dielectric constant is 3.8, if the atomic percent of F or C is 7.0, the dielectric constant is 3.4, and if the atomic percent of F or C is 10.0, the dielectric constant is 3.3. Accordingly, when the first gate insulating layer 112 includes silicon oxide, the second portion 1122 may include fluorine or carbon so that a dielectric constant in the second portion 1122 is smaller than that in the first portion 1121.

Although the driving thin film transistor T1 and the compensating thin film transistor T3 have been mainly described, the above description may be applied to the first initializing thin film transistor T4 in addition to the compensating thin film transistor T3.

The first initializing thin film transistor T4 initializes the voltage of the driving gate electrode G1 of the driving thin film transistor T1. However, since a leakage current exists in the first initializing thin film transistor T4 after the first initializing thin film transistor T4 is turned off, the voltage of the driving gate electrode G1 of the driving thin film transistor T1 may be unintentionally changed. Specifically, when the magnitudes of the leakage currents of the first initializing thin film transistors T4 are different from each other in the plurality of pixels, the degrees of the voltage variation of the driving gate electrodes G1 are different from each other in the plurality of pixels. This eventually leads to deterioration in the quality of the image displayed by the display device.

In an exemplary embodiment, a dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1 is greater than a dielectric constant in the third portion 1123 of the first gate insulating layer 112 between the fourth active region a4 (e.g., an initialization region) and the first initialization gate electrode G4 to prevent degradation of the quality of an image. That is, the dielectric constant of the third portion 1123 of the first gate insulating layer 112 between the fourth active region a4 and the first initializing gate electrode G4 may be less than the dielectric constant of the first gate insulating layer 112 in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1.

When the dielectric constant of the first gate insulating layer 112 in the third portion 1123 between the fourth active region a4 and the first initializing gate electrode G4 is reduced, the parasitic capacitance between the fourth active region a4 and the first initializing gate electrode G4 may be reduced, and thus, the magnitude of the leakage current in the first initializing thin film transistor T4 may be reduced. When the magnitude of the leakage current in the first initializing thin film transistor T4 is reduced, the difference in the magnitude of the leakage current in the first initializing thin film transistor T4 is also reduced. Accordingly, the display device according to at least one exemplary embodiment may display a high quality image.

As shown in fig. 5, a third portion 1123 of the first gate insulating layer 112 between the fourth active region a4 and the first initialization gate electrode G4 may be a portion in which the first initialization gate electrode G4 and the fourth active region a4 overlap each other. When the first and fourth initializing gate electrodes G4 and a4 are referred to as overlapping each other, this means that the first and fourth initializing gate electrodes G4 and a4 overlap each other when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the first initializing gate electrode G4. As shown in fig. 3 to 5, when the first initializing thin film transistor T4 has the double gate electrode, the first gate insulating layer 112 may have two third portions 1123 spaced apart from each other in the first initializing thin film transistor T4.

As described above, parasitic capacitance in the first initializing thin film transistor T4 occurs between the first initializing gate electrode G4 and the fourth active region a 4. Therefore, the area of the third portion 1123 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is at least the same as the area of the portion of the first initialization gate electrode G4 overlapping with the fourth active region a4 when viewed from the direction perpendicular to the substrate 101 or the direction perpendicular to the upper surface of the first initialization gate electrode G4.

In two components arranged on different layers, parasitic capacitance occurs not only between portions of the components that overlap each other in a direction perpendicular to the substrate 101. Therefore, in order to reduce parasitic capacitance, as shown in fig. 6, fig. 6 is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment, and an area of the third portion 1123 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 may be larger than an area of a portion of the first initialization gate electrode G4 overlapping the fourth active region a4 when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to an upper surface of the first initialization gate electrode G4.

Further, as shown in fig. 7, fig. 7 is a schematic cross-sectional view of a portion of a display device according to an exemplary embodiment, in the first initializing thin film transistor T4 having a dual gate electrode, the third portion 1123 having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 may correspond not only to the first initializing gate electrodes G4 spaced apart from each other but also to a portion between the first initializing gate electrodes G4 (i.e., the region A4a between two fourth active regions A4).

Accordingly, the magnitude of the leakage current in the first initializing thin film transistor T4 can be reduced. When the magnitude of the leakage current in the first initializing thin film transistor T4 is reduced, the difference in the magnitude of the leakage current in the first initializing thin film transistor T4 is also reduced. Accordingly, the display device according to at least one exemplary embodiment may display a high quality image.

In an exemplary embodiment, the permittivity in the third portion 1123 of the first gate insulating layer 112 between the fourth active region a4 and the first initialization gate electrode G4 may be made smaller than the permittivity in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1 by one of various methods. As described above, when the first gate insulating layer 112 includes silicon oxide, the number of oxygen atoms per unit volume in the third portion 1123 may be larger than the number of oxygen atoms per unit volume in the first portion 1121, so that the dielectric constant in the third portion 1123 is smaller than the dielectric constant in the first portion 1121. Alternatively, when the first gate insulating layer 112 includes silicon oxide, the third portion 1123 may include fluorine or carbon such that the permittivity in the third portion 1123 is smaller than that in the first portion 1121. That is, the first portion 1121 of the first gate insulating layer 112 may include SiOx, and the third portion 1123 may include SiOF or SiOC.

The above description about the first initializing thin film transistor T4 can also be applied to the second initializing thin film transistor T7.

The second initializing thin film transistor T7 may be turned on according to the scan signal Sn received through the next scan line SL +1 to perform an operation of initializing the pixel electrode of the organic light emitting diode OLED. However, since a leakage current exists in the second initializing thin film transistor T7 after the second initializing thin film transistor T7 is turned off, a current flowing to the organic light emitting diode OLED may be unintentionally changed. Specifically, when the magnitudes of the leakage currents of the second initializing thin film transistors T7 are different from each other in the plurality of pixels, the degrees of the changes in the current flowing to the organic light emitting diodes OLED are different from each other in the plurality of pixels. This may eventually lead to a degradation in the quality of the image displayed by the display device.

In an exemplary embodiment, a dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1 is greater than a dielectric constant in the fifth portion of the first gate insulating layer 112 between the seventh active region a7 and the second initializing gate electrode G7 to prevent deterioration of image quality. That is, the dielectric constant of the fifth portion of the first gate insulating layer 112 between the seventh active region a7 and the second initializing gate electrode G7 is smaller than the dielectric constant of the first gate insulating layer 112 in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1. For reference, the structures of the seventh active region a7, the second initialization gate electrode G7, and the fifth portion in the cross-sectional views may be the same as those of the sixth active region a6, the emission control gate electrode G6, and the fourth portion 1124 shown in the cross-sectional views of fig. 5 to 7. This also applies to the embodiments described later and modifications thereof.

When the dielectric constant of the first gate insulating layer 112 in the fifth portion between the seventh active region a7 and the second initializing gate electrode G7 is reduced, the parasitic capacitance between the seventh active region a7 and the second initializing gate electrode G7 may be reduced, and thus, the magnitude of the leakage current in the second initializing thin film transistor T7 may be reduced. When the magnitude of the leakage current in the second initializing thin film transistor T7 is reduced, the difference in the magnitude of the leakage current in the second initializing thin film transistor T7 is also reduced. Accordingly, the display device according to at least one exemplary embodiment may display a high quality image.

A fifth portion of the first gate insulating layer 112 between the seventh active region a7 and the second initializing gate electrode G7 may be a portion in which the second initializing gate electrode G7 and the seventh active region a7 overlap each other. When the second initializing gate electrode G7 and the seventh active region a7 are referred to as overlapping each other, this means that the second initializing gate electrode G7 and the seventh active region a7 overlap each other when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the second initializing gate electrode G7.

As described above, parasitic capacitance in the second initializing thin film transistor T7 may occur between the second initializing gate electrode G7 and the seventh active region a 7. Therefore, according to an exemplary embodiment, an area of the fifth portion having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is at least the same as an area of a portion of the second initializing gate electrode G7 overlapping with the seventh active region a7 when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the second initializing gate electrode G7. That is, since the area of the fourth portion 1124 of the first gate insulating layer 112 is the same as the area of the portion of the emission control gate electrode G6 overlapping the sixth active region a6 in fig. 5, the area of the fifth portion having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is the same as the area of the portion of the second initialization gate electrode G7 overlapping the seventh active region a 7.

In two components arranged on different layers, parasitic capacitance occurs not only between portions of the components that overlap each other in a direction perpendicular to the substrate 101. The area of the fifth portion having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is larger than that of the portion of the second initialization gate electrode G7 overlapping with the seventh active region a7 when viewed from a direction perpendicular to the substrate 101 or a direction perpendicular to the upper surface of the second initialization gate electrode G7 to reduce parasitic capacitance. That is, since the area of the fourth portion 1124 of the first gate insulating layer 112 is greater than that of the portion of the emission control gate electrode G6 overlapping the sixth active region a6 in fig. 6, the area of the fifth portion having a lower dielectric constant than the first portion 1121 in the first gate insulating layer 112 is greater than that of the portion of the second initialization gate electrode G7 overlapping the seventh active region a 7.

Accordingly, the magnitude of the leakage current in the second initializing thin film transistor T7 can be reduced. When the magnitude of the leakage current in the second initializing thin film transistor T7 is reduced, the difference in the magnitude of the leakage current in the second initializing thin film transistor T7 is also reduced. Accordingly, the display device according to at least one exemplary embodiment may display a high quality image.

In an exemplary embodiment, the dielectric constant in the fifth portion of the first gate insulating layer 112 between the seventh active region a7 and the second initializing gate electrode G7 may be made smaller than the dielectric constant in the first portion 1121 of the first gate insulating layer 112 between the first active region a1 and the driving gate electrode G1 by one of various methods. As described above, when the first gate insulating layer 112 includes silicon oxide, the number of oxygen atoms per unit volume in the fifth portion may be larger than the number of oxygen atoms per unit volume in the first portion 1121, so that the dielectric constant in the fifth portion is smaller than the dielectric constant in the first portion 1121. Alternatively, when the first gate insulating layer 112 includes silicon oxide, the fifth portion may include fluorine or carbon so that a dielectric constant in the fifth portion is smaller than that in the first portion 1121. That is, the first portion 1121 of the first gate insulating layer 112 may include SiOx, and the fifth portion may include SiOF or SiOC.

Although the display device according to the exemplary embodiment has been described, the present disclosure is not limited thereto. It will be understood that methods of manufacturing such display devices also fall within the scope of the present disclosure.

For example, as shown in fig. 5, a semiconductor layer 1130 having a first active region a1 and a third active region A3 is formed over the substrate 101, and a first gate insulating layer 112 covering the semiconductor layer 1130 is formed. The first gate insulating layer 112 may include, for example, silicon oxide. In addition, oxygen ions, fluorine ions, or carbon ions may be implanted into the second portion 1122 of the first gate insulating layer 112 corresponding to the third active region a 3.

By forming a mask layer covering the first gate insulating layer 112 but exposing only the second portion 1122 using photoresist and implanting oxygen ions, fluorine ions, or carbon ions into the first gate insulating layer 112, or by performing a remote plasma treatment, oxygen ions, fluorine ions, or carbon ions may be implanted into the second portion 1122 of the first gate insulating layer 112 corresponding to the third active region a 3. The mask layer may then be removed and a thermal treatment may be performed to activate the implanted ions.

Then, a driving gate electrode G1 corresponding to the first active region a1 and a compensation gate electrode G3 corresponding to the third active region A3 may be formed on the first gate insulating layer 112 to form a gate electrode having first active regions a1 and aA drive gate electrode G1 and configured to control a drive current I flowing to the organic light emitting diode OLED_OLEDThe driving thin film transistor T1 and the compensation thin film transistor T3 having the third active region A3 and the compensation gate electrode G3. The compensation thin film transistor T3 may be configured to diode-connect the driving thin film transistor T1 in response to a voltage applied to the compensation gate electrode G3, and then, the organic light emitting diode OLED electrically connected to the driving thin film transistor T1 may be formed to manufacture an organic light emitting display device.

As shown in fig. 5, a semiconductor layer 1130 may be formed over the substrate 101 to have a fourth active region a4 except for the first active region a1 and the third active region A3, and a first gate insulating layer 112 covering the semiconductor layer 1130 may be formed. The first gate insulating layer 112 may include, for example, silicon oxide. In addition, oxygen ions, fluorine ions, or carbon ions may be implanted into the third portion 1123 of the first gate insulating layer 112 corresponding to the fourth active region a 4.

Oxygen ions, fluorine ions, or carbon ions may be implanted into the third portion 1123 of the first gate insulating layer 112 corresponding to the fourth active region a4 in the same manner as oxygen ions, fluorine ions, or carbon ions are implanted into the second portion 1122 of the first gate insulating layer 112 corresponding to the third active region A3. Oxygen ions, fluorine ions, or carbon ions may be implanted into the second portion 1122 and the third portion 1123 simultaneously during the same process.

Then, when the driving gate electrode G1 corresponding to the first active region a1 and the compensation gate electrode G3 corresponding to the third active region A3 are formed on the first gate insulating layer 112, the first initializing gate electrode G4 may also be simultaneously formed using the same material to form the driving thin film transistor T1, the compensation thin film transistor T3 and the first initializing thin film transistor T4. Then, the organic light emitting diode OLED electrically connected to the driving thin film transistor T1 may be formed to manufacture an organic light emitting display device.

The display device may be manufactured in a different manner from that described above. For example, according to an exemplary embodiment, in a method of manufacturing a display device, as shown in fig. 5, a semiconductor layer 1130 having a first active region a1 and a third active region A3 is formed over a substrate 101, and a first gate insulating layer 112 covering the semiconductor layer 1130 is formed. The first gate insulating layer 112 may include, for example, silicon oxide. Then, in an embodiment of the method, silicon ions are implanted into the first portion 1121 of the first gate insulating layer 112 corresponding to the first active region a 1. That is, when the first gate insulating layer 112 is formed, the silicon oxide layer may be formed to have a large number of oxygen atoms per unit volume, and silicon ions may be implanted into the first portion 1121 having a relatively high dielectric constant in the first gate insulating layer 112. Therefore, the dielectric constant in the first portion 1121 can be increased. For example, when the first gate insulating layer 112 is formed, the layer including silicon oxide may be formed such that the number of oxygen atoms included per unit volume is 1.9 times or more the number of silicon atoms included per unit volume.

By forming a mask layer covering the first gate insulating layer 112 but exposing only the first portion 1121 using photoresist and implanting silicon ions into the first gate insulating layer 112, or by performing remote plasma treatment, silicon ions may be implanted into the first portion 1121 of the first gate insulating layer 112 corresponding to the first active region a 1. The mask layer may then be removed and a thermal treatment may be performed to activate the implanted ions.

In an exemplary embodiment of the method, silicon ions are implanted into a portion of the first gate insulating layer 112 other than the second portion 1122 of the first gate insulating layer 112. In the present embodiment, a mask layer may be disposed only on the second portion 1122 of the first gate insulating layer 112 to prevent silicon ions from being implanted into the second portion 1122.

Then, a driving gate electrode G1 corresponding to the first active region a1 and a compensation gate electrode G3 corresponding to the third active region A3 may be formed on the first gate insulating layer 112 to form a gate electrode having a first active region a1 and a driving gate electrode G1 and configured to control a driving current I flowing to the organic light emitting diode OLED_OLEDThe driving thin film transistor T1 and the compensation thin film transistor T3 having the third active region A3 and the compensation gate electrode G3. The compensation thin film transistor T3 is configured to respond to the voltageThe voltage applied to the compensation gate electrode G3 diode-connects the driving thin film transistor T1. Then, the organic light emitting diode OLED electrically connected to the driving thin film transistor T1 may be formed to manufacture an organic light emitting display device.

As shown in fig. 5, a semiconductor layer 1130 may be formed over the substrate 101 to have a fourth active region a4 except for the first active region a1 and the third active region A3, and a first gate insulating layer 112 covering the semiconductor layer 1130 may be formed. The first gate insulating layer 112 may include silicon oxide having a large number of oxygen atoms per unit volume. In addition, silicon ions may be implanted into the first portion 1121 of the first gate insulating layer 112 corresponding to the first active region a 1.

Silicon ions may be implanted into portions other than the second and third portions 1122 and 1123 of the first gate insulating layer 112. In this case, the mask layer is disposed only on the second and third portions 1122 and 1123 of the first gate insulating layer 112.

Then, when the driving gate electrode G1 corresponding to the first active region a1 and the compensation gate electrode G3 corresponding to the third active region A3 are formed on the first gate insulating layer 112, the first initializing gate electrode G4 may also be simultaneously formed using the same material to form the driving thin film transistor T1, the compensation thin film transistor T3 and the first initializing thin film transistor T4. Then, the organic light emitting diode OLED electrically connected to the driving thin film transistor T1 may be formed to manufacture an organic light emitting display device.

In an exemplary embodiment of the present disclosure, an area of the second portion 1122 and/or an area of the third portion 1123 of the first gate insulating layer 112 are the same as those described above with reference to fig. 5 to 7.

In the manufacturing method described above, a process such as implanting oxygen ions, fluorine ions, or carbon ions into the third portion 1123 of the first gate insulating layer 112 corresponding to the fourth active region a4 may also be applied to the fifth portion of the first gate insulating layer 112 corresponding to the seventh active region a 7.

According to at least one of the above-described embodiments, an organic light emitting display device configured to display a high quality image and a method of manufacturing an organic light emitting display device configured to display a high quality image may be implemented. However, embodiments of the present disclosure are not limited to providing higher quality images, and may provide other benefits.

It is to be understood that the embodiments described herein are to be considered in a descriptive sense and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. Although one or more embodiments have been described herein with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.