阅读说明：本技术 一种锁相环电路 (Phase-locked loop circuit ) 是由 孙杰 于 2019-09-12 设计创作，主要内容包括：本发明实施例公开了一种锁相环电路。包括：鉴频鉴相器、电荷泵、滤波电路、电压电流转换电路、第一电容、电压缓冲单元、第二电容、电流镜像单元、电流控制振荡器及分频器；所述鉴频鉴相器、所述电荷泵、所述电压电流转换电路、所述电流控制振荡器及所述分频器依次连接；所述滤波电路连接于第一节点和接地端之间；所述第一电容连接于第二节点与接地端之间；所述电压缓冲单元的输入端与所述第二节点相连,电压缓冲单元的输入端与所述第二电容的一端连接；所述第二电容的另一端与电流镜像单元的输入端相连,所述电流镜像单元输出单元的输出端与所述第二节点相连。可以降低振荡器带来的电压波动,从而减小锁相环电路输出时钟的抖动。(The embodiment of the invention discloses a phase-locked loop circuit. The method comprises the following steps: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence; the filter circuit is connected between the first node and a grounding end; the first capacitor is connected between the second node and the grounding end; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node. The voltage fluctuation caused by the oscillator can be reduced, and therefore the jitter of the output clock of the phase-locked loop circuit is reduced.)

1. A phase-locked loop circuit, comprising: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;

The phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;

The filter circuit is connected between the first node and a grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;

The first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;

the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node.

2. The circuit of claim 1, wherein the voltage-to-current conversion circuit comprises a first PMOS transistor; the current controlled oscillator comprises three inverters;

The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is respectively connected with the input stages of the three phase inverters; the three inverters are connected in series in a manner that the intermediate stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.

3. The circuit of claim 2, wherein the inverter comprises a PMOS transistor and an NMOS transistor.

4. the circuit of claim 1, wherein the filter circuit comprises a first resistor and a third capacitor;

one end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; and the other end of the third capacitor is connected with a grounding end.

5. The circuit of claim 1, wherein the voltage buffer unit comprises two PMOS transistors, namely a second PMOS transistor and a third PMOS transistor;

The grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the grounding end.

6. The circuit of claim 1, wherein the current mirror unit comprises two PMOS transistors and two NMOS transistors; a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube respectively;

The grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are both connected with a grounding end; and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube.

7. The circuit of claim 6, wherein the other end of the second capacitor is connected to the drain of the fourth PMOS transistor.

Technical Field

the embodiment of the invention relates to the technical field of circuits, in particular to a phase-locked loop circuit.

Background

With the development of wireless communication technology and integrated circuit technology, more and more wireless communication systems are integrated on a chip. The phase-locked loop can generate an accurate clock signal or a frequency signal, so the phase-locked loop is widely applied to a clock generator, and a frequency synthesizer based on the phase-locked loop is widely applied to a radio frequency transceiving system in an electronic system such as a wireless communication transceiving system, a clock/data recovery circuit and the like. These needs have prompted the study and development of phase-locked loop circuits.

disclosure of Invention

the embodiment of the invention provides a phase-locked loop circuit, which can reduce voltage fluctuation caused by an oscillator so as to reduce the jitter of an output clock of the phase-locked loop circuit.

in a first aspect, an embodiment of the present invention provides a phase-locked loop circuit, including: the phase frequency detector comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider;

The phase frequency detector is provided with a reference signal input end and a feedback signal input end connected with the frequency divider; the phase frequency detector, the charge pump, the voltage-current conversion circuit, the current control oscillator and the frequency divider are connected in sequence;

The filter circuit is connected between the first node and a grounding end; wherein a first node is located between the charge pump and the voltage-to-current conversion circuit;

the first capacitor is connected between the second node and the grounding end; wherein a second node is located between the voltage-to-current conversion circuit and the current controlled oscillator;

The input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node.

further, the voltage-current conversion circuit comprises a first PMOS tube; the current controlled oscillator comprises three inverters;

The grid electrode of the first PMOS tube is connected with the output end of the charge pump, the source electrode of the first PMOS tube is connected with a power supply, and the drain electrode of the first PMOS tube is respectively connected with the input stages of the three phase inverters; the three inverters are connected in series in a manner that the intermediate stage is connected with the output stage; the second node is positioned between the drain electrode of the first PMOS tube and the input stages of the three inverters.

Further, the phase inverter comprises a PMOS tube and an NMOS tube.

Further, the filter circuit comprises a first resistor and a third capacitor;

One end of the first resistor is connected with the first node, and the other end of the first resistor is connected with one end of the third capacitor; and the other end of the third capacitor is connected with a grounding end.

further, the voltage buffer unit comprises two PMOS tubes, namely a second PMOS tube and a third PMOS tube;

the grid electrode of the second PMOS tube is connected with the first node, the source electrode of the second PMOS tube is connected with a power supply, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the third PMOS tube and one end of the second capacitor; and the grid electrode of the third PMOS tube is connected with the second node, and the drain electrode of the third PMOS tube is connected with the grounding end.

Further, the current mirror unit comprises two PMOS tubes and two NMOS tubes; a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube and a second NMOS tube respectively;

the grid electrodes of the fourth PMOS tube and the fifth PMOS tube are connected with the first node, and the source electrodes are connected with a power supply; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube; the drain electrode of the fifth PMOS tube is connected with the drain electrode of the second NMOS tube; the source electrodes of the first NMOS tube and the second NMOS tube are both connected with a grounding end; and the drain electrode of the first NMOS tube is connected with the grid electrode of the second NMOS tube.

Further, the other end of the second capacitor is connected with the drain electrode of the fourth PMOS transistor.

The phase-locked loop circuit provided by the embodiment of the invention comprises a phase frequency detector, a charge pump, a filter circuit, a voltage-current conversion circuit, a first capacitor, a voltage buffer unit, a second capacitor, a current mirror unit, a current control oscillator and a frequency divider; the first capacitor is connected between the second node and the grounding end; the second node is positioned between the voltage-current conversion circuit and the current control oscillator; the input end of the voltage buffer unit is connected with the second node, and the input end of the voltage buffer unit is connected with one end of the second capacitor; the other end of the second capacitor is connected with the input end of the current mirror image unit, and the output end of the output unit of the current mirror image unit is connected with the second node. The voltage fluctuation caused by the oscillator can be reduced, and therefore the jitter of the output clock of the phase-locked loop circuit is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a phase-locked loop circuit according to a first embodiment of the present invention;

FIG. 2 is a schematic diagram of a current controlled oscillator according to a first embodiment of the present invention;

Fig. 3 is a schematic diagram of a partial structure of a pll circuit according to a first embodiment of the present invention;

Fig. 4 is a schematic diagram of voltages and currents at nodes in a pll circuit according to a first embodiment of the present invention.

Detailed Description

the present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.