阅读说明：本技术 具有Г型栅的GaN基MIS-HEMT器件及制备方法 (GaN-based MIS-HEMT device with Г type gate and preparation method thereof ) 是由 王洪 陈竟雄 刘晓艺 于 2019-08-13 设计创作，主要内容包括：本发明公开了一种具有Г型栅的GaN基MIS-HEMT器件及其制备方法,所述器件包括AlGaN/GaN异质结外延层等结构,所述器件还包括一Г型栅电极,所述Г型栅电极包括栅帽和栅脚,栅脚的一端和栅帽的部分下表面连接,另一端和第二开口处部分暴露的栅介质层上表面连接,栅帽的其余下表面和钝化层上表面连接。本发明利用G线、I线光刻包括接触式光刻和步进式光刻与金属剥离工艺或金属刻蚀工艺结合,通过在钝化层开口处通过对准的方式,使一部分的栅极金属与栅介质层接触,另一部分与钝化层接触,使栅足线宽在光刻的极限线宽下大大减小；所述Г栅结构,引入了场板,场板调制了栅靠漏侧导电沟道的电场强度分布,提高了器件的击穿电压。(the invention discloses a GaN-based MIS-HEMT device with Г type gates and a preparation method thereof, wherein the device comprises structures such as an AlGaN/GaN heterojunction epitaxial layer and the like, and further comprises a Г type gate electrode, the Г type gate electrode comprises a gate cap and a gate pin, one end of the gate pin is connected with part of the lower surface of the gate cap, the other end of the gate pin is connected with the upper surface of a gate dielectric layer exposed at a second opening, and the other lower surface of the gate cap is connected with the upper surface of a passivation layer.)

1. The GaN-based MIS-HEMT device with the Г type gate is characterized by comprising an AlGaN/GaN heterojunction epitaxial layer, wherein the AlGaN/GaN heterojunction epitaxial layer is of a boss structure, the upper part of the boss is an active region, two ends of the upper surface of the active region are respectively connected with a source drain electrode, a gate dielectric layer and a passivation layer are sequentially covered on the source drain electrode and the upper surface of the active region from bottom to top in a region except the region where the source drain electrode is connected with the source drain electrode, the gate dielectric layer and the passivation layer are respectively provided with a first opening on the upper surface of the source drain electrode and a first opening exposing part of the upper surface of the source drain electrode, the passivation layer is provided with a second opening on the gate dielectric layer between the source drain electrode and the drain electrode, the upper surface of the gate dielectric layer is exposed, the second opening is further connected with a Г type gate electrode, the Г type gate electrode comprises a gate cap and a gate pin, the Г type vertical edge part is the gate pin, the transverse edge part is the gate cap, one end of the gate pin is connected with part of the lower.

2. The GaN-based MIS-HEMT device with an Г -type gate as claimed in claim 1, wherein the gate electrode has a material layer of at least three metal layers or metal nitride layers, the top material layer is at least one of TiN, WN, Cr and TiW, the middle material layer is Au or Al, the bottom material layer is at least one of TiN, WN, Cr and TiW, the gate electrode has a total thickness of 200 and 300nm, the gate legs have a left and right width of 0.2-0.5 μm, and the gate caps have a left and right width of 0.4-1 μm.

3. The GaN-based MIS-HEMT device with an Г -type gate as claimed in claim 1, wherein the thickness of the AlGaN/GaN heterojunction epitaxial layer is 500-1000 μm, and the thickness of the active region is 100-300 nm.

4. The GaN-based MIS-HEMT device with Г type gate as claimed in claim 1, wherein the source/drain electrode is a Ti layer, an Al layer, a Ni layer and an Au layer deposited on the upper surface of the active region from bottom to top, the source/drain electrode has a thickness of 200-300nm, and the Ti layer, the Al layer, the Ni layer and the Au layer have a thickness of 10-30nm, 80-120nm, 5-15nm and 80-120nm, respectively.

5. The GaN-based MIS-HEMT device with Г -type gate of claim 1, wherein the gate dielectric layer is SiN, the thickness of the gate dielectric layer is 5-15nm, and the passivation layer is SiN or SiO₂The thickness of the passivation layer is 65-150 nm.

6. The GaN based MIS-HEMT device with an Г type gate of claim 1, wherein the left-right width of the second opening is 0.35-1 μm.

7. a method of fabricating the GaN based MIS-HEMT device with an Г -type gate of any one of claims 1-6 comprising the steps of:

(1) Preparing and cleaning an AlGaN/GaN heterojunction epitaxial layer: preparing an AlGaN/GaN heterojunction epitaxial layer by Metal Organic Chemical Vapor Deposition (MOCVD), soaking the AlGaN/GaN heterojunction epitaxial layer in an acidic solution to remove a surface oxide layer, and removing organic matters on the AlGaN/GaN heterojunction epitaxial layer by adopting an organic solvent;

(2) Annealing the source and drain electrodes to form ohmic contact: defining metal positions and patterns of a source and drain electrode on an isolated active region by a negative photoresist photoetching process, and depositing the source and drain electrode; annealing at the temperature of more than 800 ℃ for 30-90s in the nitrogen atmosphere to enable the source drain electrode and the AlGaN barrier layer to form ohmic contact;

(3) Depositing a gate dielectric layer and a passivation layer: depositing a gate dielectric layer on the source drain electrode and the area outside the AlGaN/GaN heterojunction epitaxial layer, wherein the area is connected with the source drain electrode; depositing a passivation layer on the gate dielectric layer;

(4) Removing part of the passivation layer between the source electrode and the drain electrode: exposing the photoresist by a photoetching method to protect the area outside the second opening, removing the passivation layer with the thickness of 60-140nm by a physical etching method, and removing the passivation layer with the remaining thickness of 5-10nm by a chemical etching method to expose the upper surface of the gate dielectric layer;

(5) Preparing a gate electrode by combining optical lithography with stripping or etching, namely exposing a gate electrode pattern at a second opening by using an I-line or G-line lithography machine, depositing a material layer of the gate electrode between a source electrode and a drain electrode by electron beam evaporation or magnetron sputtering, and preparing an Г -type gate electrode in a stripping mode, or depositing the material layer of the gate electrode by electron beam evaporation or magnetron sputtering, exposing a gate electrode pattern area at the second opening, and reducing the left and right widths of a gate cap and a gate pin by using anisotropic etching photoresist and etching the gate electrode material layer outside the gate electrode pattern area by using inductively coupled plasma to prepare a Г -type gate electrode;

(6) Opening of the source and drain electrodes: exposing the area outside the first opening protected by the photoresist through optical lithography, and removing the passivation layer and the gate dielectric layer at the first opening on the source and drain electrodes through inductive coupling plasma etching;

(7) And (3) forming an independent active region by isolation etching: defining an active area on the AlGaN/GaN epitaxial layer, and covering and protecting the active area by adopting photoresist; and removing the AlGaN/GaN heterojunction epitaxial layer outside the active region by utilizing inductively coupled plasma etching (ICP) or Reactive Ion Etching (RIE), wherein the etching depth is 100-300 nm.

8. The method for preparing the GaN-based MIS-HEMT device with the Г -type gate, according to claim 7, wherein the method for depositing the source and drain electrodes is electron beam evaporation or magnetron sputtering.

9. the method of claim 7, wherein the gate dielectric layer is deposited by MOCVD or LPCVD.

10. The method of claim 7, wherein the passivation layer is deposited by PECVD.

Technical Field

The invention belongs to the technical field of semiconductors, and particularly relates to a GaN-based MIS-HEMT device with an Г gate structure and a preparation method thereof.

Background

Wide bandgap III-nitride materials, typically gallium nitride (GaN), and alloys thereof are called third generation semiconductor materials, and GaN-based wide bandgap semiconductor materials and devices have been developed very rapidly. GaN is a III-V group direct band gap semiconductor, has the characteristics of wide forbidden band, high breakdown field strength, high saturated electron drift velocity and high temperature resistance, wherein the GaN is very suitable for the application of microwave/millimeter wave high-power devices due to the forbidden band width of 3.4 ev. In addition, the GaN can be formed with the AlGaN/GaN heterojunction structure doped with the modulation dopant, and the two-dimensional electron gas conduction channel formed at room temperature has the characteristics of high electron concentration and high electron mobility, so that the switching rate is greatly improved compared with a bulk electron channel of a silicon device, and the cooling requirement is lower compared with the silicon device. Therefore, the gallium nitride HEMT device has wide application prospect in the field of microwave power.

from the small-signal and large-signal characteristics of HEMT devices, it is known that the shorter the gate length, the higher the cutoff frequency and maximum oscillation frequency of the device, and the higher the gate voltage swing and breakdown voltage of the device, the higher the power density, which requires that the gate length be reduced as much as possible, and that the gate voltage swing be increased by forming an MIS structure by inserting an insulating dielectric layer between the gate electrode and the AlGaN barrier layer, and that the breakdown voltage of the device be increased by modulating the channel electric field distribution by a field plate structure such as Г gate structure.

At present, the grid line width of the GaN-based MIS-HEMT device is determined by photoetching, and the most commonly used means mainly comprise G lines, I lines, deep ultraviolet and extreme ultraviolet photoetching with shorter wavelength and electron beam photoetching technology.

The G line and I line photoetching technology has the advantages of simple process, low cost and high efficiency. However, the minimum line width is limited by the wavelength of the light source, and a general G-line or I-line lithography machine can only achieve grid lines with a thickness of more than 0.5 μm. And the grid line below 0.5 μm needs a stepping photoetching machine or some special skills, the process is complex, the consistency is not high, and the requirement on the mask is higher than that of a contact photoetching machine.

The grid length manufactured by the electron beam direct writing method can reach the nanometer level, and the consistency is very good. But the production efficiency is low, the equipment is expensive and the maintenance cost is high, and the method can only be used for experimental research generally. In addition, the deep ultraviolet or extreme ultraviolet photoetching machine adopts a light source with shorter wavelength, the resolution ratio is higher and can reach 0.05-0.25 mu m, but compared with the G-line or I-line photoetching technology, the cost is higher and the efficiency is low.

Therefore, the search for a preparation method of the GaN-based MIS-HEMT device with the Г gate structure and the deep submicron gate length, which has the advantages of simple process, high efficiency and low cost, is a problem to be solved urgently in the industry.

Disclosure of Invention

The invention aims to overcome the defects of limitation of the gate photoetching process and low power density of the existing GaN-based MIS-HEMT device, provides the GaN-based MIS-HEMT device with the Г gate structure and the preparation method thereof from the aspects of the gate process and the device structure, and can effectively improve the frequency characteristic and the power characteristic of the device so as to meet the requirements of high-efficiency and high-yield large-scale production.

The purpose of the invention is realized by one of the following technical schemes.

The invention provides a GaN-based MIS-HEMT device with an Г type gate, which comprises an AlGaN/GaN heterojunction epitaxial layer, wherein the AlGaN/GaN heterojunction epitaxial layer is of a boss structure, the upper part of the boss is an active region, two ends of the upper surface of the active region are respectively connected with a source drain electrode, a gate dielectric layer and a passivation layer are sequentially covered on the source drain electrode and the region of the upper surface of the active region except the region connected with the source drain electrode from bottom to top, the upper surfaces of the source drain electrode and the active region are respectively provided with a first opening, parts of the upper surfaces of the source drain electrode and the source drain electrode are respectively exposed, the passivation layer is provided with a second opening on the gate dielectric layer between the source drain electrode and the source drain electrode, the upper surface of the gate dielectric layer is exposed, the second opening is also connected with a Г type gate electrode, the Г type gate electrode comprises a gate cap and a gate pin, the vertical edge part of the Г type is a gate pin, the transverse edge part is a gate cap, one end of the gate pin is connected with the lower surface of the gate cap.

Preferably, the material layer of the gate electrode is a metal layer or a metal nitride layer with more than three layers; the top material layer is more than one of Ni, TiN, WN, Cr and TiW; the material layer of the middle layer is Au or Al; the bottom material layer is more than one of TiN, WN, Cr and TiW; the total thickness of the gate electrode is 200-300 nm; the left width and the right width of the grid feet are 0.2-0.5 mu m; the left and right width of the gate cap is 0.4-1 μm.

preferably, the thickness of the AlGaN/GaN heterojunction epitaxial layer is 500-1000 μm, and the thickness of the active region is 100-300 nm.

Preferably, the source and drain electrodes are a Ti layer, an Al layer, a Ni layer and an Au layer which are sequentially deposited on the upper surface of the active region from bottom to top, and the thickness of the source and drain electrodes is 200-300 nm; the thicknesses of the Ti layer, the Al layer, the Ni layer and the Au layer are respectively 10-30nm, 80-120nm, 5-15nm and 80-120 nm.

Preferably, the gate dielectric layer is SiN; the thickness of the gate dielectric layer is 5-15 nm; the passivation layer is SiN or SiO₂The thickness of the passivation layer is 65-150 nm.

preferably, the left and right width of the second opening is 0.35-1 μm.

the invention also provides a method for preparing the GaN-based MIS-HEMT device with the Г type gate, which comprises the following steps:

(1) preparing and cleaning an AlGaN/GaN heterojunction epitaxial layer: preparing an AlGaN/GaN heterojunction epitaxial layer by Metal Organic Chemical Vapor Deposition (MOCVD), soaking the AlGaN/GaN heterojunction epitaxial layer in an acidic solution to remove a surface oxide layer, and removing organic matters on the AlGaN/GaN heterojunction epitaxial layer by adopting an organic solvent;

(2) Annealing the source and drain electrodes to form ohmic contact: defining metal positions and patterns of a source and drain electrode on an isolated active region by a negative photoresist photoetching process, and depositing the source and drain electrode; annealing at the temperature of more than 800 ℃ for 30-90s in the nitrogen atmosphere to enable the source drain electrode and the AlGaN barrier layer to form ohmic contact;

(3) Depositing a gate dielectric layer and a passivation layer: depositing a gate dielectric layer on the source drain electrode and the area outside the AlGaN/GaN heterojunction epitaxial layer, wherein the area is connected with the source drain electrode; depositing a passivation layer on the gate dielectric layer;

(4) Removing part of the passivation layer between the source electrode and the drain electrode: exposing the photoresist by a photoetching method to protect the area outside the second opening, removing the passivation layer with the thickness of 60-140nm by a physical etching method, and removing the rest passivation layer with the thickness of 5-10nm by a chemical etching method to expose the upper surface of the gate dielectric layer;

(5) Preparing a gate electrode by combining optical lithography with stripping or etching, namely exposing a gate electrode pattern at a second opening by using an I-line or G-line lithography machine, depositing a material layer of the gate electrode between a source electrode and a drain electrode by electron beam evaporation or magnetron sputtering, and preparing an Г -type gate electrode in a stripping mode, or depositing the material layer of the gate electrode by electron beam evaporation or magnetron sputtering, exposing a gate electrode pattern area at the second opening, and reducing the left and right widths of a gate cap and a gate pin by using anisotropic etching photoresist and etching the gate electrode material layer outside the gate electrode pattern area by using inductively coupled plasma to prepare a Г -type gate electrode;

(6) Opening of the source and drain electrodes: exposing the area outside the first opening protected by the photoresist through optical lithography, and removing the passivation layer and the gate dielectric layer at the first opening on the source and drain electrodes through inductive coupling plasma etching;

(7) and (3) forming an independent active region by isolation etching: defining an active area on the AlGaN/GaN epitaxial layer, and covering and protecting the active area by adopting photoresist; and removing the AlGaN/GaN heterojunction epitaxial layer outside the active region by utilizing inductively coupled plasma etching (ICP) or Reactive Ion Etching (RIE), wherein the etching depth is 100-300 nm.

Preferably, the method for depositing the source and drain electrodes is electron beam evaporation or magnetron sputtering.

Preferably, the method for depositing the gate dielectric layer is Metal Organic Chemical Vapor Deposition (MOCVD) or Low Pressure Chemical Vapor Deposition (LPCVD).

Preferably, the deposition method of the passivation layer is a plasma enhanced chemical vapor deposition PECVD.

Compared with the prior art, the invention has the following beneficial effects and advantages:

1) The gate dielectric layer adopts SiN grown by low-pressure chemical vapor deposition (LPCVD), has high compactness, and has much slower reaction with hydrofluoric acid compared with SiN grown by Plasma Enhanced Chemical Vapor Deposition (PECVD) in chemical property, so that the gate dielectric layer can be opened by a method combining physical etching and chemical etching, the damage of the physical etching to the gate dielectric layer is reduced, the electric leakage of a gate electrode is reduced, and the performance of a device is improved;

2) the low-pressure chemical vapor deposition LPCVD or the metal organic chemical vapor deposition MOCVD belong to mature processes of semiconductor industrial production, can be used in large-scale production, and can introduce a gate dielectric layer to improve the performance of devices;

3) the gate structure Г is introduced, so that the first advantage is that G-line and I-line photoetching including contact photoetching and step photoetching can be combined with a metal stripping process or a metal etching process, one part of gate metal is contacted with a gate dielectric layer, the other part is contacted with a passivation layer in an alignment mode at the opening of the passivation layer, the line width of a gate foot is greatly reduced under the limit line width of photoetching, and the second advantage is that a field plate is introduced through the Г gate structure, so that the electric field intensity distribution of a conductive channel on the side of a gate close to a drain is modulated.

drawings

FIG. 1 is a flowchart of a method for fabricating a GaN-based MIS-HEMT device with an Г gate structure according to an embodiment;

Fig. 2-10 are schematic diagrams during the fabrication of a GaN-based MIS-HEMT device with an Г gate structure according to an embodiment;

the figures show that: 1-AlGaN/GaN heterojunction epitaxial layer; 2-an active region; 3-source drain electrode; 4-a gate dielectric layer; 5-a passivation layer; 6-a gate electrode; 7-a photoresist layer; 8-gate electrode material layer.

Detailed Description

the following detailed description of the embodiments of the invention, taken in conjunction with the accompanying drawings and examples, is not intended to limit the invention or its application and protection, but it is noted that the following detailed description of the process or process parameters, if any, is within the skill of the art and may be made with reference to the prior art.