阅读说明：本技术 半导体结构及其形成方法 (Semiconductor structure and forming method thereof ) 是由 周飞 于 2018-06-08 设计创作，主要内容包括：一种半导体结构及其形成方法,方法包括：提供基底,包括衬底以及位于衬底上的鳍部,基底包括相邻接的第一区域和第二区域,鳍部沿延伸方向横跨第一区域和第二区域,第一区域基底内形成有阱区,第二区域基底内形成有漂移区；形成覆盖鳍部顶部表面和侧壁表面的栅氧化层；在第一区域和第二区域交界处的栅氧化层上形成栅极层,栅极层横跨鳍部且覆盖鳍部部分顶部和部分侧壁的栅氧化层；在栅极层一侧的阱区内形成源区,在栅极层另一侧的漂移区内形成漏区；形成源区和漏区后,依次刻蚀位于漏区一侧部分第二区域的栅极层、栅氧化层以及漂移区部分厚度基底,在漂移区内形成隔离槽；在隔离槽内形成隔离层。本发明有利于提升LDMOS的耐压性能。(A semiconductor structure and a method of forming the same, the method comprising: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate, the base comprises a first area and a second area which are adjacent, the fin part crosses the first area and the second area along an extension direction, a well area is formed in the base of the first area, and a drift area is formed in the base of the second area; forming a gate oxide layer covering the top surface and the side wall surface of the fin part; forming a gate layer on the gate oxide layer at the junction of the first area and the second area, wherein the gate layer crosses the fin part and covers the gate oxide layer on the partial top and partial side wall of the fin part; forming a source region in the well region on one side of the gate layer, and forming a drain region in the drift region on the other side of the gate layer; after forming a source region and a drain region, sequentially etching a gate layer, a gate oxide layer and a substrate with partial thickness in a drift region of a partial second region on one side of the drain region, and forming an isolation groove in the drift region; and forming an isolation layer in the isolation groove. The invention is beneficial to improving the voltage resistance of the LDMOS.)

1. A method of forming a semiconductor structure, comprising:

Providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate, the base comprises a first area and a second area which are adjacent, the fin part crosses the first area and the second area along an extension direction, a well region is formed in the base of the first area, a drift region is formed in the base of the second area, the well region and the drift region are provided with doped ions, and the type of the doped ions in the drift region is different from the type of the doped ions in the well region;

Forming a gate oxide layer covering the top surface and the side wall surface of the fin part;

Forming a gate layer on the gate oxide layer at the junction of the first area and the second area, wherein the gate layer crosses the fin part and covers the gate oxide layer on the partial top and partial side wall of the fin part;

Forming a source region in a first region fin part on one side of the gate layer, wherein the source region is positioned in the well region, forming a drain region in a second region fin part on the other side of the gate layer, the drain region is positioned in the drift region, the source region and the drain region are provided with doping ions, and the doping ions in the source region and the drain region are the same as the doping ions in the drift region in type;

After the source region and the drain region are formed, sequentially etching a gate layer, a gate oxide layer and a substrate with partial thickness of a drift region in a partial region on one side of the drain region in the second region, forming an isolation groove in the drift region, and covering the gate oxide layer at the junction of the first region and the second region by the residual gate layer;

And forming an isolation layer in the isolation groove.

2. The method as claimed in claim 1, wherein an opening of the isolation trench along the extending direction of the fin is 20nm to 200 nm.

3. The method of claim 1, wherein a distance from a bottom of the isolation trench to a top of the fin is defined asTo

4. The method of claim 1, wherein the isolation layer is made of a material selected from the group consisting of silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, silicon boron carbonitride, and silicon carbonitride.

5. The method of claim 1, wherein the isolation layer is formed by a process comprising a flowable chemical vapor deposition process or a high aspect ratio chemical vapor deposition process.

6. The method of forming a semiconductor structure of claim 1, wherein the step of forming the isolation trench comprises: and sequentially etching the gate layer, the gate oxide layer and the substrate material with partial thickness of the drift region in the partial region on one side of the drain region in the second region by adopting a dry etching process.

7. The method of forming a semiconductor structure of claim 1, further comprising, prior to forming the isolation layer within the isolation trench: and forming a protective layer on the bottom and the side wall of the isolation groove.

8. The method of claim 7, wherein the protective layer is made of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon boron carbonitride, silicon oxycarbide, silicon rich oxide, or amorphous silicon.

9. The method of forming a semiconductor structure of claim 7, wherein the process of forming the protective layer is an atomic layer deposition process.

10. The method of forming a semiconductor structure of claim 7, wherein the protective layer has a thickness ofTo

11. The method of forming a semiconductor structure of claim 1, wherein after forming the source and drain regions and before forming an isolation trench in the drift region, further comprising: forming an interlayer dielectric layer on the substrate with the exposed gate layer, wherein the interlayer dielectric layer covers the side wall of the gate layer;

in the step of forming the isolation groove, the isolation groove is surrounded by the interlayer dielectric layer, a residual gate layer located at the junction of the first region and the second region, a residual gate oxide layer and a residual drift region.

12. The method of forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, the substrate further comprises a single-diffusion rupture isolation region for forming a single-diffusion rupture isolation structure, the single-diffusion rupture isolation region having a fin portion with the gate oxide layer formed thereon and a gate layer on the gate oxide layer;

After the interlayer dielectric layer is formed on the substrate with the exposed gate layer, the method further comprises the following steps: etching to remove the gate layer of the single-diffusion-fracture isolation region, the gate oxide layer positioned below the gate layer and the substrate with partial thickness, wherein the interlayer dielectric layer and the residual substrate of the single-diffusion-fracture isolation region form a groove in a surrounding manner; filling an isolation material in the groove to form a single diffusion fracture isolation structure;

In the step of forming the trench, forming the isolation trench;

In the step of forming the single diffusion rupture isolation structure in the trench, the isolation layer is formed in the isolation trench.

13. The method of forming a semiconductor structure of claim 1, further comprising, after forming an isolation layer within the isolation trench: and forming an interlayer dielectric layer on the substrate with the exposed gate layer, wherein the interlayer dielectric layer covers the side wall of the gate layer.

14. The method of forming a semiconductor structure of claim 13, wherein after forming the source and drain regions and before forming isolation trenches in the drift region, further comprising: forming a filling layer on the substrate exposed out of the gate layer, wherein the filling layer covers the side wall of the gate layer;

In the step of forming the isolation groove, the isolation groove is surrounded by the filling layer, a residual gate layer located at the junction of the first region and the second region, a residual gate oxide layer and a residual drift region;

After forming the isolation layer in the isolation groove, before forming the interlayer dielectric layer on the substrate with the exposed residual gate layer, the method further comprises the following steps: and removing the filling layer.

15. The method of claim 14, wherein the fill layer is a bottom anti-reflective coating material, a dielectric anti-reflective coating material, a deep ultraviolet light absorbing oxide material, an organic dielectric material, an advanced patterning film material, amorphous carbon, or amorphous silicon.

16. A semiconductor structure, comprising:

The substrate comprises a substrate and a fin part positioned on the substrate, the substrate comprises a first area and a second area which are adjacent, the fin part crosses the first area and the second area along the extension direction, a well area is formed in the substrate of the first area, a drift area is formed in the substrate of the second area, doped ions are arranged in the well area and the drift area, and the type of the doped ions in the drift area is different from that of the doped ions in the well area;

The gate oxide layer is positioned on the top surface and the side wall surface of the fin part;

The gate layer is positioned on the gate oxide layer at the junction of the first area and the second area, spans the fin part and covers the gate oxide layer on the partial top and partial side wall of the fin part;

The source region is positioned in the first region fin part on one side of the grid layer and positioned in the well region, doped ions are arranged in the source region, and the types of the doped ions in the source region are the same as those of the doped ions in the drift region;

The drain region is positioned in the fin part of the second region on the other side of the gate layer and positioned in the drift region, doped ions are arranged in the drain region, and the types of the doped ions in the drain region and the doped ions in the drift region are the same;

And the isolation layer penetrates through the second region gate oxide layer between the gate layer and the drain region and a part of thickness substrate, and is positioned in the drift region.

17. The semiconductor structure of claim 16, wherein a width of the isolation layer along an extension direction of the fin is 20nm to 200 nm.

18. The semiconductor structure of claim 16, wherein a distance from a bottom of the isolation layer to a top of the fin isTo

19. The semiconductor structure of claim 16, wherein a material of the isolation layer is silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon boron carbonitride, or silicon carbonitride.

20. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: and the protective layer is positioned between the isolation layer and the drift region.

21. The semiconductor structure of claim 20, wherein the material of the protective layer is silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon boron carbonitride, or silicon oxycarbide, silicon rich oxide, or amorphous silicon.

22. the semiconductor structure of claim 20, wherein the protective layer has a thickness ofTo

23. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: the interlayer dielectric layer is positioned on the substrate exposed out of the gate layer and covers the side wall of the gate layer;

And the isolation layer also extends to the top of the interlayer dielectric layer along the normal direction of the surface of the substrate.

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

As semiconductor chips are widely used, factors causing electrostatic damage to the semiconductor chips are increasing. In the conventional chip design, an Electrostatic Discharge (ESD) protection circuit is often used to reduce chip damage. The design and application of the existing electrostatic discharge protection circuit include: a Gate Grounded N-type field effect Transistor (GGNMOS) protection circuit, a Silicon Controlled Rectifier (SCR) protection circuit, a Lateral Double Diffused MOSFET (LDMOS) protection circuit, a Bipolar Junction Transistor (BJT) protection circuit, etc. Among them, LDMOS is widely used for ESD protection because it can withstand higher breakdown voltage.

In order to improve the pressure resistance, a drift region is arranged between the source region and the drain region, and the doping concentration of the drift region is low. Therefore, when the LDMOS is connected with high voltage, the drift region has higher partial voltage due to larger resistance, and can bear higher voltage.

With the trend toward very large scale integrated circuits, the feature sizes of integrated circuits continue to decrease. Planar LDMOS devices have failed to meet the technical requirements, and LDMOS devices are gradually shifting to three-dimensional transistors with higher performance, such as fin field effect transistors.

However, after the fin field effect transistor is introduced into the LDMOS, the voltage resistance of the LDMOS still needs to be improved.

disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can improve the voltage resistance of LDMOS.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a fin part positioned on the substrate, the base comprises a first area and a second area which are adjacent, the fin part crosses the first area and the second area along an extension direction, a well region is formed in the base of the first area, a drift region is formed in the base of the second area, the well region and the drift region are provided with doped ions, and the type of the doped ions in the drift region is different from the type of the doped ions in the well region; forming a gate oxide layer covering the top surface and the side wall surface of the fin part; forming a gate layer on the gate oxide layer at the junction of the first area and the second area, wherein the gate layer crosses the fin part and covers the gate oxide layer on the partial top and partial side wall of the fin part; forming a source region in a first region fin part on one side of the gate layer, wherein the source region is positioned in the well region, forming a drain region in a second region fin part on the other side of the gate layer, the drain region is positioned in the drift region, the source region and the drain region are provided with doping ions, and the doping ions in the source region and the drain region are the same as the doping ions in the drift region in type; after the source region and the drain region are formed, sequentially etching a gate layer, a gate oxide layer and a substrate with partial thickness of a drift region in a partial region on one side of the drain region in the second region, forming an isolation groove in the drift region, and covering the gate oxide layer at the junction of the first region and the second region by the residual gate layer; and forming an isolation layer in the isolation groove.

Accordingly, the present invention also provides a semiconductor structure comprising: the substrate comprises a substrate and a fin part positioned on the substrate, the substrate comprises a first area and a second area which are adjacent, the fin part crosses the first area and the second area along the extension direction, a well area is formed in the substrate of the first area, a drift area is formed in the substrate of the second area, doped ions are arranged in the well area and the drift area, and the type of the doped ions in the drift area is different from that of the doped ions in the well area; the gate oxide layer is positioned on the top surface and the side wall surface of the fin part; the gate layer is positioned on the gate oxide layer at the junction of the first area and the second area, spans the fin part and covers the gate oxide layer on the partial top and partial side wall of the fin part; the source region is positioned in the first region fin part on one side of the grid layer and positioned in the well region, doped ions are arranged in the source region, and the types of the doped ions in the source region are the same as those of the doped ions in the drift region; the drain region is positioned in the fin part of the second region on the other side of the gate layer and positioned in the drift region, doped ions are arranged in the drain region, and the types of the doped ions in the drain region and the doped ions in the drift region are the same; and the isolation layer penetrates through the second region gate oxide layer between the gate layer and the drain region and a part of thickness substrate, and is positioned in the drift region.

Compared with the prior art, the technical scheme of the invention has the following advantages:

After a source region and a drain region are formed, a grid electrode layer, a grid oxide layer and a substrate with partial thickness corresponding to a drift region in a second region are etched in sequence, wherein the grid electrode layer and the grid oxide layer are positioned in a partial region on one side of the drain region; the isolation layer is formed in the drift region between the rest gate layer and the drain region, when the device works, current flows out of the drain region, bypasses the isolation layer, flows to the fin portion at the bottom of the rest gate layer, and flows to the source region through the fin portion at the bottom of the rest gate layer, namely, the current flow path comprises the side wall and the bottom of the isolation layer in the drift region, so that the length of the current flow path can be prolonged due to the arrangement of the isolation layer, the voltage gradient on the current flow path is reduced, and the voltage withstanding performance of the LDMOS is improved.

Furthermore, no gate oxide layer is formed on the side wall of the isolation groove close to one side of the gate layer, so that the problem of breakdown of the gate oxide layer on the current circulation path can be correspondingly avoided, and the voltage withstanding performance of the LDMOS is further improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIGS. 2 to 12 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;

FIGS. 13-17 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention;

FIG. 18 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As known from the background art, after the fin field effect transistor is introduced into the LDMOS, the voltage endurance of the LDMOS needs to be improved. The reason why the voltage resistance of a semiconductor structure needs to be improved is analyzed in combination with the semiconductor structure.

Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.

The semiconductor structure includes: the substrate 100 comprises a first region I and a second region II which are adjacent, the fin portion located at the junction of the first region I and the second region II is a first fin portion 101, and the fin portion located in the second region II is a second fin portion 102; a well region 112 located in the fin portion of the first region I and the substrate 100; a drift region 111 located in the fin portion of the second region II and the substrate 100; the isolation structure 113 is located on the substrate 100 where the fin portions are exposed, and the isolation structure 113 covers partial sidewalls of the first fin portion 101 and the second fin portion 102; a gate structure 104 located on the isolation structure 113, wherein the gate structure 104 covers a part of the sidewall surface and the top surface of the first fin portion 101 and spans the first region I and the second region II, and the gate structure 104 includes a gate oxide layer 114 and a gate layer 124 located on the gate oxide layer 114; a source region 121 located in the first fin 101 on one side of the gate structure 104; and the drain region 122 is positioned in the second fin portion 102 on the other side of the gate structure 104.

Taking the semiconductor structure as an N-type semiconductor structure as an example, the type of the doped ions in the source region 121, the drain region 122 and the drift region 111 is N-type, and the type of the doped ions in the well region 112 is P-type. When the static electricity is discharged, a large voltage generated by the static electricity is applied to the drain region 122, the channel of the LDMOS is turned on, and therefore, a path is generated from the drain region 122 to the source region 121, a current flows out from the drain region 122 to the source region 121 via the channel under the gate structure 104, the path of the current includes the sidewall and the bottom of the isolation structure 113 (as shown by the dashed arrow in fig. 1), and the voltage gradually decreases along the path.

with the continuous improvement of the element density and the integration of the semiconductor device, along the extending direction of the fin portion, the distance between the drain region 122 and the gate structure 104 is gradually reduced, and the distance between the drain region 122 and the source region 121 is gradually reduced, so that the current flowing path is shorter, the voltage gradient on the current flowing path is correspondingly larger, and the improvement of the voltage resistance of the LDMOS is further influenced.

Moreover, the gate oxide layer 114 is formed on the sidewall of the first fin 101 on one side of the second region II (at a position shown by a dashed line frame a in fig. 1), and the gate oxide layer 114 on the sidewall of the first fin 101 is also prone to be broken down due to a large voltage gradient.

In order to solve the technical problem, after a source region and a drain region are formed, a grid layer, a grid oxide layer and a substrate with partial thickness corresponding to a drift region in a partial region on one side of the drain region in a second region are etched in sequence, an isolation groove is formed in the residual drift region, the residual grid layer covers the grid oxide layer at the junction of the first region and the second region, and then an isolation layer is formed in the isolation groove; when the device works, current flows out from the drain region, flows to the fin part at the bottom of the grid electrode layer by bypassing the isolation layer, and flows to the source region through the fin part at the bottom of the grid electrode layer, namely the current circulation path comprises the side wall and the bottom of the isolation layer in the drift region, so that the length of the current circulation path is prolonged by the arrangement of the isolation layer, the voltage gradient on the current circulation path is reduced, and the voltage withstanding performance of the LDMOS is improved.

And moreover, no gate oxide layer is formed on the side wall of the isolation groove close to one side of the gate layer, so that the problem of breakdown of the gate oxide layer on the current circulation path can be correspondingly avoided, and the voltage resistance of the LDMOS is further improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2 to 4 in combination, fig. 2 is a perspective view (only one fin portion is shown), fig. 3 is a schematic cross-sectional view of fig. 2 taken along a cut line perpendicular to an extending direction of the fin portion (for example, along direction AA1 in fig. 2), fig. 4 is a schematic cross-sectional view of fig. 2 taken along a cut line along the extending direction of the fin portion (for example, along direction BB1 in fig. 2), a base (not labeled) is provided, the base includes a substrate 200 and a fin portion 210 on the substrate 200, the base includes a first region i (shown in fig. 4) and a second region ii (shown in fig. 4) which are adjacent to each other, the fin portion 210 crosses the first region i and the second region ii along the extending direction, wherein a well region 211 (shown in fig. 4) is formed in the base of the first region i, a drift region 212 (shown in fig. 4) is formed in the base of the second region ii, and the well region 211 and the drift region 212 have doped ions, and the type of doped ions in the drift region 212 is different from the type of doped ions in the well region 211.

The substrate 200 is used to provide a process platform for the subsequent formation of semiconductor structures. Specifically, the formed semiconductor structure is an LDMOS.

In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the fin portion 210 crosses the first region i and the second region ii along the extending direction, that is, along the extending direction of the fin portion 210, the first region i and the second region ii share one fin portion 210; the fin portion 210 located in the first region i is used for providing a channel of a fin field effect transistor, and the fin portion 210 located in the second region ii is used for prolonging the distance between a source region and a drain region of the fin field effect transistor, so that the length of a circulation path of current when the channel of the fin field effect transistor is turned on is prolonged, and the voltage resistance of the LDMOS is improved.

In this embodiment, the material of the fin portion 210 is the same as the material of the substrate 200, and the material of the fin portion 210 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.

it should be noted that, in order to simplify the process steps for forming fin 210 and substrate 200, substrate 200 and fin 210 are formed simultaneously. Specifically, the steps of forming the fin 210 and the substrate 200 include: providing an initial substrate; patterning the initial base through a photoetching and etching process, wherein the rest of the patterned initial base serves as the substrate 200, and the protrusion on the substrate 200 serves as the fin portion 210. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

It should be further noted that, after the substrate 200 and the fin portion 210 are formed, the method further includes: forming an isolation structure 201 on the substrate 200 exposed by the fin portion 210, wherein the isolation structure 201 covers a part of the sidewall of the fin portion 210, and the top of the isolation structure 201 is lower than the top of the fin portion 210.

in this embodiment, the fin 210 crosses the first region i and the second region ii along the extending direction, so along the extending direction of the fin 210, the isolation structure 201 is located on the first region i substrate 200 on one side of the fin 210 and on the second region ii substrate 200 on the other side of the fin 210.

In this embodiment, the isolation structure 201 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

the well region 211 and the drift region 212 are in contact with each other, the well region 211 and the drift region 212 are located in the substrate and are sequentially arranged along the extending direction of the fin portion 210, the well region 211 serves as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 212 is used for bearing a larger partial pressure.

In this embodiment, the well region 211 is located in the fin portion 210 of the first region i and the portion of the thickness substrate 200 below the fin portion 210, and the drift region 212 is located in the fin portion 210 of the second region ii and the portion of the thickness substrate 200 below the fin portion 210. In other embodiments, the well region and the drift region may be located only within the fin portion.

Note that, for convenience of illustration, the well region 211 and the drift region 212 are not illustrated in fig. 1 and fig. 2.

The well region 211 and the drift region 212 have doped ions therein, and the type of the doped ions in the drift region 212 is different from the type of the doped ions in the well region 211. In this embodiment, the LDMOS is an N-type semiconductor structure, the doped ions In the well region 211 are P-type ions, and the P-type ions include B ions, Ga ions, or In ions; the doped ions in the drift region 212 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions.

Specifically, after the fin portion 210 is formed and before the isolation structure 201 is formed, P-type doping processing is performed on the fin portion 210 and the substrate 200 in the first region i, the well region 211 is formed in the fin portion 210 and the substrate 200 in the first region i, N-type doping processing is performed on the fin portion 210 and the substrate 200 in the second region ii, and the drift region 212 is formed in the fin portion 210 and the substrate 200 in the second region ii.

It should be noted that, in other embodiments, before the substrate and the fin portion are formed, P-type doping processing may be performed on the initial base corresponding to the first region to form the well region, and N-type doping processing may be performed on the initial base corresponding to the second region to form the drift region. In other embodiments, the well region and the drift region may also be formed after the isolation structure is formed.

Referring to fig. 5, a gate oxide layer 220 is formed covering the top surface and sidewall surfaces of the fin 210.

in this embodiment, the gate oxide layer 220 is made of silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

In this embodiment, the gate oxide layer 220 is formed by performing oxidation treatment on the fin portion 210, so that the formation quality and density of the gate oxide layer 220 are improved. Specifically, the process formed by the oxidation treatment may be an In-situ water vapor Generation oxidation (ISSG) process. Correspondingly, the gate oxide layer 220 covers the top surface and the sidewall surface of the fin portion 210 exposed by the isolation structure 201.

referring to fig. 6, a gate layer 230 is formed on the gate oxide layer 220 at the boundary of the first region i and the second region ii, the gate layer 230 crosses over the fin 210 and covers the gate oxide layer 220 on part of the top and part of the sidewall of the fin 210.

In this embodiment, the gate layer 230 serves as a dummy gate layer, and the gate layer 230 occupies a space for forming a gate electrode layer.

The material of the gate layer 230 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials. In this embodiment, the material of the gate layer 230 is polysilicon. In other embodiments, the material of the gate layer may also be a metal material, that is, the gate layer may also be the gate electrode layer.

The gate layer 230 is formed on the gate oxide layer 220 at the junction of the first region i and the second region ii, and along the extending direction of the fin 210, a part of the well region 211 is exposed on one side of the gate layer 230, and a part of the drift region 212 is exposed on the other side of the gate layer 230, so that a process basis is provided for the subsequent formation of a source region and a drain region.

Specifically, the step of forming the gate layer 230 includes: forming a gate material layer crossing the fin portion 210 on the gate oxide layer 220; forming a gate mask layer 240 on the gate material layer; and etching the gate material layer by taking the gate mask layer 240 as a mask to expose part of the gate oxide layer 220, taking the etched residual gate material layer as the gate layer 230, and covering part of the top and part of the side wall of the gate oxide layer 220 by the gate layer 230.

Note that after the gate layer 230 is formed, the gate mask layer 240 on the top of the gate layer 230 is remained. The gate mask layer 240 is made of silicon nitride, and the gate mask layer 240 is used for protecting the top of the gate layer 230 in a subsequent process.

With continuing reference to fig. 6, after forming the gate layer 230, the method further includes: side walls 250 are formed on the sidewalls of the gate layer 230.

The sidewall spacers 250 may serve as an etching mask for a subsequent etching process, and are used to define formation regions of subsequent source and drain regions, and also used to protect sidewalls of the gate layer 230 during the subsequent etching process.

The sidewall 250 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 250 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 250 has a single-layer structure, and the material of the sidewall spacer 250 is silicon nitride.

In this embodiment, a gate mask layer 240 is formed on the top of the gate layer 230, so the sidewall spacers 250 also cover the sidewalls of the gate mask layer 240. In order to simplify the process steps, after the sidewall spacers 250 are formed, the gate oxide layer 220 exposed from the sidewall spacers 250 is retained.

referring to fig. 7, a source region 261 is formed in the first region ipfin 210 (shown in fig. 3) on one side of the gate layer 230, a drain region 262 is formed in the second region ipfin 210 on the other side of the gate layer 230, the source region 261 and the drain region 262 have doping ions therein, and the doping ions in the source region 261 and the drain region 262 are the same as the doping ions in the drift region 212.

When static electricity is discharged, a large voltage generated by the static electricity is applied to the drain region 262, so that a PN junction formed by the drift region 212 and the well region 211 breaks down, and further an NPN bipolar junction transistor formed by the drift region 212, the well region 211, and the source region 261 is turned on, that is, a channel in the fin portion 210 under the gate layer 230 is turned on, and a path is generated from the drain region 262 to the source region 261 for releasing the static electricity, thereby functioning as a protection circuit.

In this embodiment, the fin 210 crosses the first region i and the second region ii along the extending direction, and the gate layer 230 is formed on the gate oxide layer 220 at the boundary between the first region i and the second region ii, so that the source region 261 is formed in the well region 211 on one side of the fin 210, and the drain region 262 is formed in the drift region 212 on the other side of the fin 210.

In this embodiment, the LDMOS is an N-type semiconductor structure, and the doped ions in the drift region 212 are N-type ions, so the doped ions in the source region 261 and the drain region 262 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions.

Specifically, the step of forming the source region 261 and the drain region 262 includes: a first stress layer doped with N-type ions is formed in the first region i fin 210 on one side of the gate layer 230, and a second stress layer doped with N-type ions is formed in the second region ii fin 210 on the other side of the gate layer 230.

in this embodiment, the first stress layer and the second stress layer are made of Si or SiC materials, and may be respectively formed in the well region 211 and the drift region 212 by epitaxial growth, and the N-type ions are doped in an in-situ self-doping manner during the epitaxial growth. In other embodiments, after the first stress layer and the second stress layer are formed, an N-type ion doping process may be performed on the first stress layer and the second stress layer.

With reference to fig. 8 to fig. 9, after the source region 261 and the drain region 262 are formed, the gate mask layer 240, the gate layer 230, the gate oxide layer 220 and the substrate with a partial thickness of the drift region 212 in the second region ii on one side of the drain region 262 are sequentially etched, an isolation trench 270 is formed in the remaining drift region 212 (as shown in fig. 9), and the remaining gate layer 230 after etching covers the gate oxide layer 220 at the boundary between the first region i and the second region ii.

The isolation trench 270 provides a spatial location for subsequent isolation layer formation.

Specifically, the subsequent isolation layer is formed in the drift region 212 between the remaining gate layer 230 and the drain region 262, and when the device operates, a current flows from the drain region 262, and the current bypasses the isolation layer to flow to the fin 210 at the bottom of the remaining gate layer 230 and flows to the source region 261 through the fin 210 (shown in fig. 2) at the bottom of the remaining gate layer 230 (i.e., the channel under the gate layer 230), that is, the flow path of the current includes the sidewall and the bottom of the isolation layer located in the drift region 212, so that the length of the flow path of the current can be extended, the voltage gradient in the current path can be reduced, and the voltage withstanding performance of the LDMOS can be improved.

Moreover, the gate oxide layer 220 is not formed on the sidewall of the isolation trench 270 close to the remaining gate layer 230 (as shown in the position indicated by the dashed line frame B in fig. 9), which can also avoid the problem of breakdown of the gate oxide layer 220 on the current path, and is beneficial to further improving the voltage endurance of the LDMOS.

When the device is in operation, the current path includes the sidewalls and bottom of the isolation layer in the drift region 212, so that the distance H from the bottom of the isolation trench 270 to the top of the fin 210 is increased, which is beneficial to extending the length of the current path. Therefore, if the distance H is too small, the effect of extending the length of the current path is relatively poor when the device works, so that the effect of improving the voltage resistance of the LDMOS is relatively poor; however, if the distance H is too large, the thickness T of the base material corresponding to the residual drift region 212 at the bottom of the isolation trench 270 is too small, which is likely to adversely affect the current flow, and the too large distance H may cause a problem of too large aspect ratio of the isolation trench 270, which is likely to cause a reduction in the quality of the subsequent isolation layer formation. Therefore, in the present embodiment, the distance H from the bottom of the isolation trench 270 to the top of the fin 210 isToThe top of the fin 210 is the top of the well 211 and the drift 212.

similarly, increasing the opening dimension W1 of the isolation trench 270 along the extending direction of the fin 210 also facilitates extending the length of the current path. If the opening size W1 is too small, the effect of prolonging the length of the current circulation path is relatively poor, so that the effect of improving the voltage resistance of the LDMOS is poor; if the opening size W1 of the isolation trench 270 is too large, the width W2 of the base material corresponding to the drift region 212 under the remaining gate layer 230 along the extending direction of the fin 210 is too small, which is likely to adversely affect the current flow, and too small the opening size W1 may cause the aspect ratio of the isolation trench 270 to be too large, resulting in a reduction in the quality of the subsequent isolation layer formation. For this reason, in the present embodiment, along the extending direction of the fin 210, the opening dimension W1 of the isolation trench 270 is 20nm to 200 nm.

In this embodiment, by reasonably setting the distance H from the bottom of the isolation trench 270 to the top of the fin 210 and the opening dimension W1 of the isolation trench 270, and matching the distance H with the opening dimension W1, the length of the current flowing path is effectively extended, and at the same time, the problem of an excessively large aspect ratio of the isolation trench 270 is avoided, and the influence on the normal use function of the LDMOS is reduced.

in this embodiment, the step of forming the isolation trench 270 includes: and sequentially etching the gate layer 230, the gate oxide layer 220 and the substrate material with partial thickness corresponding to the drift region 212 in the partial region on one side of the drain region 262 in the second region II by adopting a dry etching process. The dry etching process has anisotropic etching characteristics, thereby being beneficial to improving the appearance quality of the isolation trench 270 and better controlling the position of the isolation trench 270 in the drift region 212.

In this embodiment, in order to effectively extend the length of the current flowing path, the material of the fin 210 and the material of the substrate 200 with a partial thickness corresponding to the drift region 212 are etched by the dry etching process, that is, the bottom surface of the trench 270 is lower than the top surface of the substrate 200. In other embodiments, the fin material of a portion of the thickness corresponding to the drift region may be etched, that is, the bottom surface of the trench is higher than the top surface of the substrate.

With continued reference to fig. 8, in this embodiment, after forming the source region 261 and the drain region 262, before forming the isolation trench 270 (as shown in fig. 9) in the remaining drift region 212, the method further includes: an interlayer dielectric layer 202 is formed on the substrate 200 exposed by the gate layer 230, and the interlayer dielectric layer 202 covers the sidewalls of the gate layer 230.

The interlayer dielectric layer 202 is used for realizing electrical isolation between adjacent semiconductor structures, and the interlayer dielectric layer 202 is also used for defining the size and the position of a subsequent gate electrode layer.

the interlayer dielectric layer 202 is made of an insulating material. In this embodiment, the interlayer dielectric layer 202 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

Specifically, the step of forming the interlayer dielectric layer 202 includes: forming a dielectric material layer on the substrate 200 exposed by the gate layer 230, wherein the dielectric material layer covers the top of the gate layer 230; and performing planarization treatment on the dielectric material layer, and removing the dielectric material layer higher than the top of the gate layer 230, wherein the residual dielectric material layer after the planarization treatment is used as the interlayer dielectric layer 202.

In this embodiment, the gate mask layer 240 is formed on the top of the gate layer 230, and in order to reduce the difficulty of the process for forming the dielectric material layer, the dielectric material layer covers the top of the gate mask layer 240; therefore, in the planarization process, the gate mask layer 240 is used to define a stop position of the planarization process, that is, after the planarization process, the interlayer dielectric layer 202 exposes the top of the gate mask layer 240.

After the interlayer dielectric layer 202 is formed, the top of the gate electrode layer 230 is protected in a subsequent process by retaining the gate mask layer 240, and a stop position can be defined at the top of the gate mask layer 240 in a subsequent planarization process.

Accordingly, the isolation trench 270 (as shown in fig. 9) extends to the top of the interlayer dielectric layer 202 along the normal direction of the surface of the substrate 200. That is, the isolation trench 270 is surrounded by the interlayer dielectric layer 202 located in the second region ii, the remaining gate layer 230 located at the boundary between the first region i and the second region ii, the remaining gate oxide layer 220, and the remaining drift region 212.

Specifically, the isolation trench 270 exposes a sidewall of the remaining gate layer 230 on one side of the second region ii, and also exposes a sidewall 250 of the second region ii.

In this embodiment, by forming the isolation trench 270 after the formation of the interlayer dielectric layer 202, the process for forming the interlayer dielectric layer 202 can be prevented from affecting the isolation trench 270. Moreover, after the isolation trench 270 is formed, the interlayer dielectric layer 202 can also support the sidewall 250 located in the second region ii, so as to avoid the problem of collapse of the sidewall 250, and the interlayer dielectric layer 202 can also protect the substrate, the isolation structure 201, the source region 261 and the drain region 262, so that the influence of the process for forming the isolation trench 270 on the performance of the semiconductor structure is reduced.

it should be noted that, in order to reduce the process cost for forming the semiconductor structure and simplify the process steps for forming the semiconductor structure, the isolation trench 270 and the isolation layer subsequently formed in the isolation trench 270 are formed in the process of forming a Single diffusion rupture (SDB) isolation structure.

Specifically, the substrate typically further includes a single-diffusion-rupture isolation region (not shown) for forming a single-diffusion-rupture isolation structure, wherein the gate oxide layer 220 is formed on the fin portion 210 (shown in fig. 2) of the single-diffusion-rupture isolation region, and the gate layer 230 is located on the gate oxide layer 220.

Therefore, after the forming the interlayer dielectric layer 202 on the substrate 200 exposed by the gate layer 230, the method further includes: etching to remove the gate layer 230 of the single diffusion rupture isolation region, the gate oxide layer 220 located below the gate layer 230, and a substrate with a partial thickness, wherein a trench (not shown) is surrounded by the interlayer dielectric layer 202 and the remaining substrate of the single diffusion rupture isolation region; and filling an isolation material in the groove to form a single diffusion fracture isolation structure.

In this embodiment, the gate layer 230 of the single-diffusion rupture isolation region, the gate oxide layer 220 located below the gate layer 230, the fin 210, and the substrate 200 with a partial thickness are etched away to form the trench, and in the process step of forming the trench, the isolation trench 270 is formed. That is, the isolation trench 270 and the trench are formed in the same process step.

Referring to fig. 10 and 11 in combination, an isolation layer 290 (shown in fig. 11) is formed within the isolation trench 270 (shown in fig. 10).

The isolation layer 290 is used to isolate the drain region 262 from a channel below the gate layer 230, so as to prevent current from flowing into the channel from the drain region 262 directly along the extending direction of the fin 210.

For this purpose, the material of the isolation layer 290 is an insulating material. In this embodiment, the material of the isolation layer 290 is silicon oxide. The silicon oxide is an insulating material commonly used in a semiconductor process, has high process compatibility, has low cost, and is beneficial to reducing the process cost for forming the semiconductor structure.

In other embodiments, the material of the isolation layer may also be silicon oxynitride, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon boron oxycarbonitride, or silicon carbonitride.

In this embodiment, the process of forming the isolation layer 290 includes a Flowable Chemical Vapor Deposition (FCVD) process. By adopting the flowable chemical vapor deposition process, the material for forming the isolation layer 290 has a good filling effect in the isolation trench 270, thereby improving the formation quality of the isolation layer 290 in the isolation trench 270.

In other embodiments, the isolation layer may also be formed by a High Aspect Ratio Process (HARP) Chemical Vapor Deposition Process (CVD). The high aspect ratio chemical vapor deposition process can meet the filling requirement of the opening with the higher aspect ratio, so that the filling effect of the material of the isolation layer in the isolation groove can be improved by adopting the high aspect ratio chemical vapor deposition process.

It should be noted that the isolation trench 270 and the isolation layer 290 are formed during a process of forming a single-diffusion rupture isolation structure, so that the isolation layer 290 is formed in the isolation trench 270 in the step of forming the single-diffusion rupture isolation structure in the trench (not shown). That is, the single diffusion rupture isolation structure and the isolation layer 290 may be formed in the same process step, which accordingly reduces the process cost for forming the semiconductor structure and simplifies the process steps for forming the semiconductor structure.

With continuing reference to fig. 10 and 11, in this embodiment, before forming the isolation layer 290 (as shown in fig. 11) in the isolation trench 270, the method further includes: a protective layer 280 is formed on the bottom and sidewalls of the isolation trench 270 (as shown in fig. 11).

the protection layer 280 is used to protect the substrate material exposed by the isolation trench 270 (as shown in fig. 10) during the process of forming the isolation layer 290, so as to prevent the substrate material from being consumed by the process of forming the isolation layer 290, thereby preventing the formation of the isolation layer 290 from adversely affecting the performance of the semiconductor structure.

Since the semiconductor structure retains the protection layer 280, the material of the protection layer 280 is also an insulating material in order to reduce the impact on the performance of the semiconductor structure.

In this embodiment, the material of the protection layer 280 is silicon nitride (SiN). The density of the silicon nitride material is higher, so that the probability of loss of the substrate exposed by the isolation groove 270 can be effectively reduced by selecting the silicon nitride material. In other embodiments, the material of the protective layer may also be silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOCN), silicon-rich oxide, or amorphous silicon.

It should be noted that the thickness (not labeled) of the protection layer 280 should not be too small, and should not be too large. If the thickness of the protective layer 280 is too small, the protective effect of the protective layer 280 on the substrate is correspondingly reduced; if the thickness of the protection layer 280 is too large, the process cost and time are wasted, and the size of the remaining space of the isolation trench 270 is reduced, which may adversely affect the filling quality of the isolation layer 290 in the isolation trench 270. For this purpose, in this embodiment, the thickness of the protection layer 280 isTo

In this embodiment, in order to prevent the process of forming the protection layer 280 from consuming the material of the substrate, a deposition process is used to form the protection layer 280. Specifically, the deposition process is an Atomic Layer Deposition (ALD) process.

Through an atomic layer deposition process, the material of the protection layer 280 is formed on the bottom and the sidewall of the isolation trench 270 in the form of an atomic layer, so that the uniformity of the deposition rate, the thickness uniformity of the protection layer 280 and the structural uniformity in the protection layer 280 are improved, and the protection layer 280 has good conformal coverage capability; in addition, the process temperature of the ald process is typically low, which is beneficial to reduce the Thermal Budget (Thermal Budget) and the impact of the process for forming the protection layer 280 on the device performance.

therefore, in this embodiment, before forming the isolation layer 290 in the isolation trench 270, a protection film 285 (as shown in fig. 10) is formed on the bottom and the sidewall of the isolation trench 270, and the protection film 285 also covers the top of the gate layer 230 and the top of the interlayer dielectric layer 202.

Accordingly, the step of forming the isolation layer 290 (shown in fig. 11) includes: filling an isolation material layer in the isolation groove 270, wherein the isolation material layer covers the top of the protective film 285; and removing the isolation material layer and the protective film 285 above the top of the gate layer 230 by using a planarization process, leaving the residual protective film 285 on the bottom and the side wall of the isolation groove 270 as the protective layer 280, and leaving the residual isolation material layer in the isolation groove 270 as the isolation layer 290.

In the planarization process, the top of the gate mask layer 240 is used as a stop position, so that the probability of damage to the gate layer 230 can be reduced. Accordingly, after the isolation layer 290 is formed, the gate mask layer 240 is removed.

In this embodiment, after the isolation layer 290 is formed, the top of the interlayer dielectric layer 202 is flush with the top of the gate layer 230.

It should be further noted that, in this embodiment, the gate layer 230 is a dummy gate layer, and therefore, with reference to fig. 12, after the forming of the isolation layer 290, the method further includes: the gate layer 230 is removed (as shown in fig. 11), and a gate electrode layer 300 is formed at the location of the gate layer 230.

In this embodiment, the material of the gate electrode layer 300 is W. In other embodiments, the material of the gate electrode layer may also be a conductive material such as Al, Cu, Ag, Au, Pt, Ni, or Ti.

it should be noted that, since the LDMOS is a high-voltage device, that is, the threshold voltage of the semiconductor structure is higher, in this embodiment, according to the actual process requirement, after the gate layer 230 is removed, the gate oxide layer 220 is retained.

Fig. 13 to 17 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: after forming an isolation layer 690 (shown in fig. 15) in the isolation trench 670 (shown in fig. 14), an interlayer dielectric layer 602 (shown in fig. 17) is formed on the substrate 600 (shown in fig. 17) exposed by the remaining gate layer 630 (shown in fig. 17), wherein the interlayer dielectric layer 602 covers the sidewalls of the gate layer 630.

By forming the interlayer dielectric layer 602 after forming the isolation layer 690, the quality of the interlayer dielectric layer 602 can be prevented from being affected by the process of forming the isolation groove 670 and the isolation layer 690, so that the performance of the interlayer dielectric layer 602 is prevented from being affected, and the performance of the formed semiconductor structure can be improved.

Specifically, referring to fig. 13, after forming a source region 661 and a drain region 662, a filling layer 700 is formed on the substrate 600 exposed by the gate layer 630, and the filling layer 700 covers the sidewalls of the gate layer 630.

The filling layer 700 is used to provide a process platform for the subsequent formation of the isolation trench 670 (shown in fig. 15) and the isolation layer 690 (shown in fig. 16), so as to improve the process operability, and the filling layer 700 can also protect the substrate, the gate layer 630, the isolation structure 601, the source region 661, and the drain region 662 in the subsequent process, so as to reduce the influence of the process for forming the isolation trench 670 on the performance of the semiconductor structure, and after the isolation trench 670 is formed subsequently, the filling layer 700 can also support the sidewall 650 located in the second region ii, so as to avoid the problem of collapse of the sidewall 650.

It should be noted that, the filling layer 700 is further removed subsequently, so that the material of the filling layer 700 is a material that is easy to be removed, and the process of removing the filling layer 700 has a small influence on the substrate, the gate layer 630, the isolation structure 601, the source region 661, and the drain region 662, thereby avoiding an adverse effect on the performance of the semiconductor structure.

In this embodiment, the material of the filling layer 700 is a Bottom Anti-Reflective Coating (BARC) material. The BARC material has a good filling performance, which is beneficial to ensuring the protection effect of the filling layer 700 on the substrate, the gate layer 630, the isolation structure 601, the source region 661 and the drain region 662, and is an organic material, thereby reducing the process difficulty and the process risk of subsequently removing the filling layer 700.

In other embodiments, the material of the filling Layer may also be a Dielectric Anti-Reflective Coating (DARC) material, Deep ultraviolet Light absorbing oxide (DUO) material, Organic Dielectric Layer (ODL) material, Advanced Patterning Film (APF) material, amorphous carbon or amorphous silicon. Wherein the DUO material is a siloxane polymer material comprising CH3-SiOx, Si-OH, SiOH3, or the like.

Specifically, the step of forming the filling layer 700 includes: forming a filling material layer by adopting a spin coating process, wherein the filling material layer covers the top of the gate mask layer 640; the filling material layer is planarized to make the top surface of the filling material layer have a flat surface, and the rest of the filling material layer after the planarization process is used as the filling layer 700.

By providing a flat surface on the top surface of the filling layer 700, unwanted reflection or scattering can be reduced during the subsequent exposure process for forming the photoresist layer, so that the formed photoresist layer has high position accuracy and topography accuracy.

in this embodiment, in order to reduce the difficulty of the subsequent etching process and simplify the process steps, the top of the filling layer 700 is flush with the top of the gate mask layer 640. In other embodiments, the filling layer may also cover the top of the gate mask layer.

Referring to fig. 14, a photoresist layer 710 having a pattern opening (not labeled) is formed on the filling layer 700; and sequentially etching the gate mask layer 640, the gate layer 630, the gate oxide layer 620 and a substrate (not labeled) with a partial thickness corresponding to the drift region 612 in the second region ii, which are located in a partial region on one side of the drain region 662, by using the photoresist layer 710 as a mask, and forming an isolation groove 670 in the remaining drift region 612.

In this embodiment, the substrate 600 is formed with the filling layer 700, and correspondingly, the isolation groove 670 extends to the top of the filling layer 700 along the normal direction of the surface of the substrate 600. That is, the isolation trench 670 is surrounded by the filling layer 700 located in the second region ii, the remaining gate layer 630 located at the boundary between the first region i and the second region ii, the remaining gate oxide layer 620, and the substrate corresponding to the remaining drift region 612.

In this embodiment, for the subsequent processes, after the isolation trench 670 is formed, the photoresist layer 710 is removed.

For a detailed description of the process steps for forming the isolation trench 670 by etching, please refer to the corresponding description in the foregoing embodiments, which is not repeated in this embodiment.

It should be noted that, after the isolation groove 670 is formed, the filling layer 700 is remained, and the filling layer 700 is used to provide a process platform in the subsequent process of forming the isolation layer 690, so as to improve the process operability.

Referring to fig. 15, a protective layer 680 is formed on the bottom and sidewalls of the isolation trench 670 (shown in fig. 14); an isolation layer 690 is formed in the isolation groove 670 in which the protective layer 680 is formed.

Specifically, the step of forming the protective layer 680 and the isolation layer 690 includes: forming a protective film on the bottom and the side wall of the isolation groove 670, wherein the protective film covers the top of the gate mask layer 640 and the top of the filling layer 700; filling an isolation material layer in the isolation groove 670 with the protection film, wherein the isolation material layer covers the top of the protection film; and removing the isolation material layer and the protective film which are higher than the top of the gate mask layer 640 by adopting a planarization process, reserving the residual protective films on the bottom and the side wall of the isolation groove 670 as the protective layer 680, and reserving the residual isolation material layer in the isolation groove 670 as the isolation layer 690.

For a detailed description of the process steps for forming the protective layer 680 and the isolation layer 690, please refer to the corresponding description in the previous embodiments, which is not repeated in this embodiment.

In this embodiment, after the protective layer 680 and the isolation layer 690 are formed, the remaining gate mask layer 640 is remained, the remaining gate mask layer 640 is used for protecting the top of the remaining gate layer 630 in a subsequent process, and the top of the remaining gate mask layer 640 is also used for defining a stop position in a subsequent planarization process.

Referring to fig. 16, after the protective layer 680 and the isolation layer 690 are formed, the filling layer 700 is removed (as shown in fig. 15).

By removing the filling layer 700, a space position is provided for the formation of a subsequent interlayer dielectric layer.

In this embodiment, the material of the filling layer 700 is a bottom anti-reflective coating material, and accordingly, an ashing process may be used to remove the filling layer 700.

Referring to fig. 17, after removing the filling layer 700 (as shown in fig. 15), an interlayer dielectric layer 602 is formed on the substrate 600 where the remaining gate layer 630 is exposed, and the interlayer dielectric layer 602 covers the sidewalls of the gate layer 630.

Specifically, the step of forming the interlayer dielectric layer 602 includes: forming a dielectric material layer on the substrate 600 exposed by the gate layer 630, wherein the dielectric material layer covers the top of the remaining gate mask layer 640 (shown in fig. 16); and performing planarization treatment on the dielectric material layer, and removing the dielectric material layer higher than the top of the gate layer 630, wherein the residual dielectric material layer after the planarization treatment is used as the interlayer dielectric layer 602.

In the planarization process, the top of the gate mask layer 640 is used as a stop position, so that the probability of damaging the top of the gate layer 630 can be reduced. Accordingly, after the isolation layer 690 is formed, the gate mask layer 640 is removed.

For a detailed description of the process steps for forming the interlayer dielectric layer 602 and the subsequent processes, please refer to the corresponding description in the foregoing embodiments, which is not repeated in this embodiment.

It should be noted that, for the specific description of the forming method in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details in this embodiment are not repeated.

Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 18, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.

The semiconductor structure includes: a base (not shown), where the base includes a substrate 400 and a fin portion (not shown) located on the substrate 400, the base includes a first region i and a second region ii that are adjacent to each other, the fin portion crosses the first region i and the second region ii along an extending direction (as shown in a direction DD1 in fig. 18), a well region 411 is formed in the base of the first region i, a drift region 412 is formed in the base of the second region ii, doped ions are provided in the well region 411 and the drift region 412, and a type of the doped ions in the drift region 412 is different from a type of the doped ions in the well region 411; the gate oxide layer 420 is positioned on the top surface and the side wall surface of the fin part; the gate layer 500 is positioned on the gate oxide layer 420 at the junction of the first area I and the second area II, and the gate layer 500 spans the fin part and covers the gate oxide layer 420 on the partial top and partial side wall of the fin part; a source region 461 located in the first region fin portion on one side of the gate layer 500, wherein the source region 461 is located in the well region 411, doped ions are located in the source region 461, and the doped ions in the source region 461 are of the same type as the doped ions in the drift region 412; a drain region 462 located in the second iifin portion on the other side of the gate layer 500, wherein the drain region 462 is located in the drift region 412, the drain region 462 has doped ions, and the doped ions in the drain region 462 are of the same type as the doped ions in the drift region 412; an isolation layer 490, penetrating through the second region iigate oxide layer 420 and a portion of the thickness substrate between the gate layer 500 and the drain region 462, wherein the isolation layer 490 is located in the drift region 412.

The substrate 400 is used to provide a process platform for the formation of the semiconductor structure. Specifically, the semiconductor structure is an LDMOS.

In this embodiment, the substrate 400 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

In this embodiment, the fin portion located in the first region i is used to provide a channel of the semiconductor structure, and the fin portion located in the second region ii is used to extend a distance between the source region 461 and the drain region 462, so that when the channel of the semiconductor structure is turned on, a length of a flow path of a current is increased, thereby improving a voltage withstanding performance of the LDMOS.

In this embodiment, the material of the fin portion is the same as that of the substrate 400, and the material of the fin portion is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.

It should be noted that, in this embodiment, in order to simplify the process steps for forming the fin portion and the substrate 400, the substrate 400 and the fin portion are formed in the same process step, and thus the fin portion and the substrate 400 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

It should be further noted that the semiconductor structure includes: and the isolation structure 401 is located on the substrate 400 with the exposed fin portion, the isolation structure 401 covers part of the side wall of the fin portion, and the top of the isolation structure 401 is lower than the top of the fin portion.

In this embodiment, the fin portion crosses over the first region i and the second region ii along the extending direction, so along the extending direction of the fin portion, the isolation structure 401 is located on the first region i substrate 400 on one side of the fin portion and on the second region ii substrate 400 on the other side of the fin portion.

in this embodiment, the isolation structure 401 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

The well region 411 is in contact with the drift region 412, the well region 411 and the drift region 412 are located in the substrate and are sequentially arranged along the extending direction of the fin portion, the well region 411 is used as a lateral diffusion region to form a channel with a concentration gradient, and the drift region 412 is used for bearing larger partial pressure.

In this embodiment, the well region 411 is located in the fin portion of the first region i and the portion of the thickness substrate 400 below the fin portion, and the drift region 412 is located in the fin portion of the second region ii and the portion of the thickness substrate 400 below the fin portion. In other embodiments, the well region and the drift region may be located only within the fin portion.

The well region 411 and the drift region 412 have doped ions therein, and the type of the doped ions in the drift region 412 is different from the type of the doped ions in the well region 411. In this embodiment, the LDMOS is an N-type semiconductor structure, and the doped ions In the well region 411 are P-type ions, which include B ions, Ga ions, or In ions; the doped ions in the drift region 412 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions.

The gate oxide layer 420 covers the top surface and the side wall surface of the exposed fin portion of the isolation structure 401, and the gate oxide layer 420 is used for realizing insulation between the gate layer 500 and a channel. In this embodiment, the gate oxide layer 420 is made of silicon oxide. In other embodiments, the material of the gate oxide layer can also be silicon oxynitride.

In this embodiment, the material of the gate layer 500 is a metal material, that is, the gate layer 500 is a gate electrode layer.

In this embodiment, the material of the gate layer 500 is W. In other embodiments, the material of the gate layer may also be a conductive material such as Al, Cu, Ag, Au, Pt, Ni, or Ti. In other embodiments, the gate layer may also be a polysilicon gate, that is, the material of the gate layer may also be polysilicon.

The source region 461 penetrates through the gate oxide layer 420 and is located in the well region 411 on one side of the gate layer 500, the drain region 462 penetrates through the gate oxide layer 420 and is located in the drift region 412 on the other side of the gate layer 500, when static electricity is discharged, large voltage generated by static electricity is applied to the drain region 462, so that a PN junction formed by the drift region 412 and the well region 411 is broken down, an NPN bipolar junction transistor formed by the drift region 412, the well region 411 and the source region 461 is correspondingly conducted, that is, a channel in a fin portion below the gate layer 500 is conducted, and a path is generated from the drain region 462 to the source region 461 for releasing static electricity, so that a protection circuit is achieved.

In this embodiment, the LDMOS is an N-type semiconductor structure, and the doped ions in the drift region 412 are N-type ions, so the doped ions in the source region 461 and the drain region 462 are N-type ions, and the N-type ions include P ions, As ions, or Sb ions.

Specifically, the source region 461 includes a first stress layer doped with the N-type ions, the drain region 462 includes a second stress layer doped with the N-type ions, and the first stress layer and the second stress layer are made of Si or SiC materials.

the isolation layer 490 penetrates through the second region ii gate oxide layer 420 between the gate layer 500 and the drain region 462 and a portion of the thickness substrate, the isolation layer 490 is located in the drift region 412, and the isolation layer 490 is used for isolating the drain region 462 from a channel below the gate layer 500, so as to prevent current from flowing into the channel directly along the extending direction of the fin portion after flowing out of the drain region 462.

For this purpose, the material of the isolation layer 490 is an insulating material. In this embodiment, the material of the isolation layer 490 is silicon oxide. The silicon oxide is an insulating material commonly used in a semiconductor process, has high process compatibility, has low cost, and is beneficial to reducing the process cost for forming the semiconductor structure. In other embodiments, the material of the isolation layer may also be silicon oxynitride, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon boron oxycarbonitride, or silicon carbonitride.

Specifically, when the device operates, after the current flows out from the drain region 462, the current bypasses the isolation layer 490 to the fin portion at the bottom of the gate layer 500 and flows to the source region 461 through the fin portion at the bottom of the gate layer 500 (i.e. the channel under the gate layer 500), that is, the current flow path includes the sidewall and the bottom of the isolation layer 490 in the drift region 412 (the flow path is shown by the dashed arrow in fig. 18), so that the length of the current flow path is extended by the isolation layer 490, thereby reducing the voltage gradient on the current path, and facilitating to improve the voltage withstanding performance of the LDMOS.

Moreover, the gate oxide layer 420 is not formed between the drift region 412 below the gate layer 500 and the sidewall of the isolation layer 490 (as shown by the dashed line frame C in fig. 18), which can also avoid the problem of breakdown of the gate oxide layer 420 on the current flow path, and is beneficial to further improving the voltage endurance of the LDMOS.

When the device works, the current flow path includes the sidewall and the bottom of the isolation layer 490 in the drift region 412, so that the distance (not labeled) from the bottom of the isolation layer 490 to the top of the fin portion is increased, which is beneficial to extending the length of the current flow path, and if the distance is too small, the effect of extending the length of the current flow path is relatively poor when the device works, thereby resulting in poor effect of improving the voltage resistance of the LDMOS; however, if the distance is too large, the thickness (not shown) of the substrate material corresponding to the remaining drift region 412 at the bottom of the isolation layer 490 is too small, which is likely to cause adverse effects on the current flow, and the too large distance also increases the process difficulty of the isolation layer 490 during the formation process, which is likely to cause the formation quality of the isolation layer 490 to be degraded. To this end, in this embodiment, the distance from the bottom of the isolation layer 490 to the top of the fin portion isToThe top of the fin portion is the top of the well 411 and the drift 412.

Similarly, along the extending direction of the fin portion, the width of the isolation layer 490 is increased, which is also beneficial to extending the length of the current flowing path, and if the width of the isolation layer 490 is too small, the effect of extending the length of the current flowing path is relatively poor, thereby resulting in poor effect of improving the voltage resistance of the LDMOS; however, if the width of the isolation layer 490 is too large, the width of the base material corresponding to the drift region 412 below the remaining gate layer 500 along the extending direction of the fin is too small, which is likely to cause adverse effect on the current flow, and too small a width of the isolation layer 490 may increase the process difficulty of the isolation layer 490 during the formation process, resulting in a reduction in the formation quality of the isolation layer 490. For this reason, in the present embodiment, the width of the isolation layer 490 is 20nm to 200nm along the extending direction of the fin portion.

In this embodiment, the distance from the bottom of the isolation layer 490 to the top of the fin portion and the width of the isolation layer 490 are set reasonably, and the distance and the width are matched, so that the length of the current flowing path is effectively prolonged, and the influence on the normal use function of the LDMOS is reduced.

In this embodiment, the semiconductor structure further includes: a protection layer 480 located between the isolation layer 490 and the drift region 412. The protection layer 480 is used to prevent the process of forming the isolation layer 490 from consuming the substrate material corresponding to the drift region 412, thereby preventing the formation of the isolation layer 490 from adversely affecting the performance of the semiconductor structure.

In order to reduce the influence on the performance of the semiconductor structure, the material of the protection layer 480 is also an insulating material. In this embodiment, the material of the protection layer 480 is silicon nitride. The density of the silicon nitride material is higher, so that the probability of the loss of the substrate can be effectively reduced by selecting the silicon nitride material. In other embodiments, the material of the protective layer may also be silicon oxide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon boron carbonitride, silicon oxycarbide, silicon rich oxide, or amorphous silicon.

It should be noted that the thickness (not labeled) of the protective layer 480 is not too small or too large. If the thickness of the protection layer 480 is too small, the protection effect of the protection layer 480 on the substrate is correspondingly reduced; if the thickness of the protection layer 480 is too large, the process cost and time are wasted, and the formation space of the isolation layer 490 is reduced, which may adversely affect the formation quality of the isolation layer 490. For this purpose, in this embodiment, the thickness of the protection layer 480 isTo

In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 402 on the substrate 400 exposed by the gate layer 500, wherein the interlayer dielectric layer 402 covers a sidewall of the gate layer 500.

The interlayer dielectric layer 402 is used to electrically isolate adjacent semiconductor structures, and the interlayer dielectric layer 402 is also used to define the size and position of the gate layer 500. Specifically, the top of the interlayer dielectric layer 402 is flush with the top of the gate layer 500.

The interlayer dielectric layer 402 is made of an insulating material. In this embodiment, the interlayer dielectric layer 402 is made of silicon oxide. In other embodiments, the interlayer dielectric layer may also be made of other dielectric materials such as silicon nitride or silicon oxynitride.

Accordingly, the isolation layer 490 also extends to the top of the interlayer dielectric layer 402 along a direction perpendicular to the normal of the surface of the substrate 400.

In this embodiment, in order to reduce the difficulty of the process for forming the semiconductor structure, the protection layer 480 also extends to the top of the interlayer dielectric layer 402.

It should be noted that the semiconductor structure further includes: and the side wall 450 is positioned on the side wall of the gate layer 500 close to the source region 461, and is also positioned between the protective layer 480 and the interlayer dielectric layer 402 and the drain region 462 of the second region ii.

In the process of forming the semiconductor structure, the sidewall spacers 450 are used to define the formation regions of the source region 461 and the drain region 462. The sidewall 450 may be made of one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride, and the sidewall 450 may have a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 450 has a single-layer structure, and the material of the sidewall spacer 450 is silicon nitride.

The semiconductor structure may be formed by the formation method described in the first embodiment, the formation method described in the second embodiment, or other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.