阅读说明：本技术 一种三种高低电平接电情况下的逻辑电路 (Logic circuit under three high-low level power connection conditions ) 是由 唐大为 于 2018-06-08 设计创作，主要内容包括：本发明公开一种三类高低电平接电情况下的逻辑电路,是当两个接电端在接入高低电平时,分别三种不同接电情况下产生的两个送电端送出不同高低电平的逻辑电路,如图1中,通过对Lin、Rin接入不同高低电平的三种情况,则Lout、Rout表现出三种高低电平的输出情况,可用于计算机基础加法计算领域,和一些需要不同接电条件进行不同通路的电路领域。(The invention discloses a logic circuit under three types of high and low level power connection conditions, which is a logic circuit that two power transmission ends generated under three different power connection conditions send out different high and low levels when two power connection ends are connected with the high and low levels, as shown in fig. 1, Lin and Rin are connected with the three conditions of different high and low levels, then Lout and Rout show the output conditions of the three high and low levels, and the logic circuit can be used in the field of basic addition calculation of computers and the field of circuits which need different power connection conditions to carry out different paths.)

1. When two electric connection ends are connected with different or same high and low levels, two power transmission ends generate different high and low levels.

2. The method of claim 1, further comprising: 4 AND gates, 2 OR gates, 1 NOT gate, two electric connection ends and two electric transmission ends.

3. The method of claim 1, further comprising: when the two power receiving ends are both at low level, the two power transmitting ends are also at low level; when one of the two electric connection ends is at a high level, one of the two power transmission ends is at a high level; when both the electric terminals are at high level, one of the power transmitting terminals is at high level and is just opposite to the output result of only one electric terminal at high level.

4. The method of claim 1, further comprising: and taking the result of the right end of the power transmission end as a binary bit of the addition calculation result, judging the result of the left end of the power transmission end and the result of the right end of the power transmission end with a next bit by a logic circuit, taking the result of the right end of the power transmission end as a next bit binary result, and so on.

Technical Field

The invention discloses a logic circuit under three high and low level power connection conditions, which is a circuit that two power transmission ends generated under three different power connection conditions send different high and low levels when two power connection ends are connected with the high and low levels, and can be used in the field of basic addition calculation of computers and the field of circuits which need different power connection conditions to carry out different paths.

Background

Some computer basic logic gate combination application uses three kinds of logic circuits of AND gate, OR gate and NOT gate to make computer binary data addition calculation.

Disclosure of Invention

The invention aims to provide a Logic circuit for Bit-wise addition of binary data of a computer, which is mainly used for carrying out binary Carry of electronic signals, so that the Logic circuit is simply called a Carry Gate in the following description, and is called a Logic Carry Bit Gate in English and is simply called LCBG.

The invention is characterized in that: the combination of 7 computer logic gate circuits is used to complete the carry operation of one computer.

The invention has the advantages that: as shown in fig. 2, if there are 4 bits in the computer data for addition, 4 LCBGs are needed in the first row, and one LCBG is decreased for each row, so that 4-bit data addition can be completed. If the data is operated by N bits, N LCBG are needed in the first row, and one LCBG is reduced for each row to complete the addition operation.

If the addition is calculated by N bits, (1+ N) N/2 LCBG are needed to enter the operation.

Drawings

As shown in FIG. 1, Lin is a left side connection terminal, Rin is a right side connection terminal, Lout is a left side power transmission terminal, Rout is a right side power transmission terminal, 1, 7 are OR gates, 2, 3, 5, 6 are AND gates, and 4 is a NOT gate.

As shown in fig. 2, two sets of 4-bit binary computer data are respectively arranged on the left side and the right side of the top part in the figure, 10 LCBGs are arranged in the middle part in the figure, and a 4-bit binary computer data result obtained by adding the two 4-bit binary computer data on the upper part is output on the lower part in the figure.

Detailed Description

As shown in figure 1 of the drawings, in which,

When Lin and Rin are both high level, 1, 2 and 3 all output high level, then Lout is high level, 1 in the computer binary data, and 4 NOT gate output is low level, then 5, 6 and 7 output low level, Rout is low level, 0 in the computer binary data;

When only one of Lin or Rin is high level and the other is low level, 1 outputs high level, 2 and 3 outputs low level, Lout is low level and is 0 in the binary data of the computer, 4 NOT gate outputs high level, 5 and 6 outputs high level, 7 outputs high level, Rout is high level and is 1 in the binary data of the computer;

when Lin and Rin are both low, Lout and Rout are both low, and both of the binary data of the computer are 0.

as shown in figure 2 of the drawings, in which,

The application structure diagram of LCBG in binary bit-by-bit addition operation of computer.

Explaining the rightmost bit of the two 4-bit data at the upper part of the figure, when the two 4-bit data are accessed to Lin and Rin ends of the rightmost LCBG in the first row of the LCBG array, if signals of the two are both 1, the Lout is 1, the Rout is 0, the rightmost bit of the binary data which obtains the addition calculation result output by the bottommost part in the figure is 0, the 1 of the Lout data and the Rout output result of the second LCBG at the right of the first row of the LCBG array are judged in the first LCBG at the right of the second row, the new Rout is shown as 1 or 0 at the rightmost second bit of the right part in the figure, and so on, through the operation of the 4 rows of LCBG, a new group of 4-bit binary electronic data is obtained finally, namely, the result of adding the two groups of 4-bit binary electronic data at the top is obtained.

For example, N bits of data are added, for example, 8 bits, 16, 32, 64 bits, and so on.