阅读说明：本技术 一种高k金属栅极结构及其制作方法 (A kind of high-K metal gate structure and preparation method thereof ) 是由 雷海波 田明 宋洋 廖端泉 于 2019-08-29 设计创作，主要内容包括：本发明提供一种高K金属栅极结构及其制作方法,在TiN和TiAl之间,新增一层TaN阻挡层,使TiN内外均由TaN阻挡层保护,内部沉积填充金属层无法扩散进入PMOS功函数金属TiN层,提高PMOS器件的稳定性。在新增TaN阻挡层沉积完成后,通过光刻和蚀刻的工艺,使NMOS结构暴露出来,PMOS结构整体为牺牲层保护,之后对于新增TaN层做氟化处理,置换TaN层中的N元素,使此TaN层完全形成TaFx化合物,水洗移除,从而在不影响其他层的情况下,完全移除新增TaN层,进而实现上述改进的PMOS栅极结构,并且不影响NMOS结构。(The present invention provides a kind of high-K metal gate structure and preparation method thereof; between TiN and TiAl, one layer of TaN barrier layer is increased newly, make TiN is inside and outside to be protected by TaN barrier layer; inside deposition filling metal layer can not diffuse into PMOS workfunction metal TiN layer, improve the stability of PMOS device.After the completion of newly-increased TaN barrier layer deposition; by the technique of photoetching and etching, NMOS structure is exposed, PMOS structure generally sacrificial layer is protected; fluorination treatment is done for newly-increased TaN layers later; N element in TaN layers of displacement makes this TaN layers to form TaFx compound completely, and washing removes; to in the case where not influencing other layers; it removes completely TaN layers newly-increased, and then realizes above-mentioned improved PMOS gate structure, and do not influence NMOS structure.)

1. a kind of high-K metal gate structure, which is characterized in that include at least:

Groove and the outer barrier being deposited in the groove；The metal work function layer being deposited in the outer barrier；Deposition Internal barriers on the metal work function layer；The metal compound layer being deposited in the internal barriers；It is deposited on Adhesive layer on the metal compound layer is filled in the groove, the metal of the bonding layer surface.

2. high-K metal gate structure according to claim 1, it is characterised in that: the high-K metal gate structure is PMOS High-K metal gate.

3. high-K metal gate structure according to claim 3, it is characterised in that: the outer barrier is the first TaN Layer.

4. high-K metal gate structure according to claim 4, it is characterised in that: the metal work function layer is TiN layer.

5. high-K metal gate structure according to claim 5, it is characterised in that: the internal barriers are the 2nd TaN Layer.

6. high-K metal gate structure according to claim 6, it is characterised in that: the metal compound layer is TiAl layers.

7. high-K metal gate structure according to claim 2, it is characterised in that: the metal compound layer be with it is described The metal work function layer of NMOS in the same processing procedure of PMOS.

8. high-K metal gate structure according to claim 1, it is characterised in that: the adhesive layer is to be made of TiN and Ti Lamination.

9. high-K metal gate structure according to claim 1, it is characterised in that: the metal is aluminium.

10. high-K metal gate structure according to claim 6, it is characterised in that: the high-K metal gate structure is also wrapped Include the lamination between the outer barrier and silicon substrate of the groove type；The lamination is followed successively by inter-level dielectric from bottom to top Layer, HfO2 layers, TiN layer.

11. high-K metal gate structure according to claim 10, it is characterised in that: inter-level dielectric described in the lamination Layer with a thickness of 8~10 angstroms；Described HfO2 layers with a thickness of 20 angstroms；The TiN layer with a thickness of 20 angstroms.

12. according to claim 1 to the production method of high-K metal gate structure described in 11 any one, it is characterised in that: should Method the following steps are included:

Step 1: providing the groove for being respectively used to production PMOS, NMOS high-K metal gate structure, the groove is located at same half On conductor structure；

Step 2: deposition the first TaN layers on the semiconductor structure, deposits the described first TaN layers of shape in the groove At the outer barrier of groove type；

Step 3: depositing one layer of TiN layer on the first TaN layer, it is deposited on described for making PMOS high-K metal gate knot The TiN layer in the groove of structure forms metal work function layer；

Step 4: TaN layers of the deposition the 2nd in the TiN layer, is deposited on described for making PMOS high-K metal gate structure The 2nd TaN layers of formation internal barriers in groove；

Step 5: using lithography and etching technique by the groove upper surface region for being used to make NMOS high-K metal gate structure Domain is exposed；

Step 6: to the 2nd TaN layers of progress fluorination treatment in the groove for making NMOS high-K metal gate structure, Form it into TaFx compound；

Step 7: washing removes the TaFx compound；

Step 8: wet etching removal is described for making the TiN layer in the groove of NMOS high-K metal gate structure；

Step 9: successively on the semiconductor structure depositing metallic compounds layer in surface and the groove, depend on the gold Belong to the adhesive layer and metal on compound layer；

Step 10: planarization grinding is carried out to the semiconductor structure upper surface, until the interlayer dielectric layer between exposing groove is Only.

13. the production method of high-K metal gate structure according to claim 12, it is characterised in that: the semiconductor junction Structure includes at least: silicon substrate and the area PWell, the area NWell on the silicon substrate；Between the area PWell and the area NWell by STI isolation；The NMOS high-K metal gate structure is located above the area PWell；The PMOS high-K metal gate structure bit Above the area NWell；The area PWell, the area NWell two sides respectively form active, drain region.

14. the production method of high-K metal gate structure according to claim 13, it is characterised in that: described in step 6 Gas used in the process of fluorination treatment combines generation by the plasma gas containing CxFy, NF3, BF3, SiF4, Ar, H2, N2.

15. the production method of high-K metal gate structure according to claim 12, it is characterised in that: used in step 8 Hot SC1 cleaning solution carries out the wet etching.

16. the production method of high-K metal gate structure according to claim 15, it is characterised in that: the hot SC1 cleaning It include deionized water, hydrogen peroxide, NH in liquid₄OH。

17. the production method of high-K metal gate structure according to claim 16, it is characterised in that: the hot SC1 cleaning Deionized water, hydrogen peroxide, NH in liquid₄The proportion of OH are as follows: 5:1.1:1.

18. the production method of high-K metal gate structure according to claim 17, it is characterised in that: used in step 8 The temperature that hot SC1 cleaning solution carries out the wet etching is 60 degrees Celsius.

19. the production method of high-K metal gate structure according to claim 12, it is characterised in that: the gold in step 9 Belonging to compound layer is TiAl layers.

Technical field

The present invention relates to field of semiconductor fabrication, more particularly to a kind of high-K metal gate structure and preparation method thereof.

Background technique

Continuous with transistor size reduces and the continuous improvement of device performance requirements, HKMG (high dielectric constant/ Metal gates) technology almost has become the indispensable technology of 28nm high performance device.In order to reduce electric leakage of the grid, grid electricity is reduced Hold, promotes transistor performance in 28nm technology node and generally use HKMG framework and technical solution.

High dielectric constant material replaces traditional silicon dioxide, possesses high dielectric constant, while possessing silica Superior function, good insulation, high temperature resistant etc..High dielectric constant material and polysilicon poor compatibility, the two boundary defect cause Fermi level pinning effect cause threshold voltage to increase, the surphon scattering effect meeting of high-k (High-K) material itself Carrier mobility is caused to reduce.Introduce metal can solve the above problem instead of polysilicon gate.

In metal gates (metal gate) technique, the work function for optimizing metal electrode is the important of adjusting means performance Means.In post tensioned unbonded prestressed concrete (Gate-last) technology, bimetallic electrode technology is used, PMOS and NMOS is deposited respectively different The metallic diaphragm of metal work function, to obtain optimal work function control.The workfunction metal of PMOS tube uses TiN, work function Close to valence band, the workfunction metal of NMOS tube uses TiAl, and work function is close to conduction band.It is external necessary to protect workfunction metal Additional coverage barrier layer, such as TiN, TaN, Ta.

As shown in Figures 1 to 6, foundries (Foundry) mainstream technology is first to deposit p-type workfunction metal TaN/ at present TiN, photoetching exposes NMOS area, and wet etching falls p-type metal, is parked on TaN to high selectivity ratio, then deposited n-type work content Number metal TiAl, finally fills metal Al or W.Metal used herein above is industry materials known, can only be by depositing work Skill adjusts metal work function, to reach the different work functions requirement of valence band and conduction band, wherein PMOS workfunction metal film layer is TiN/TaN/TiN, and NMOS workfunction metal is the TiAlN that TiAl and TiN are mutually diffuseed to form.

Current existing HKMG production process are as follows: silicon substrate is provided, shallow trench, polysilicon gate, source-drain area are successively carried out The techniques such as molding carry out pseudo- grid removal after interlayer dielectric layer (ILD0) carries out chemical mechanical grinding (CMP)；Deposit PMOS Metal work function TiN；Pass sequentially through the TiN of the techniques such as Lithography Etching removal NMOS area deposition；It is heavy in NMOS and PMOS area Product NMOS metal work function TiN/Ti, and the filling of Al is carried out, finally carry out metal gates (Metal gate) CMP process.

In HKMG organization plan, in PMOS gate structure workfunction metal be TiN, outside have one layer of TaN barrier layer, Inside is deposition filling TiAl layers and metal layer, and the TiAl layers is easy to diffuse to workfunction layers TiN, and then influences The stability of PMOS.

It is, therefore, desirable to provide a kind of new high-K metal gate structure and preparation method thereof solves the above problems.

Summary of the invention

In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of high-K metal gate structure and Its production method, workfunction metal is TiN in PMOS gate structure for solving in the prior art, outside have one layer of TaN resistance Barrier, inside is deposition filling TiAl layers and metal layer, and the TiAl layers is easy to diffuse to workfunction layers TiN, in turn The problem of influencing the stability of PMOS.

In order to achieve the above objects and other related objects, the present invention provides a kind of high-K metal gate structure, includes at least: Groove and the outer barrier being deposited in the groove；The metal work function layer being deposited in the outer barrier；It is deposited on institute State the internal barriers on metal work function layer；The metal compound layer being deposited in the internal barriers；It is deposited on described Adhesive layer on metal compound layer is filled in the groove, the metal of the bonding layer surface.

Preferably, the high-K metal gate structure is the high-K metal gate of PMOS.

Preferably, the outer barrier is the first TaN layers.

Preferably, the metal work function layer is TiN layer.

Preferably, the internal barriers are the 2nd TaN layers.

Preferably, the metal compound layer is TiAl layers.

Preferably, the metal compound layer is the metal work function layer with the NMOS in the same processing procedure of the PMOS.

Preferably, the adhesive layer is the lamination being made of TiN and Ti.

Preferably, the metal is aluminium.

Preferably, the high-K metal gate structure further include positioned at the groove type outer barrier and silicon substrate it Between lamination；The lamination is followed successively by interlayer dielectric layer, HfO2 layers, TiN layer from bottom to top.

Preferably, interlayer dielectric layer described in the lamination with a thickness of 8~10 angstroms；Described HfO2 layers with a thickness of 20 Angstrom；The TiN layer with a thickness of 20 angstroms.

The present invention also provides the production methods of the high-K metal gate structure, method includes the following steps: Step 1: mentioning For being respectively used to the groove of production PMOS, NMOS high-K metal gate structure, the groove is located at on semiconductor structure；Step Rapid two, deposition the first TaN layers on the semiconductor structure, deposits the described first TaN layers of formation groove in the groove The outer barrier of type；Step 3: depositing one layer of TiN layer on the first TaN layer, it is deposited on described for making PMOS high The TiN layer in the groove of karat gold category gate structure forms metal work function layer；Step 4: depositing second in the TiN layer It TaN layers, is deposited on described for making blocking inside the 2nd TaN layers of formation in the groove of PMOS high-K metal gate structure Layer；Step 5: using lithography and etching technique by the groove surface area for being used to make NMOS high-K metal gate structure It is exposed；Step 6: to it is described for make in the groove of NMOS high-K metal gate structure the 2nd TaN layers be fluorinated Processing, forms it into TaFx compound；Step 7: washing removes the TaFx compound；Step 8: described in wet etching removal The TiN layer in groove for making NMOS high-K metal gate structure；Step 9: successively surface on the semiconductor structure And depositing metallic compounds layer in the groove, depend on adhesive layer and metal on the metal compound layer；Step 10: right The semiconductor structure upper surface carries out planarization grinding, until exposing the interlayer dielectric layer between groove.

Preferably, the semiconductor structure includes at least: silicon substrate and the area PWell on the silicon substrate, NWell Area；It is isolated between the area PWell and the area NWell by STI；The NMOS high-K metal gate structure is located in the area PWell Side；The PMOS high-K metal gate structure is located above the area NWell；The area PWell, the area NWell two sides respectively formed Active, drain region.

Preferably, the gas used in the process of fluorination treatment described in step 6 by containing CxFy, NF3, BF3, SiF4, The plasma gas of Ar, H2, N2, which combine, to be generated.

Preferably, the wet etching is carried out using hot SC1 cleaning solution in step 8.

It preferably, include deionized water, hydrogen peroxide, NH in the hot SC1 cleaning solution₄OH。

Preferably, deionized water, hydrogen peroxide, NH in the hot SC1 cleaning solution₄The proportion of OH are as follows: 5:1.1:1.

Preferably, hot SC1 cleaning solution is used to carry out the temperature of the wet etching as 60 degrees Celsius in step 8.

Preferably, the metal compound layer in step 9 is TiAl layers.

As described above, high-K metal gate structure and preparation method thereof of the invention, has the advantages that the present invention Between TiN and TiAl, one layer of TaN barrier layer is increased newly, make TiN is inside and outside to be protected by TaN barrier layer, inside deposition filling metal Layer can not diffuse into PMOS workfunction metal TiN layer, improve the stability of PMOS device.PMOS deposition work function TiN it Afterwards, this newly-increased TaN barrier layer is deposited, simultaneously, NMOS can also deposit this layer of TaN to the deposition of TaN barrier layer, need inside PMOS The TaN of the side NMOS and TiN are removed together, and are not damaged to barrier layer TaN layers of outer layer.If using traditional pickling Minimizing technology, when removal is TaN layers newly-increased, since pickling is much larger than the etch-rate of TiN the etch-rate of TaN, Lower layer's TiN layer is easily got rid of together, and outer layer barrier TaN is exposed, and is damaged by acid.The present invention is above-mentioned for realizing PMOS gate structure avoids NMOS structural damage from doing and discloses together.After the completion of newly-increased TaN barrier layer deposition, pass through photoetching With the technique of etching, NMOS structure is exposed, PMOS structure generally sacrificial layer is protected, and uses plasma later (Plasma) equipment, does fluorination treatment for newly-increased TaN layers, and the N element in TaN layers of displacement makes this TaN layers to form TaFx completely Compound, and wash and remove, to be removed completely TaN layers newly-increased in the case where not influencing other layers.And then realize above-mentioned change Into PMOS gate structure, and do not influence NMOS structure.

Detailed description of the invention

Fig. 1 is shown as the present invention for making the semiconductor structure schematic diagram of PMOS high-K metal gate structure；

Fig. 2, which is shown, removes the structural schematic diagram that dummy grid forms groove 01 in semiconductor structure of the invention；

Fig. 3 is shown as depositing the structural representation after outer barrier and metal work function layer on semiconductor structure of the invention Figure；

Fig. 4 is shown as depositing the semiconductor structure schematic diagram after internal barriers in the present invention on metal work function layer；

Fig. 5 is shown as exposing the groove surface area for being used to make NMOS high-K metal gate structure in the present invention Semiconductor structure schematic diagram after coming；

Fig. 6 is shown as the 2nd TaN layers and metal work function in the groove that will be used to make NMOS high-K metal gate structure Structural schematic diagram after layer removal；

Fig. 7 is shown as in the present invention knot on semiconductor structure after depositing metallic compounds layer, adhesive layer and metal Structure schematic diagram；

Fig. 8 is shown as the structural schematic diagram after the grinding of the semicon-ductor structure surface in the present invention；

Fig. 9 is PMOS high-K metal gate structural schematic diagram in the prior art；

Figure 10 is PMOS high-K metal gate structural schematic diagram of the invention；

Figure 11 is shown as the production method flow chart of high-K metal gate structure of the invention.

Specific embodiment

Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.

Fig. 1 is please referred to Figure 11.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout kenel may also be increasingly complex.

The present invention provides a kind of high-K metal gate structure, as shown in figure 8, the high-K metal gate structure includes at least: recessed Slot and the outer barrier 02 being deposited in the groove；The metal work function layer 03 being deposited in the outer barrier 02；Deposition Internal barriers 04 on the metal work function layer 03；The metal compound layer being deposited in the internal barriers 04 06；The adhesive layer 07 being deposited on the metal compound layer 06 is filled in the groove, the metal of the bonding layer surface 08.As shown in figure 8, the high-K metal gate structure is the high-K metal gate of PMOS.In Fig. 8, the high-K metal gate of the PMOS The high-K metal gate structure of pole and the NMOS are formed on same silicon substrate.The high-K metal gate structure of the NMOS utilizes Groove on the left of Fig. 8 is formed.The groove in the present invention is to be formed after dummy grid removes polysilicon.

In the high-K metal gate structure of the PMOS, depositing the outer barrier 02 in the groove is the One TaN layers, i.e., the material of the described outer barrier is TaN, the described first TaN layers be inner sidewall and bottom shape in the groove At one layer of TaN, as barrier layer.Therefore the planform of the outer barrier 02 is also groove type.In the outer barrier It deposited one layer of metal work function layer 03 in layer, the metal work function layer 03 is preferably in the present invention TiN layer, that is, in institute The inner sidewall and bottom for stating the outer barrier 02 of groove type all deposited one layer of TiN, form the metal work function of the invention Several layers 03, the metal work function layer 03 is also groove type.

Such as Fig. 8, the internal barriers 04 being deposited on the metal work function layer 03, the internal barriers 04 are used as institute The 2nd TaN layers for stating PMOS high-K metal gate structure, that is, the internal barriers 04 are preferably TaN layers in the present invention.Institute State the 2nd TaN layers of inner sidewall for being deposited on the internal barriers 04 and bottom, thus the described 2nd TaN layers be also groove type. The PMOS high-K metal gate structure further includes the metal compound layer 06 being deposited in the internal barriers 04, the present invention Preferably, the metal compound layer is TiAl layers.That is, in the inner sidewall of the internal barriers 04 and one layer of bottom deposit TiAl, described TiAl layers is also groove type.As shown in figure 8, due to the NMOS high-K metal gate structure and the PMOS high K Metal gate structure is formed on same silicon substrate, and the two deposits the metal compound layer TiAl's in same processing procedure Effect is as the metal work function layer with the NMOS in the same processing procedure of the PMOS.

The PMOS high-K metal gate structure further includes the adhesive layer 07 being deposited on the metal compound layer, this hair It is bright further, the adhesive layer is the lamination being made of TiN and Ti.The PMOS high-K metal gate structure further includes filling In in the groove, it is described bonding layer surface metal, the metal is preferably aluminium.The effect of the adhesive layer is by the gold Belong to aluminium and described metallic compound TiAl layers are preferably bonded together.

As shown in Figure 10, Figure 10 is the enlarged diagram of PMOS high-K metal gate structure described in Fig. 8, and Fig. 9 is existing PMOS high-K metal gate structural schematic diagram in technology, the structure in Fig. 9 are compared with Figure 10, the high-K metal gate of the invention Structure increases by one layer of internal barriers 04 between the metal compound layer 06 and the metal work function layer 03, prevents metal Compound layer 06 (TiAl layers) is spread to metal work function layer 03 (TiN layer).Improve the stability of PMOS device.

As shown in Figure 10, further, the high-K metal gate structure of the invention further includes being located at the groove type Lamination between outer barrier and silicon substrate；The lamination is followed successively by interlayer dielectric layer, HfO from bottom to top₂Layer, TiN layer.More into One step, interlayer dielectric layer described in the lamination with a thickness of 8~10 angstroms；The HfO₂Layer with a thickness of 20 angstroms；The TiN Layer with a thickness of 20 angstroms.

The present invention also provides the production methods of the high-K metal gate structure, and as shown in figure 11, Figure 11 is shown as the present invention High-K metal gate structure production method flow chart, method includes the following steps:

Step 1: providing the groove for being respectively used to production PMOS, NMOS high-K metal gate structure, the groove is located at same On semiconductor structure；As shown in Figure 1, Fig. 1 is shown as the present invention for making the semiconductor junction of PMOS high-K metal gate structure Structure schematic diagram, dummy grid is removed not yet in the semiconductor structure in Fig. 1, therefore, for making described PMOS, NMOS The groove of high-K metal gate structure is formed not yet.Comprising silicon substrate and on the silicon substrate in the semiconductor structure The area PWell, the area NWell；It is isolated between the area PWell and the area NWell by STI；The NMOS high-K metal gate structure is located at Above the area PWell；The PMOS high-K metal gate structure is located above the area NWell；The area PWell, NWell The two sides in area respectively form active, drain region.

Show as shown in Fig. 2, the structure that removal dummy grid forms groove 01 in semiconductor structure of the invention is shown in Fig. 2 It is intended to；The groove on the semiconductor structure be it is multiple, can be used for making respectively PMOS high-K metal gate structure and NMOS metal gate structure.If the groove of right end in 2 is to be formed used in PMOS high-K metal gate structure, the groove of the left end Fig. 2 is It is formed used in NMOS high-K metal gate structure, the groove is to pass through interlayer dielectric layer (LD0) CMP (chemical mechanical grinding) Afterwards, it is formed after eliminating dummy grid.

Step 2: deposition the first TaN layers on the semiconductor structure, deposits the first TaN in the groove Layer forms the outer barrier of groove type；As shown in figure 3, Fig. 3 is shown as depositing outer barrier on semiconductor structure of the invention Structural schematic diagram after layer and metal work function layer, it is described while depositing described first TaN layers on the semiconductor structure Inside grooves have also been deposited one layer of TaN, TaN layers of formation the described first, the outside as the PMOS high-K metal gate structure Barrier layer 02.Described first TaN layers be not only deposited at it is described for making in the groove of PMOS high-K metal gate structure, simultaneously It also is deposited upon in the groove for making the NMOS high-K metal gate structure and the upper surface of the semiconductor structure.

Step 3: depositing one layer of TiN layer on the first TaN layer, it is deposited on described for making PMOS high-K metal gate The TiN layer in the groove of pole structure forms metal work function layer；As shown in figure 3, being deposited in the outer barrier 02 Metal work function layer 03 of the TiN layer as the PMOS high-K metal gate structure.The metal work function layer 03 (TiN layer) It is deposited on the first TaN layer in the groove for making PMOS, NMOS high-K metal gate structure and semiconductor structure simultaneously On first TaN layer of upper surface.

Step 4: TaN layers of the deposition the 2nd in the TiN layer, is deposited on described for making PMOS high-K metal gate knot The 2nd TaN layers of formation internal barriers in the groove of structure；As shown in figure 4, Fig. 4 is shown as in the present invention in metal work function The semiconductor structure schematic diagram after internal barriers is deposited on layer.The internal barriers 04 are deposited on for making simultaneously In the TiN layer in the groove of PMOS, NMOS high-K metal gate structure and in the TiN layer of the semiconductor structure upper surface.

Step 5: using lithography and etching technique by table on the groove for being used to make NMOS high-K metal gate structure Face region is exposed；As shown in figure 5, Fig. 5 is shown as to be used to make the groove of NMOS high-K metal gate structure in the present invention Surface area be exposed after semiconductor structure schematic diagram, and in the production PMOS high-K metal gate structure upper surface Region is also covered with photoresist 05.PMOS structural region generally sacrificial layer is protected.

Step 6: to it is described for make in the groove of NMOS high-K metal gate structure the 2nd TaN layers carry out at fluorination Reason, forms it into TaFx compound；Gas used in the process of fluorination treatment described in the step by containing CxFy, NF3, BF3, The plasma gas of SiF4, Ar, H2, N2, which combine, to be generated.Using plasma (Plasma) equipment, for the described 2nd TaN layers Fluorination treatment is done, the N element in TaN layers of displacement makes this TaN layers to form TaFx compound completely.

Step 7: washing removes the TaFx compound；The TaFx compound is easy to be washed with water process removal, thus In the case where not influencing other layers, the described 2nd TaN layers are removed completely.As shown in fig. 6, Fig. 6 is shown as to be used to make The 2nd TaN layers and metal work function layer in the groove of NMOS high-K metal gate structure remove after structural schematic diagram.Described The described first TaN layers (outer barrier 02) are left in groove for making NMOS high-K metal gate structure.Washing so that TaN removal in NMOS area is without damaging the TiN layer.If using traditional pickling minimizing technology, in TaN layers of removal the described 2nd When, since pickling is much larger than the etch-rate of TiN the etch-rate of TaN, lower layer's TiN layer is easily removed together Fall, outer barrier TaN is exposed, is damaged by acid.

Step 8: wet etching removal is described for making the TiN layer in the groove of NMOS high-K metal gate structure；Such as Shown in Fig. 6, Fig. 6 is shown as the 2nd TaN layers and metal work function in the groove that will be used to make NMOS high-K metal gate structure Structural schematic diagram after layer removal.The wet etching is carried out using hot SC1 cleaning solution in step 8.Further, the heat It include deionized water, hydrogen peroxide, NH in SC1 cleaning solution₄OH.Further, gone in heretofore described hot SC1 cleaning solution from Sub- water, hydrogen peroxide, NH₄The proportion of OH are as follows: 5:1.1:1.And deionized water, hydrogen peroxide, NH in the hot SC1 cleaning solution₄OH's Proportion are as follows: 5:1.1:1.

Step 9: successively on the semiconductor structure depositing metallic compounds layer in surface and the groove, depend on Adhesive layer and metal on the metal compound layer；As shown in fig. 7, Fig. 7 is shown as in the present invention sinking on semiconductor structure Structural schematic diagram after product metal compound layer, adhesive layer and metal.Wherein the metal compound layer 06 is TiAl layers, is glued The lamination that layer 07 is made of TiN and Ti is closed, the metal 08 deposited in the step is aluminium.

Step 10: planarization grinding is carried out to the semiconductor structure upper surface, until the inter-level dielectric between exposing groove Until layer.As shown in figure 8, Fig. 8 is shown as the structural schematic diagram after the grinding of the semicon-ductor structure surface in the present invention.Therefore, In The groove inner wall for making NMOS high-K metal gate structure is deposited with outer barrier 02, metal compound layer 06, glues Layer 07 and metal 08 are closed, and the groove inner wall in production PMOS high-K metal gate structure is deposited with outer barrier 02, metal Work-function layer 03, internal barriers 04, metal compound layer 06, adhesive layer 07 and metal 08.

In conclusion the present invention between TiN and TiAl, increases one layer of TaN barrier layer newly, make TiN is inside and outside to be stopped by TaN Layer protection, inside deposition filling metal layer can not diffuse into PMOS workfunction metal TiN layer, improve the stabilization of PMOS device Property.After PMOS deposits work function TiN, deposit this newly-increased TaN barrier layer, inside PMOS the deposition of TaN barrier layer simultaneously, NMOS can also deposit this layer of TaN, need together to remove the TaN of the side NMOS and TiN, and be not damaged to the blocking of outer layer TaN layers of layer.If the erosion using traditional pickling minimizing technology, when removal is TaN layers newly-increased, due to pickling for TiN Etching speed is much larger than the etch-rate of TaN, and lower layer's TiN layer is easily got rid of together, and outer layer barrier TaN is exposed, It is damaged by acid.The present invention avoids NMOS structural damage from doing and discloses together for above-mentioned PMOS gate structure is realized.Newly-increased After the completion of TaN barrier layer deposition, by the technique of photoetching and etching, NMOS structure is exposed, PMOS structure is generally sacrificial Domestic animal layer protection, uses plasma apparatus later, does fluorination treatment for newly-increased TaN layers, and the N element in TaN layers of displacement makes this TaN layers form TaFx compound, this compound completely, it is easy to process removal are washed with water, thus not influencing other layers In the case of, it removes completely TaN layers newly-increased, and then realizes above-mentioned improved PMOS gate structure, and do not influence NMOS structure.Institute With the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.

The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.