阅读说明：本技术 一种延时电路以及驱动装置 (Time delay circuit and driving device ) 是由 李进 于 2019-03-20 设计创作，主要内容包括：一种延时电路以及驱动装置,该延时电路可以包括至少两条支路,该至少两条支路并联,至少两条支路中的每条支路具有不同的延时；该延时电路包括至少一个寄存器,该寄存器用于控制至少两条支路中的一条支路接通,使得该延时电路产生于接通的支路对应的延时。由于输入信号的延时越大,摆率越小,因此输入信号通过该至少两条支路中任意一条支路的摆率不同。通过至少一个寄存器控制该至少两条支路中的一条支路接通可以调节输出信号的摆率,使得输出信号的摆率可以兼容不同协议或同一协议下的不同模式。(A time delay circuit and a driving device, the time delay circuit can include at least two branches, the at least two branches are connected in parallel, and each branch of the at least two branches has different time delay; the delay circuit comprises at least one register for controlling one of the at least two branches to be switched on, so that the delay circuit generates a delay corresponding to the switched-on branch. The larger the delay of the input signal is, the smaller the slew rate is, so that the slew rate of the input signal passing through any one of the at least two branches is different. The slew rate of the output signal can be adjusted by controlling the connection of one branch of the at least two branches through at least one register, so that the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.)

A delay circuit, comprising:

at least two branches connected in parallel, each of the at least two branches having a different delay;

the delay circuit comprises at least one register, and the at least one register is used for controlling one branch of the at least two branches to be switched on, so that the delay circuit generates delay corresponding to the switched-on branch.

The delay circuit of claim 1, wherein each of the at least two branches comprises a different number and/or size of MOS transistors, such that the at least two branches have different delays.

The delay circuit of claim 2, wherein the at least one register comprises a first register, wherein the at least two branches comprise a first branch and a second branch, and wherein the first register is configured to control one of the first branch and the second branch to be turned on.

The delay circuit of claim 3, wherein the first register comprises a first input and a second input, the first input and the second input are in anti-phase, the first branch comprises a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is connected to a supply voltage, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, a gate of the first PMOS transistor is connected to an input signal, and a gate of the second PMOS transistor is connected to the first input of the first register;

the first branch circuit further comprises a first NMOS tube and a second NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the input signal, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the second input of the first register.

The delay circuit of claim 4, wherein the second branch comprises a third PMOS transistor and a fourth PMOS transistor, a source of the third PMOS transistor is connected to a supply voltage, a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, a gate of the third PMOS transistor is connected to the input signal, and a gate of the fourth PMOS transistor is connected to the second input of the first register;

the second branch circuit further comprises a third NMOS tube and a fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the input signal, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the first input of the first register.

The delay circuit of claim 5, wherein the first input of the first register is 0, the second input is 1, the second PMOS transistor and the second NMOS transistor are both turned on, the fourth PMOS transistor and the fourth NMOS transistor are both turned off, and the first branch is turned on;

or, the first input of the first register is 1, the second input is 0, the second PMOS transistor and the second NMOS transistor are both turned off, the fourth PMOS transistor and the fourth NMOS transistor are both turned on, and the second branch is turned on.

The delay circuit of claim 2, wherein said at least one register comprises a first register and a second register, wherein said at least two branches comprise a first branch and a second branch, wherein said first register controls said first branch, wherein said second register controls said second branch, and wherein said first branch is connected to one of said second branch.

The delay circuit of claim 7, wherein the first register comprises a first input and a second input, the first input and the second input are in an inverse direction, the first branch comprises a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is connected to a supply voltage, a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, a gate of the first PMOS transistor is connected to an input signal, and a gate of the second PMOS transistor is connected to the first input of the first register;

the first branch circuit further comprises a first NMOS tube and a second NMOS tube, the source electrode of the first NMOS tube is grounded, the drain electrode of the first NMOS tube is connected with the source electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the input signal, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the second input of the first register.

The delay circuit of claim 8, wherein the second register comprises a third input and a fourth input, the third input and the fourth input are in an inverse direction, the second branch comprises a third PMOS transistor and a fourth PMOS transistor, a source of the third PMOS transistor is connected to a supply voltage, a drain of the third PMOS transistor is connected to a source of the fourth PMOS transistor, a gate of the third PMOS transistor is connected to the input signal, and a gate of the fourth PMOS transistor is connected to the third input of the second register;

the second branch circuit further comprises a third NMOS tube and a fourth NMOS tube, the source electrode of the third NMOS tube is grounded, the drain electrode of the third NMOS tube is connected with the source electrode of the fourth NMOS tube, the grid electrode of the third NMOS tube is connected with the input signal, the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode of the fourth NMOS tube is connected with the fourth input of the second register.

The delay circuit of claim 9, wherein when the first register controls both the second PMOS transistor and the second NMOS transistor to be turned on, and the second register controls both the fourth PMOS transistor and the fourth NMOS transistor to be turned off, the first branch is turned on;

or when the first register controls the second PMOS tube and the second NMOS tube to be both closed and the second register controls the fourth PMOS tube and the fourth NMOS tube to be both opened, the second branch circuit is switched on.

The delay circuit of claim 10, wherein the first input of the first register is 0, the second input is 1, the third input of the second register is 1, the fourth input is 0, the second PMOS transistor and the second NMOS transistor are both turned on, the fourth PMOS transistor and the fourth NMOS transistor are both turned off, and the first branch is turned on;

or, the first input of the first register is 1, the second input is 0, the third input of the second register is 0, the fourth input is 1, the second PMOS transistor and the second NMOS transistor are both turned off, the fourth PMOS transistor and the fourth NMOS transistor are both turned on, and the second branch is turned on.

A drive device, characterized in that the drive device comprises:

the delay circuit and the N-stage driving circuit according to any one of claims 1 to 11, wherein N is an integer greater than 1;

wherein, the output of the N-1 stage delay circuit is respectively connected with the input of the N stage delay circuit and the input of the N-1 stage drive circuit;

the output of the Nth stage delay circuit is connected with the input of the Nth stage drive circuit;

n output signals of the 1 st-Nth stage driving circuit form the output of the driving device together;

the driving circuit comprises at least one PMOS tube, at least one NMOS tube, a first resistor and a second resistor, wherein the at least one PMOS tube is connected with the first resistor in series, the grid electrode of the at least one PMOS tube is connected with the input signal, the at least one NMOS tube is connected with the second resistor in series, and the grid electrode of the at least one NMOS tube is connected with the input signal.

The driving apparatus as claimed in claim 12, wherein the delay between the output of the driving apparatus and the input signal is related to at least one of the number of MOS transistors in the driving apparatus, the size of the MOS transistors, the number of stages of the N-stage delay circuit and the N-stage driving circuit, the delay of the branch on which each stage of the N-stage delay circuit is turned on, or the delay of the N-stage driving circuit.

The driving apparatus as claimed in claim 13, wherein the delay between the output of the driving apparatus and the input signal comprises a delay of the N-stage delay circuit and a delay of the N-stage driving circuit, wherein the delay of the N-stage delay circuit is related to the number of stages of the N-stage delay circuit and a delay of a branch of the N-stage delay circuit where each stage of the delay circuit is turned on.

A drive arrangement as claimed in any one of claims 12 to 14, wherein the delay between the output of the drive arrangement and the input signal isa*(T ₁+T ₂+……+T _N)+T _loadWherein a is a correction coefficient, T₁For the delay of the first stage delay circuit in the N-stage delay circuit, T₂Is the delay of the second stage delay circuit of the N-stage delay circuit, … …, T_NFor the delay of the Nth stage delay circuit in the N stages of delay circuits, T_loadThe delay of the N-stage driving circuit.

A drive arrangement according to any one of claims 12 to 14, wherein the delay between the output of the drive arrangement and the input signal is a x N T_d+T _loadWherein a is a correction coefficient, N is the number of stages of the N-stage delay circuit, and T is_dFor the delay of each stage of the N stages of delay circuits, T_loadThe delay of the N-stage driving circuit.