阅读说明：本技术 一种延时电路以及驱动装置 (Time delay circuit and driving device ) 是由 李进 于 2019-03-20 设计创作，主要内容包括：一种延时电路以及驱动装置,该延时电路可以包括至少两条支路,该至少两条支路并联,至少两条支路中的每条支路具有不同的延时；该延时电路包括至少一个寄存器,该寄存器用于控制至少两条支路中的一条支路接通,使得该延时电路产生于接通的支路对应的延时。由于输入信号的延时越大,摆率越小,因此输入信号通过该至少两条支路中任意一条支路的摆率不同。通过至少一个寄存器控制该至少两条支路中的一条支路接通可以调节输出信号的摆率,使得输出信号的摆率可以兼容不同协议或同一协议下的不同模式。(A time delay circuit and a driving device, the time delay circuit can include at least two branches, the at least two branches are connected in parallel, and each branch of the at least two branches has different time delay; the delay circuit comprises at least one register for controlling one of the at least two branches to be switched on, so that the delay circuit generates a delay corresponding to the switched-on branch. The larger the delay of the input signal is, the smaller the slew rate is, so that the slew rate of the input signal passing through any one of the at least two branches is different. The slew rate of the output signal can be adjusted by controlling the connection of one branch of the at least two branches through at least one register, so that the slew rate of the output signal can be compatible with different protocols or different modes under the same protocol.)