阅读说明：本技术 基于沟道阵列的异质结场效应晶体管及其制作方法和应用 (Heterojunction field effect transistor based on channel array and preparation method thereof and application ) 是由 张晓东 张辉 张佩佩 郝荣晖 宋亮 于国浩 蔡勇 *** 于 2018-05-21 设计创作，主要内容包括：本发明公开了一种基于沟道阵列的异质结场效应晶体管及其制作方法和应用。所述基于沟道阵列的异质结场效应晶体管包括异质结以及与所述异质结配合的源极、漏极和栅极,异质结中形成有二维电子气,源极与漏极通过二维电子气电连接；所述晶体管还包括形成在所述异质结上的第三半导体,第三半导体能够将分布于其下方的二维电子气耗尽,在所述栅极下方的第三半导体中还形成有至少一第四半导体,并且第四半导体下方的二维电子气被保留而形成沟道。本发明提供的制作方法无需采用刻蚀技术,避免了刻蚀均匀性、重复性以及刻蚀损伤等问题；以H等离子处理或H扩散的方式处理P-GaN,处理深度可控,不会对下层材料以及二维电子气造成损伤,保证了器件的可靠性。(The invention discloses a kind of heterojunction field effect transistor based on channel array and preparation method thereof and application.The heterojunction field effect transistor based on channel array includes hetero-junctions and source electrode, drain and gate with hetero-junctions cooperation, and two-dimensional electron gas is formed in hetero-junctions, and source electrode is electrically connected with drain electrode by two-dimensional electron gas；The transistor further includes the third semiconductor being formed on the hetero-junctions, third semiconductor can exhaust the two-dimensional electron gas for being distributed in below, at least one the 4th semiconductor is also formed in third semiconductor below the grid, and the two-dimensional electron gas below the 4th semiconductor is retained and forms channel.Production method provided by the invention is without lithographic technique, the problems such as avoiding etching homogeneity, repeatability and etching injury；P-GaN is handled in such a way that H plasma treatment or H are spread, processing depth is controllable, will not cause to damage to subsurface material and two-dimensional electron gas, ensure that the reliability of device.)

1. a kind of heterojunction field effect transistor based on channel array, the source including hetero-junctions and with hetero-junctions cooperation Pole, drain and gate, two-dimensional electron gas is formed in the hetero-junctions, and the source electrode and drain electrode pass through the Two-dimensional electron pneumoelectric Connection；It is characterized by: the transistor further includes the third semiconductor being formed on the hetero-junctions, the third semiconductor The two-dimensional electron gas for being distributed in below can be exhausted, be also formed at least one in the third semiconductor below the grid 4th semiconductor, and the two-dimensional electron gas below the 4th semiconductor is retained and forms channel.

2. the heterojunction field effect transistor according to claim 1 based on channel array, it is characterised in that: the crystal Pipe includes the semiconductor array formed by a plurality of 4th semiconductor orientations；And/or the two of the 4th semiconductor End is respectively directed to source electrode and drain electrode；And/or the width of the 4th semiconductor is 1nm-10 μm；And/or the described 4th half lead Body is formed by the passivated processing in first area of the third semiconductor；Preferably, the Passivation Treatment include H plasma or H DIFFUSION TREATMENT.

3. the heterojunction field effect transistor according to claim 1 based on channel array, it is characterised in that: the third An at least Resistance is also formed in semiconductor, the Resistance in the third semiconductor for blocking source electrode and drain electrode Between electrical connection；Preferably, the Resistance is formed by the passivated processing of second area of the third semiconductor；Preferably, The Passivation Treatment includes H plasma or H DIFFUSION TREATMENT；Preferably, the Resistance is distributed in source electrode and the 4th semiconductor Between and/or drain electrode the 4th semiconductor between；Preferably, the material of the Resistance includes HR-GaN.

4. the heterojunction field effect transistor according to claim 1 based on channel array, it is characterised in that: described heterogeneous Knot includes the first semiconductor and the second conductor, and second semiconductor is formed on the first semiconductor, and has and be wider than the first half The band gap of conductor, the third semiconductor are formed on the second semiconductor；Preferably, the source electrode, drain electrode and the second semiconductor Form Ohmic contact；Preferably, the material of first semiconductor, the second conductor is selected from III-V compound；Preferably, institute State the first semiconductor, the material of the second conductor is selected from group III-nitride；Preferably, the material of first semiconductor includes GaN Or GaAs；Preferably, the material of second semiconductor includes AlGaN, AlInN, AlGaAs or AlInAs；And/or described Three semiconductors are P-type semiconductor；Preferably, the material of the P-type semiconductor includes P-GaN, P-AlGaN, p-type diamond or P- NiO；And/or the hetero-junctions with a thickness of 10nm~10 μm；And/or the third semiconductor with a thickness of the μ of 10nm~10 m；And/or the material of the 4th semiconductor includes HR-GaN；Preferably, between first semiconductor and the second semiconductor It is additionally provided with insert layer；Preferably, the material of the insert layer includes InGaN or AlN；And/or the hetero-junctions be formed in it is slow It rushes on layer, the buffer layer is formed on substrate；Preferably, the material of the buffer layer includes high resistant GaN or high resistant AlGaN； Preferably, the buffer layer with a thickness of 1nm-10 μm；Preferably, the material of the substrate include silicon, sapphire, silicon carbide or Gallium nitride；Preferably, the substrate with a thickness of 10-5000 μm.

5. the heterojunction field effect transistor according to claim 1 based on channel array, it is characterised in that: the grid Schottky contacts are formed between the 4th semiconductor；Alternatively, dielectric layer is also distributed between the grid and the 4th semiconductor； And/or the transistor comprising field plate structure or is free of field plate structure.

6. a kind of production method of the heterojunction field effect transistor based on channel array, include the steps that providing hetero-junctions and The step of source electrode, drain electrode of production and hetero-junctions cooperation, two-dimensional electron gas is formed in the hetero-junctions, it is characterised in that also wrap It includes:

Third semiconductor, the Two-dimensional electron gas consumption that the third semiconductor energy will be disposed below are formed on the hetero-junctions To the greatest extent；

The first area Passivation Treatment of the third semiconductor is formed at least one the 4th semiconductor, and makes the 4th semiconductor The two-dimensional electron gas of lower section is retained and forms channel；And the grid of production and the 4th semiconductor cooperation.

7. production method according to claim 6, it is characterised in that specifically include: to the firstth area of the third semiconductor Domain be passivated processing formed by a plurality of orientations the 4th semiconductor group at semiconductor array.

8. production method according to claim 6, it is characterised in that further include: by the second area of the third semiconductor Passivation Treatment forms an at least Resistance, and the Resistance is used to block between source electrode and drain electrode in the third semiconductor Electrical connection；Preferably, the Resistance is distributed between source electrode and the 4th semiconductor and/or drains between the 4th semiconductor.

9. production method described according to claim 6 or 7 or 8, it is characterised in that: the Passivation Treatment includes H plasma Or H DIFFUSION TREATMENT.

10. production method according to claim 6, it is characterised in that: the hetero-junctions includes the first semiconductor and second Conductor, second semiconductor are formed on the first semiconductor, and have the band gap for being wider than the first semiconductor, and the third is partly led Body is formed on the second semiconductor；Preferably, the source electrode, drain electrode and the second semiconductor form Ohmic contact；Preferably, described First semiconductor, the second conductor material be selected from III-V compound；Preferably, the material of first semiconductor, the second conductor Matter is selected from group III-nitride；Preferably, the material of first semiconductor includes GaN or GaAs；Preferably, described the second half The material of conductor includes AlGaN, AlInN, AlGaAs or AlInAs；And/or the third semiconductor is P-type semiconductor；It is preferred that , the material of the P-type semiconductor includes P-GaN, P-A1GaN, p-type diamond or P-NiO；And/or the thickness of the hetero-junctions Degree is 1nm~10 μm；And/or the third semiconductor with a thickness of 1nm~10 μm；And/or the both ends difference of the channel It is directed toward source electrode and drain electrode；And/or the width of the channel is 1nm-10 μm；And/or the material of the 4th semiconductor includes HR-GaN；Preferably, insert layer is additionally provided between first semiconductor and the second semiconductor；Preferably, the insert layer Material include InGaN or A1N；And/or the hetero-junctions is formed on the buffer layer, the buffer layer is formed on substrate；It is excellent Choosing, the material of the buffer layer includes high resistant GaN or high resistant A1GaN；Preferably, the buffer layer with a thickness of 1nm-10 μ m；Preferably, the material of the substrate includes silicon, sapphire, silicon carbide or gallium nitride；Preferably, the substrate with a thickness of 10-5000μm。

11. production method according to claim 6, it is characterised in that: form Xiao between the grid and the 4th semiconductor Te Ji contact or Ohmic contact；Alternatively, dielectric layer is also distributed between the grid and the 4th semiconductor；And/or the crystal Pipe is comprising field plate structure or is free of field plate structure.

12. heterojunction field effect transistor according to any one of claims 1 to 5 based on channel array is wanted by right The production method for seeking the heterojunction field effect transistor described in any one of 6-11 based on channel array make based on channel The heterojunction field effect transistor of array is in the application of RF application.

Technical field

The heterojunction field effect transistor and preparation method thereof based on channel array that the present invention relates in particular to a kind of belongs to In semiconductor radio frequency device arts.

Background technique

Heterojunction semiconductor is made of two or more different semiconductor materials.Due to having between different semiconductor materials Different the physical-chemical parameters (such as electron affinity, band structure, dielectric constant, lattice constant), meeting at contact interface The mismatch of various physico-chemical properties is generated, to make hetero-junctions that there are many new features.The base of heterojunction field effect transistor This structure is exactly comprising a hetero-junctions being made of wide bandgap material and low bandgap material.In the hetero-junctions, doped type N is miscellaneous The wide bandgap material of matter provides a large amount of electronics to the low bandgap material that undopes as the offer layer of electronics, or due to strong pole The polarity effect for changing material causes a large amount of electronics, the triangle that these electron accumulations are formed in the energy difference by two kinds of material conduction bands Two-dimensional electron gas is formed in potential well.Due to the scattering departing from alms giver's spur, and show very high mobility.It utilizes High concentration, high mobility two-dimensional electron gas as conducting channel, modulation of the electron concentration by grid voltage in channel, Source region and drain region are set in grid two sides, that is, form heterojunction field effect transistor.Since it is with very high cutoff frequency With frequency of oscillation, high current density, lesser short-channel effect and good noiseproof feature, hetero junction field effect crystal Pipe has very extensive application in terms of microwave circuit.

Since six the seventies of twentieth century, Group III-V compound semiconductor electronic device becomes the weight of people's research Point, since injecting the extension for realizing p-type GaN material using Mg particularly to the nineties discovery, even more the broad stopband GaN Brand-new conceptual phase has been pushed in the research of semiconductor material and device to, and up to the present, GaN associated materials and device remain unchanged It is international research hotspot.The forbidden bandwidth of GaN body material is 3.4eV, disruptive field intensity 3.3MV/cm, with AlGaN shape At two-dimensional electron gas mobility be greater than 2000cm²/ Vs, carrier face concentration is up to 1.0E13/cm², thus have The semiconductor devices of AlGaN/GaN heterojunction structure is more suitable for the application in terms of high-frequency high-power.

However, GaN transistor linearly ultimately limits the power density and efficiency of these devices in numerous applications, because It usually requires to retract to meet linearity specifications for the operating point of device.In fact, with working frequency by reduce grid length increase It is added to millimeter wave range, it is contemplated that can linearly further decrease.In the past few years, several physical mechanisms are proposed to explain Non-linear behavior in GaN HEMT, increase including aisle resistance, optical phonon transmitting, interface scattering and drains in height Self-heating effect etc. under electric current.There are some reports to provide and help to improve the linear technology of GaN HEMT, as MOSHEMT is tied Structure and self-aligning grid etc..Based on the theory of the increased aisle resistance in the case where high drain current is horizontal, fin-shaped nanometer ditch is proposed Road is to improve the linearity of device transconductance and cutoff frequency.Verified this structure can effectively improve the electric current of device Driving capability and the decline for inhibiting mutual conductance and cutoff frequency under high output level.But this structure can be because of side wall gold Category brings parasitic capacitance, influences the frequency characteristic of device.

Summary of the invention

The main purpose of the present invention is to provide a kind of heterojunction field effect transistor and its production based on channel array Methods and applications, with overcome the deficiencies in the prior art.

For realization aforementioned invention purpose, the technical solution adopted by the present invention includes:

The embodiment of the invention provides a kind of heterojunction field effect transistor based on channel array, including hetero-junctions and With source electrode, the drain and gate of hetero-junctions cooperation, two-dimensional electron gas, the source electrode and leakage are formed in the hetero-junctions Pole is electrically connected by the two-dimensional electron gas；It is characterized by: the transistor further includes be formed on the hetero-junctions Three semiconductors, the third semiconductor can exhaust the two-dimensional electron gas for being distributed in below, below the grid At least one the 4th semiconductor is also formed in three semiconductors, and the two-dimensional electron gas below the 4th semiconductor is retained And form channel.

The embodiment of the invention also provides a kind of production method of heterojunction field effect transistor based on channel array, packets The step of including source electrode, the drain electrode of the step of providing hetero-junctions and production and hetero-junctions cooperation, is formed with two in the hetero-junctions Dimensional electron gas, and further include:

Third semiconductor, the two-dimensional electron gas that the third semiconductor energy will be disposed below are formed on the hetero-junctions It exhausts；

The first area Passivation Treatment of the third semiconductor is formed at least one the 4th semiconductor, and makes the described 4th half Two-dimensional electron gas below conductor is retained；And the grid of production and the 4th semiconductor cooperation.

The embodiment of the invention also provides the heterojunction field effect transistor based on channel array or by described The hetero junction field effect based on channel array of the production method production of heterojunction field effect transistor based on channel array is brilliant Body pipe is in the application of RF application.

Compared with prior art, the invention has the advantages that

1) production method provided in an embodiment of the present invention can be realized enhanced, and P-GaN is not with H plasma at grid lower channel Or the mode of H diffusion handles the device of achievable enhancement type channel array；

2) production method provided in an embodiment of the present invention does not need to perform etching region under device gate, avoids because of etching Uniformity, repeatability and the introducing damage problem that technique introduces；

3) it is influenced without interfacial state, improves device reliability；

4) reduce effect of parasitic capacitance, improve the frequency characteristic of device；

5) due to the introducing of channel, the electric current of single channel is much smaller compared to traditional devices, so heat dissipation is than traditional device Part is more preferable, therefore can effectively inhibit self-heating effect present in traditional heterojunction field effect transistor；

6) production method simple process provided in an embodiment of the present invention, it is reproducible；

7) heterojunction field effect transistor provided in an embodiment of the present invention based on channel array, can be using traditional half Conductor micro-processing technology is completed, and the equipment that can be used includes lithography system (such as electron beam lithography, ion beam lithography, immersion The equipment such as photoetching, distributed exposure and optical exposure), nanometer embossing, etching apparatus (RIE, ICP, NLD etc.), ion Injection device etc..

Detailed description of the invention

Fig. 1 is the epitaxial material structure schematic diagram that formation is made in an exemplary embodiments of the invention；

Fig. 2 is that production forms the device architecture schematic diagram after source electrode and drain electrode in an exemplary embodiments of the invention；

Fig. 3 is to make to form semiconductor battle array in a manner of H plasma or H DIFFUSION TREATMENT in an exemplary embodiments of the invention Device architecture schematic diagram after column；

Fig. 4 is a kind of heterojunction field effect based on channel array structure that formation is made in an exemplary embodiments of the invention Answer the structural schematic diagram of transistor；

Fig. 5 is a kind of heterojunction field effect transistor based on channel array structure in an exemplary embodiments of the invention Top view.

Specific embodiment

In view of deficiency in the prior art, inventor is studied for a long period of time and is largely practiced, and is able to propose of the invention Technical solution.The technical solution, its implementation process and principle etc. will be further explained as follows.

The embodiment of the invention provides a kind of heterojunction field effect transistor based on channel array, including hetero-junctions and With source electrode, the drain and gate of hetero-junctions cooperation, two-dimensional electron gas, the source electrode and leakage are formed in the hetero-junctions Pole is electrically connected by the two-dimensional electron gas；It is characterized by: the transistor further includes be formed on the hetero-junctions Three semiconductors, the third semiconductor can exhaust the two-dimensional electron gas for being distributed in below, below the grid At least one the 4th semiconductor is also formed in three semiconductors, and the two-dimensional electron gas below the 4th semiconductor is retained And form channel.

Further, the transistor includes the semiconductor battle array formed by a plurality of 4th semiconductor orientations Column.

Further, the both ends of the 4th semiconductor are respectively directed to source electrode and drain electrode.

Further, the width of the 4th semiconductor is 1nm-10 μm.

Further, the 4th semiconductor is formed by the passivated processing in first area of the third semiconductor.

Preferably, the Passivation Treatment includes H plasma or H DIFFUSION TREATMENT or other can convert P-type semiconductor For the method for high-resistance semi-conductor or non-P-type semiconductor.

Further, an at least Resistance is also formed in the third semiconductor, the Resistance is used for described Being electrically connected between source electrode and drain electrode is blocked in third semiconductor.

Preferably, the Resistance is formed by the passivated processing of second area of the third semiconductor.

Preferably, the Passivation Treatment includes H plasma or H DIFFUSION TREATMENT or other can convert P-type semiconductor For the method for high-resistance semi-conductor or non-P-type semiconductor.

Preferably, the Resistance is distributed between source electrode and the 4th semiconductor and/or drains between the 4th semiconductor.

Preferably, the material of the Resistance includes HR-GaN.

Further, the hetero-junctions includes the first semiconductor and the second conductor, and second semiconductor is formed in first On semiconductor, and there is the band gap for being wider than the first semiconductor, the third semiconductor is formed on the second semiconductor.

Preferably, the source electrode, drain electrode and the second semiconductor form Ohmic contact.

Preferably, the material of first semiconductor, the second conductor is selected from III-V compound.

Preferably, the material of first semiconductor, the second conductor is selected from group III-nitride.

Preferably, the material of first semiconductor includes GaN or GaAs, but not limited to this.

Preferably, the material of second semiconductor includes AlGaN, AlInN, AlGaAs or AlInAs, but not limited to this.

Further, the third semiconductor is P-type semiconductor.

Preferably, the material of the P-type semiconductor includes P-GaN, P-AlGaN, p-type diamond or P-NiO, but is not limited to This.

Further, the hetero-junctions with a thickness of 1nm~10 μm.

Further, the third semiconductor with a thickness of 10nm~10 μm.

Further, the material of the 4th semiconductor includes HR-GaN.

Preferably, insert layer is additionally provided between first semiconductor and the second semiconductor.

Preferably, the material of the insert layer includes InGaN or AlN, but not limited to this.

Further, the hetero-junctions is formed on the buffer layer, and the buffer layer is formed on substrate.

Preferably, the material of the buffer layer includes high resistant GaN or high resistant AlGaN, but not limited to this.

Preferably, the buffer layer with a thickness of 1nm-10 μm.

Preferably, the material of the substrate includes silicon, sapphire, silicon carbide or gallium nitride, but not limited to this.

Preferably, the substrate with a thickness of 10-5000 μm.

Further, Schottky contacts or Ohmic contact are formed between the grid and the 4th semiconductor；Alternatively, the grid Dielectric layer is also distributed between pole and the 4th semiconductor.

Further, the transistor comprising field plate structure or is free of field plate structure.

The embodiment of the invention also provides a kind of production method of heterojunction field effect transistor based on channel array, packets The step of including source electrode, the drain electrode of the step of providing hetero-junctions and production and hetero-junctions cooperation, is formed with two in the hetero-junctions Dimensional electron gas, and further include:

Third semiconductor, the two-dimensional electron gas that the third semiconductor energy will be disposed below are formed on the hetero-junctions It exhausts；

The first area Passivation Treatment of the third semiconductor is formed at least one the 4th semiconductor, and makes the described 4th half Two-dimensional electron gas below conductor is retained and forms channel；And

The grid of production and the 4th semiconductor cooperation.

Further, the production method specifically includes: being passivated place to the first area of the third semiconductor Reason formed by a plurality of orientations the 4th semiconductor group at semiconductor array.

Further, the production method further include: form the second area Passivation Treatment of the third semiconductor An at least Resistance, the Resistance are used to block being electrically connected between source electrode and drain electrode in the third semiconductor.

Preferably, the Resistance is distributed between source electrode and the 4th semiconductor and/or drains between the 4th semiconductor.

Preferably, the Passivation Treatment includes H plasma or H DIFFUSION TREATMENT or other can convert P-type semiconductor For the method for high-resistance semi-conductor or non-P-type semiconductor.

Further, the hetero-junctions includes the first semiconductor and the second conductor, and second semiconductor is formed in first On semiconductor, and there is the band gap for being wider than the first semiconductor, the third semiconductor is formed on the second semiconductor.

Preferably, the source electrode, drain electrode and the second semiconductor form Ohmic contact.

Preferably, the material of first semiconductor, the second conductor is selected from III-V compound.

Preferably, the material of first semiconductor, the second conductor is selected from group III-nitride.

Preferably, the material of first semiconductor includes GaN or GaAs, but not limited to this.

Preferably, the material of second semiconductor includes AlGaN, AlInN, AlGaAs or AlInAs, but not limited to this.

Further, the third semiconductor is P-type semiconductor.

Preferably, the material of the P-type semiconductor includes P-GaN, P-AlGaN, p-type diamond or P-NiO, but is not limited to This.

Further, the hetero-junctions with a thickness of 10nm~10 μm.

Further, the third semiconductor with a thickness of 10nm~10 μm.

Further, the material of the 4th semiconductor includes HR-GaN.

Preferably, insert layer is additionally provided between first semiconductor and the second semiconductor.

Preferably, the material of the insert layer includes InGaN or AlN, but not limited to this.

Further, the hetero-junctions is formed on the buffer layer, and the buffer layer is formed on substrate.

Preferably, the material of the buffer layer includes high resistant GaN or high resistant AlGaN, but not limited to this.

Preferably, the buffer layer with a thickness of 1nm-10 μm.

Preferably, the material of the substrate includes silicon, sapphire, silicon carbide or gallium nitride, but not limited to this.

Preferably, the substrate with a thickness of 10-5000 μm.

Further, Schottky contacts or Ohmic contact are formed between the grid and the 4th semiconductor；Alternatively, the grid Dielectric layer is also distributed between pole and the 4th semiconductor.

Further, the transistor comprising field plate structure or is free of field plate structure.

The embodiment of the invention also provides the heterojunction field effect transistor based on channel array or by described The hetero junction field effect based on channel array of the production method production of heterojunction field effect transistor based on channel array is brilliant Body pipe is in the application of RF application.

The structure of the heterojunction field effect transistor based on channel array provided in the embodiment of the present invention such as Fig. 4 and Fig. 5 Shown, the embodiment of the present invention on the compound heterostructure of iii-v element compounds by depositing p-GaN (or P-AlGaN Etc. p-type semiconductor materials), and device architecture as shown in Figure 4 is made, when MOCVD or MBE carries out P-GaN material epitaxy It uses Mg as dopant, and H and Mg forms complex compound, Mg is prevented from forming effective doping (to be at this time high resistant gallium nitride (HR- GaN)), and then P-GaN hole concentration is influenced；Annealing process is generally carried out after the GaN of epi dopant Mg, overflows H, and Mg activates to form P-GaN, so H plays particularly important role in P-GaN and HR-GaN is mutually converted, with H plasma P-GaN after body or H DIFFUSION TREATMENT Mg activation, so that Mg is not re-used as Effective Doping.Using can produce hydrogen (H) plasma Body or the equipment of hydrogen (H) diffusion, are not limited to the equipment such as reactive ion etching (ICP, RIE, NLD), utilize H plasma or H The P-GaN of electronic device of the DIFFUSION TREATMENT based on AlGaN/GaN two-dimensional electron gas forms HR-GaN array.In H plasma Or during H DIFFUSION TREATMENT, the region P-GaN that H plasma or H diffusion or H DIFFUSION TREATMENT are crossed can be passivated to form high resistant nitrogen Change gallium (HR-GaN), and then the AlGaN/GaN two-dimensional electron gas under the region HR-GaN is not exhausted by P-GaN, to form tool There is the nano-channel array of two-dimensional electron gas.

The production method of heterojunction field effect transistor provided in an embodiment of the present invention based on channel array without Lithographic technique, the problems such as avoiding etching homogeneity, repeatability and etching injury；Meanwhile it being spread with H plasma treatment or H Mode P- GaN depth it is controllable, subsurface material and two-dimensional electron gas will not be caused to damage, ensure that the reliability of device.

In some more specific embodiments, a kind of production of the heterojunction field effect transistor based on channel array Method may include steps of:

1) Metal Organic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy (MBE) or hydrite vapor phase are utilized Extension (HVPE) homepitaxy technology, growth substrates/buffer layer/iii-v element compound heterojunction structure/p-type semiconductor material Structure；The material of substrate can select Si, SiC or sapphire etc., and the thickness of substrate can be from 10 μm to 10mm；Preferably, Buffer layer can select high resistant GaN etc., and the thickness of buffer layer can be from 10nm to 1mm；Preferably, iii-v element compound Heterojunction structure can be AlGaN/GaN heterojunction structure, AlInN/GaN heterojunction structure, AlGaN/InGaN/GaN heterojunction structure, AlGaN/AlN/GaN heterojunction structure etc.；Preferably, the thickness of iii-v element compound heterojunction structure can be from 10nm to 10 μm；Preferably, p-type semiconductor can select the p-type semiconductor materials such as p-GaN, p-AlGaN, p-type diamond, p-NiO, thickness It can be from 1nm to 1 μm；

2) P of the dry or wet etch technologies such as reactive ion etching, ion beam etching removal source and drain ohmic area is utilized Type semiconductor (such as the p-type semiconductor materials such as P-AlGaN, p-type diamond, P-NiO) and part AlGaN layer, etch areas It can be determined by photoetching or exposure mask transfer techniques；

3) using metal deposition techniques such as electron beam evaporation or sputterings, in ohmic area production source electrode (S) and drain electrode (D), then ohmic metal is made annealing treatment, it is therefore an objective to source electrode and drain electrode and hetero-junctions be made to form good Ohmic contact； Processing region can be determined by the technologies such as photoetching and exposure mask transfer；Can there is no field in hetero junction field effect pipe structure Plate, or source field plate can also be added to improve the breakdown voltage of device, improve the performance of device；

4) using can produce hydrogen (H) plasma or have the equipment of hydrogen (H) atmosphere, it is not limited to reactive ion etching Equipment such as (ICP, RIE, NLD), the electronics device using H plasma or H DIFFUSION TREATMENT based on AlGaN/GaN two-dimensional electron gas The P-GaN of the channel region of part；Simultaneously by the P-GaN near source and drain ohmic area also with H plasma or H DIFFUSION TREATMENT, with Source and drain metal is prevented to be connected to by P-GaN, the region of H plasma or H DIFFUSION TREATMENT is connect with source and drain ohmic area；Place Reason region can be determined by the technologies such as photoetching and exposure mask transfer；Preferably, the plane of HR-GaN (i.e. the 4th semiconductor) Geometry is regular shape or non-regular shape；Preferably, the shape of different HR-GaN arranged side by side is same shape or non-phase Similar shape；HR-GaN can be single, can also be the HR-GaN array of a plurality of HR-GaN composition；The width of every HR-GaN can With from several nanometers to the range of several microns, such as 1nm~10 μm, so that formation width is from several nanometers to several microns Channel；The length and width of HR-GaN is adjustable；

5) using metal deposition techniques such as electron beam evaporation or sputterings, the channel between source electrode (S) and drain electrode (D) Upper production gate electrode (G)；Processing region can be determined by the technologies such as photoetching and exposure mask transfer, and the shape of grid metal is Commonly, T-type or V-type；The size of grid metal is sub-micron or larger size；Grid metal can be with the contact of the 4th semiconductor Schottky contacts or Ohmic contact, or in order to further decrease grid Leakage Current or increase the breakdown voltage of device, it can also be with Using metal-insulating layer-semiconductor contact or metal oxide layer-semiconductor contact；It can be in hetero junction field effect pipe structure There is no field plate, or grid field plate can also be added to improve the breakdown voltage of device, improves the performance of device.

For example, a specific embodiment of the invention provides a kind of heterojunction field effect transistor based on channel array, Structure can be refering to shown in Fig. 4-Fig. 5 comprising GaN/III group-III nitride semiconductor hetero-junctions, GaN/III group-III nitride half Conductor hetero-junctions is formed in Sapphire Substrate, and source and leakage are formed on GaN/III group-III nitride semiconductor hetero-junctions Pole, the source electrode are electrically connected with drain electrode by the two-dimensional electron gas, and P-type semiconductor, the p-type half are formed in GaN layer Conductor can exhaust the two-dimensional electron gas for being distributed in below；It is formed in P-type semiconductor by a plurality of HR-GaN (i.e. 4th semiconductor) orientations formed HR-GaN array, the both ends of the HR-GaN are respectively directed to source electrode and drain electrode, are located at Two-dimensional electron gas below HR-GaN array is retained and forms the channel array；Grid is set to the HR-GaN array On；And Resistance high resistant half is also formed in the P-type semiconductor between source electrode and HR- GaN, between drain electrode and HR-GaN Conductor.

A kind of production method of the present embodiment heterojunction field effect transistor may include steps of:

1) epitaxial material structure as shown in Figure 1, lining are grown using Metal Organic Chemical Vapor Deposition (MOCVD) Bottom materials select silicon, sapphire, silicon carbide, gallium nitride or other materials, with a thickness of 10 μm~5000 μm, preferably 400 μm； The material selection high resistant GaN or high resistant AlGaN of buffer layer, with a thickness of 1nm~5000nm, preferably 4200nm；AlGaN/GaN Heterojunction structure (GaN could alternatively be GaAs or other are capable of providing the material of hetero-junctions, AlGaN could alternatively be AlInN, AlGaAs or InGaAs or other be capable of providing the material of hetero-junctions) in GaN with a thickness of 100nm~500nm, preferably 260nm； AlGaN is with a thickness of 15nm~30nm, preferably 18nm, and wherein the content of Al component is 15~30wt%, preferably 18wt%；p Type semiconductor material selects p-GaN, with a thickness of 10nm~200nm, preferably 70nm；

2) using the P-GaN and part AlGaN layer of reactive ion etching technology removal source and drain ohmic area, and using electricity Beamlet evaporation technique make source metal and drain metal (source metal and/or drain metal can be Ti/Al/Ni/Au, That is, including Ti layer, Al layers, Ni layers, Au layers being cascading), then in nitrogen (N₂) under the conditions of 875 DEG C of annealing 30s, The device architecture made after forming source metal and drain metal is as shown in Figure 2；

3) using can reactive ion etching (ICP) equipment, handled and be based in a manner of H plasma or H DIFFUSION TREATMENT The P-GaN of the electronic device of AlGaN/GaN (hetero-junctions) two-dimensional electron gas, to form the semiconductor array being made of HR-GaN； By the P-GaN near source and drain ohmic area, also processing forms HR- GaN in a manner of H plasma or H DIFFUSION TREATMENT simultaneously, with Source and drain metal is prevented to be connected to by P-GaN, the region of H plasma or H DIFFUSION TREATMENT is connect with source and drain ohmic area；System The device architecture for forming channel array is as shown in Figure 3；

4) using electron beam evaporation technique production gate metal, (gate metal can be Ni/Au, to be cascading Ni layer, Au layers), production formed the heterojunction field effect transistor based on channel array structure.

Compared with the prior art, the heterojunction field effect transistor provided in an embodiment of the present invention based on channel array can be real Now it is greater than the threshold voltage of zero volt, the positive maximum safe operating voltage of grid is higher, and strong antijamming capability, device stability is good, Simultaneously because its production method is without lithographic technique, the problems such as avoiding etching homogeneity, repeatability and etching injury； Meanwhile P-GaN is handled in a manner of H plasma treatment or H DIFFUSION TREATMENT, processing depth is controllable, will not to subsurface material and Two-dimensional electron gas causes to damage, and ensure that the reliability of device.

It should be appreciated that the technical concepts and features of above-described embodiment only to illustrate the invention, its object is to allow be familiar with this The personage of item technology cans understand the content of the present invention and implement it accordingly, and it is not intended to limit the scope of the present invention.It is all Equivalent change or modification made by Spirit Essence according to the present invention, should be covered by the protection scope of the present invention.