阅读说明：本技术 具有部分碳化硅/硅半导体材料异质结的vdmos及其制作方法 (With partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof ) 是由 段宝兴 王夏萌 杨鑫 张一攀 杨银堂 于 2019-08-15 设计创作，主要内容包括：本发明提出了一种具有部分碳化硅/硅半导体材料异质结的VDMOS及其制作方法,该异质结VDMOS器件主要特点是在外延层上形成部分具有碳化硅材料与硅材料相结合的异质结,采用硅成熟工艺形成VDMOS器件的有源区,相比于碳化硅材料,热生长氧化层与硅表面的界面质量更高,使得反型层迁移率高,也不会在栅氧化层产生很高的电场引起烧毁,而利用碳化硅半导体材料的高临界击穿电场,抬高了器件的纵向电场峰,器件可承担更高的击穿电压,同时碳化硅半导体材料的热导率高,更有利于器件散热。(The invention proposes a kind of with partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof, the hetero-junctions VDMOS device is mainly characterized by forming the hetero-junctions that there is carbofrax material to combine with silicon materials for part on epitaxial layer, the active area of VDMOS device is formed using silicon mature technology, compared to carbofrax material, the interface quality of thermal growth oxide layer and silicon face is higher, so that inversion layer mobility is high, very high electric field will not be generated in gate oxide to cause to burn, and utilize the high critical breakdown electric field of manufacturing silicon carbide semiconductor material, the longitudinal electric field peak of device is raised, device can undertake higher breakdown voltage, the thermal conductivity of manufacturing silicon carbide semiconductor material is high simultaneously, it is more advantageous to device heat dissipation.)

1. having partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, comprising:

N+ type substrate (801)；

N-type epitaxy layer positioned at N+ type substrate (801) upper surface；

The p-type base area (7) that left and right two end regions are respectively formed on N-type epitaxy layer top；N+ type source region is formed in p-type base area (7) (6) and P+ channeled substrate contacts (5) and corresponding channel, and wherein N+ type source region (6) and channel are adjacent, the contact of P+ channeled substrate (5) side of channel is located remotely from relative to N+ type source region (6)；

Gate oxide (2), be located at N-type epitaxy layer upper surface intermediate region, covering two at p-type base area (7) channel and its between Region；

Grid (3) is located at gate oxide (2) upper surface；

Source electrode, covering P+ channeled substrate contact (5) connect the upper surface in region with N+ type source region (6)；Source electrode (1,4) is total at two It connects；

It drains (9), is located at N+ type substrate (801) lower surface；

It is characterized by:

The N+ type substrate (801) uses carbofrax material；

The N-type epitaxy layer is made of two parts: a part is N-type silicon carbide epitaxial layers (802) at two, is located at the N+ Left and right two end regions in type substrate (801) upper surface；Another part is N-type silicon epitaxy layer (803), is T font structure, is based on institute State the upper surface of N-type silicon carbide epitaxial layers (802) at N+ type substrate (801) upper surface intermediate region and two, and adjacent described two Locate the medial surface of N-type silicon carbide epitaxial layers (802)；P-type base area (7) are correspondingly formed on the N-type silicon epitaxy layer (803) at two Left and right two end regions in portion, the longitudinal boundary of p-type base area (7) extend into corresponding N-type silicon carbide epitaxial layers (802), i.e. P The PN junction that type base area and N-type silicon carbide epitaxial layers are formed is located in N-type silicon carbide epitaxial layers, and channel is still located at N-type silicon epitaxy layer (803) in；

The thickness and doping concentration of the N-type silicon carbide epitaxial layers (802) are determined by the resistance to pressure request of device, outside N-type silicon carbide The doping concentration for prolonging layer (802) is lower than the doping concentration of N+ type substrate (801).

2. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: The small 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ type substrate (801) of N-type silicon carbide epitaxial layers (802).

3. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: The doping concentration of the N-type silicon epitaxy layer (803) is 1 × 10¹⁵~5 × 10¹⁵cm^-3, the N-type silicon carbide epitaxial layers (802) Doping concentration is 1 × 10¹⁴~5 × 10¹⁴cm^-3。

4. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: The p-type base area (7) and its N+ type source region (6) and P+ channeled substrate contact (5) are formed using ion implantation technique, accordingly Channel utilize double diffusion technique formation.

5. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: N-type silicon carbide epitaxial layers (802) are formed by etching to the silicon carbide progress intermediate region of epitaxial growth at described two, are carved Erosion extends to N+ type substrate (801) upper surface.

6. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: Grid (3) is polysilicon gate, and source electrode (1,4) is metallizing source, and drain electrode (9) is metalized drain.

7. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: The longitudinal boundary of p-type base area (7) extends into (802) 2~4 μm of corresponding N-type silicon carbide epitaxial layers.

8. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: The lower width (L2) of N-type silicon epitaxy layer (803) T font structure is 1~4 μm；Everywhere N-type silicon carbide epitaxial layers (802) Width (L1) is 6~7.5 μm；The distance (L3) of N-type silicon carbide epitaxial layers (802) to device surface is 0.5~3 μm.

9. according to claim 1 have partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, it is characterised in that: Drift region length is 15 microns, and the resistance to pressure request of device is 400V, then the width (L1) of everywhere N-type silicon carbide epitaxial layers is 7.5 microns, the lower width (L2) of N-type silicon epitaxy layer T font structure is 1 micron, N-type silicon carbide epitaxial layers to device surface Distance (L3) is 1 micron.

10. a kind of make the method described in claim 1 with partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, The following steps are included:

1) use N+ type silicon carbide semiconductor material as substrate (801)；

2) N-type epitaxy layer that carbofrax material is formed in the type silicon carbide upper surface N+ forms ditch after etching away intermediate a part Slot, groove turnes down to substrate top, remaining to be denoted as N-type silicon carbide epitaxial layers (802)；

3) N-type silicon epitaxy layer (803) are formed using bonding techniques or heteroepitaxial growth technology；

4) metalized drain is formed in N+ type substrate (801) lower surface；

5) left and right two end regions on N-type silicon epitaxy layer (803) top form p-type base area (7) and its N+ type using ion implanting Source region (6) and P+ channeled substrate contact (5), and corresponding channel is formed using double diffusion technique, it is ensured that the longitudinal edge of p-type base area Boundary extends into silicon carbide N type epitaxial layer, i.e., the PN junction that p-type base area and N-type silicon carbide epitaxial layers are formed is located at outside N-type silicon carbide Prolong in layer, channel is still located in silicon epitaxy layer；

6) depositing polysilicon forms polysilicon gate after entire N-type silicon epitaxy layer (803) upper surface grows gate oxide；

7) passivation layer is deposited in device surface, and etches contact hole in the position for corresponding to source electrode；

8) metal is deposited in contact hole and is etched and forms source electrode, and source electrode at two is connect altogether.

Technical field

The present invention relates to power semiconductor field more particularly to a kind of vertical bilateral diffusion metallic oxide field effect pipes And preparation method thereof.

Background technique

The continuous growth of global energy requirements and stepping up so that efficient, energy-conserving product becomes for environmental protection consciousness The new trend of market development.The development of electronic product has entered a new stage due to the appearance of power semiconductor. Power semiconductor has the advantages that switching speed is fast, input impedance is high, easy driving, there is no second breakdown, vertical double expansions Dispersed metallic-oxide semiconductor field effect transistor (VDMOS) has the advantages of bipolar transistor and common MOS device concurrently no matter It is switch application or linear application, VDMOS is ideal power device, and VDMOS is mainly used in electric machine speed regulation, inversion Device, uninterruptible power supply, electronic switch, high-fidelity music center, car electrics and electric ballast etc..

Summary of the invention

The invention proposes a kind of with partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS and preparation method thereof, It is further intended to improve the breakdown voltage of VDMOS, improves device performance.

Technical scheme is as follows:

This is with partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, comprising:

N+ type substrate；

Positioned at the N-type epitaxy layer of N+ type upper surface of substrate；

The p-type base area that left and right two end regions are respectively formed on N-type epitaxy layer top；In p-type base area formed N+ type source region and The contact of P+ channeled substrate and corresponding channel, wherein N+ type source region and channel are adjacent, and P+ channeled substrate is contacted relative to N+ type Source region is located remotely from the side of channel；

Gate oxide, be located at N-type epitaxy layer upper surface intermediate region, covering two at p-type base area channel and its between Region；

Grid is located at gate oxide upper surface；

Source electrode, covering P+ channeled substrate contact the upper surface in the region that connects with N+ type source region；Source electrode connects altogether at two；

Drain electrode is located at the N+ type substrate lower surface；

It is characterized in that

The N+ type substrate uses carbofrax material；

The N-type epitaxy layer is made of two parts: a part is N-type silicon carbide epitaxial layers at two, is located at the N+ Left and right two end regions of type upper surface of substrate；Another part is N-type silicon epitaxy layer, is T font structure, is based on the N+ type substrate The upper surface of N-type silicon carbide epitaxial layers at upper surface intermediate region and two, and at adjacent described two N-type silicon carbide epitaxial layers it is interior Side；P-type base area is correspondingly formed left and right two end regions in N-type silicon epitaxy layer top, the longitudinal edge of p-type base area at two Boundary extends into corresponding N-type silicon carbide epitaxial layers, i.e., the PN junction that p-type base area and N-type silicon carbide epitaxial layers are formed is located at N-type carbon In SiClx epitaxial layer, channel is still located in N-type silicon epitaxy layer；

The thickness and doping concentration of the N-type silicon carbide epitaxial layers determines by the resistance to pressure request of device, N-type silicon carbide epitaxy The doping concentration of layer is lower than the doping concentration of N+ type substrate.

On the basis of above scheme, the present invention has also further made following optimization:

The small 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ type substrate of N-type silicon carbide epitaxial layers.

The doping concentration of N-type silicon epitaxy layer is 1 × 10¹⁵~5 × 10¹⁵cm^-3, the doping concentration of N-type silicon carbide epitaxial layers is 1×10¹⁴~5 × 10¹⁴cm^-3。

P-type base area and its N+ type source region and the contact of P+ channeled substrate are formed using ion implantation technique, corresponding ditch Road is formed using double diffusion technique.

N-type silicon carbide epitaxial layers are formed by etching to the silicon carbide progress intermediate region of epitaxial growth at two, are carved Erosion extends to N+ type upper surface of substrate.

Grid is polysilicon gate, and source electrode is metallizing source, is drained as metalized drain.

The longitudinal boundary of p-type base area extends into 2~4 μm of corresponding N-type silicon carbide epitaxial layers.

The lower width L2 of N-type silicon epitaxy layer T font structure is 1~4 μm；The width of everywhere N-type silicon carbide epitaxial layers L1 is 6~7.5 μm；The distance L3 of N-type silicon carbide epitaxial layers to device surface is 0.5~3 μm.

A method of it makes above-mentioned with partially carbonized silicon/silicon semiconductor material hetero-junctions VDMOS, including following step It is rapid:

1) use N+ type silicon carbide semiconductor material as substrate；

2) N-type epitaxy layer that carbofrax material is formed in the type silicon carbide upper surface N+, after etching away intermediate a part, shape At groove, groove turnes down to substrate top, remaining to be denoted as N-type silicon carbide epitaxial layers；

3) N-type silicon epitaxy layer is formed using bonding techniques or heteroepitaxial growth technology；

4) metalized drain is formed in the type substrate lower surface N+；

5) left and right two end regions on N-type silicon epitaxy layer top form p-type base area and its N+ type source region using ion implanting It is contacted with P+ channeled substrate, and corresponding channel is formed using double diffusion technique, it is ensured that the longitudinal boundary of p-type base area extends into carbon In SiClx N-type epitaxy layer, i.e., the PN junction that p-type base area and N-type silicon carbide epitaxial layers are formed is located in N-type silicon carbide epitaxial layers, ditch Road is still located in silicon epitaxy layer；

6) depositing polysilicon forms polysilicon gate after entire N-type silicon epitaxy layer upper surface grows gate oxide；

7) passivation layer is deposited in device surface, and etches contact hole in the position for corresponding to source electrode；

8) metal is deposited in contact hole and is etched and forms source electrode, and source electrode at two is connect altogether.

Technical solution of the present invention has the beneficial effect that:

The substrate of VDMOS device uses carbofrax material, by the lesser N-type silicon carbide epitaxial layers of doping concentration in silicon carbide N+ type substrate material upper surface is formed, and using the N-type silicon carbide for being etched away intermediate a part, forms groove, then by heterogeneous Epitaxy technology (or bonding techniques) forms N-type silicon epitaxy layer.Silicon substrate channel is more advantageous to electric current and flows through, and avoids silicon carbide channel Resistance is big, and the active area of VDMOS device, compared to carbofrax material, thermal growth oxide layer and silicon are formed using silicon mature technology The interface quality on surface is higher, so that inversion layer mobility is high, will not generate very high electric field in gate oxide and cause to burn. Using the high critical breakdown electric field of manufacturing silicon carbide semiconductor material, the longitudinal electric field peak of device is raised, so that the breakdown potential of device Pressure improves, and improves breakdown voltage and the limit relation than conducting resistance in traditional VDMOS.Field distribution is optimized, device is made Resistance to pressure reach best.The thermal conductivity of manufacturing silicon carbide semiconductor material is high simultaneously, is more advantageous to device heat dissipation, effectively improves device Part performance.

Detailed description of the invention

Fig. 1 is structural schematic diagram of the invention.

Wherein, 1- source electrode；2- gate oxide；3- grid；4- source electrode；5-P+ channeled substrate contacts (P+ type body area)；6-N+ Type source region；7-P type base area；801-N+ type substrate；802-N type silicon carbide epitaxial layers；803-N type silicon epitaxy layer；9- drain electrode.

Specific embodiment

The present invention is introduced by taking N-channel VDMOS as an example with reference to the accompanying drawing.

As shown in Figure 1, this example includes:

The N+ type substrate 801 of carbofrax material；

In the N-type silicon carbide epitaxial layers 802 that 801 upper surface of N+ type substrate is formed；

Outside the N-type silicon that 802 surface of N-type silicon carbide epitaxial layers is formed by bonding techniques or heteroepitaxial growth technology Prolong layer 803；

Left and right two end regions on N-type silicon epitaxy layer top are respectively formed p-type base area 7 at two；

In everywhere p-type base area 7, N+ type source region 6 and P+ channeled substrate contact 5, and and ditch are formed using ion implanting Road contact, wherein N+ type source region 6 and channel are adjacent, and P+ channeled substrate contact 5 is located at remote apart from channel relative to N+ type source region 6 Side；

In p-type base area, longitudinal boundary is extended into silicon carbide N type epitaxial layer, i.e. p-type base area and N-type silicon carbide epitaxy The PN junction that layer is formed is located in N-type silicon carbide epitaxial layers, and channel is still located in silicon epitaxy layer；

N-type silicon epitaxy layer is covered, forms gate oxide 2 at two between p-type base area 7 and at corresponding two on channel；

Grid 3 is formed on gate oxide upper surface；

The upper surface that covering P+ channeled substrate contact 5 connects region with N+ type source region 6 forms source electrode 1,4；Source electrode 1,4 at two It connects altogether；

Drain electrode 9 is formed in 801 lower surface of N+ type substrate；

Wherein, the small 4-6 order of magnitude of doping concentration of the doping concentration ratio N+ type substrate of N-type silicon carbide epitaxial layers.N-type silicon The doping concentration of epitaxial layer is 1 × 10¹⁵~5 × 10¹⁵cm^-3, the doping concentration of N-type silicon carbide epitaxial layers is 1 × 10¹⁴~5 × 10¹⁴cm^-3。

The longitudinal boundary of p-type base area extends into 2~4 μm of corresponding N-type silicon carbide epitaxial layers.N-type silicon epitaxy layer T font knot The lower width L2 of structure is 1~4 μm；The width L1 of everywhere N-type silicon carbide epitaxial layers is 6~7.5 μm；N-type silicon carbide epitaxy The distance L3 of layer to device surface is 0.5~3 μm.

By taking N-channel VDMOS as an example, it can specifically be prepared by following steps:

1) use N+ type silicon carbide semiconductor material as substrate 801；

2) N-type epitaxy layer that carbofrax material is formed in 801 upper surface of N+ type silicon carbide etches away intermediate a part Afterwards, groove is formed, groove turnes down to substrate top, remaining to be denoted as N-type silicon carbide epitaxial layers 802；

The 1 × 10 of N-type silicon carbide epitaxial layers 802¹⁴~5 × 10¹⁴cm^-3, the doping concentration ratio of N-type silicon carbide epitaxial layers 802 The small 4-6 order of magnitude of the doping concentration of N+ type substrate 801；

3) N-type silicon epitaxy layer 803 is formed using bonding techniques or heteroepitaxial growth technology；

4) metalized drain is formed in 801 lower surface of N+ type substrate；

5) left and right two end regions on N-type silicon epitaxy layer top form p-type base area 7 and its N+ type source using ion implanting Area 6 and P+ channeled substrate contact 5, and corresponding channel is formed using double diffusion technique, it is ensured that the longitudinal boundary of p-type base area extends Enter in silicon carbide N type epitaxial layer, i.e., the PN junction that p-type base area and N-type silicon carbide epitaxial layers are formed is located at N-type silicon carbide epitaxial layers Interior, channel is still located in silicon epitaxy layer；

6) form gate oxide in entire N-type silicon epitaxy layer upper surface, and depositing polysilicon, then etches polycrystalline silicon and Gate oxide removal is located at the part of left and right two end regions, forms polysilicon gate；

7) passivation layer is deposited in device surface, and etches contact hole in the position for corresponding to source electrode；

8) metal is deposited in contact hole and etches removal remaining passivation layer formation source electrode of periphery, and source electrode at two is total to It connects.

The hetero-junctions VDMOS device is mainly characterized by being formed part on epitaxial layer with carbofrax material and silicon materials phase In conjunction with hetero-junctions the lower N-type silicon carbide of doping concentration half is formed on silicon carbide N+type substrate using growth technology Conductor material epitaxial layers form groove, then partly lead using the N-type silicon carbide for being etched away intermediate a part with the N-type silicon carbide Body epitaxial layer is that basic heteroepitaxial growth (or utilizing bonding techniques) forms N-type silicon semiconductor material epitaxial layer.Using silicon at Ripe technique forms the active area of VDMOS device, and compared to carbofrax material, the interface quality of thermal growth oxide layer and silicon face is more Height will not generate very high electric field in gate oxide and cause to burn so that inversion layer mobility is high, and partly be led using silicon carbide The high critical breakdown electric field of body material, has raised the longitudinal electric field peak of device, and device can undertake higher breakdown voltage, while carbon The thermal conductivity of SiClx semiconductor material is high, is more advantageous to device heat dissipation.

Show performance improvement of the device compared with traditional silicon substrate VDMOS through ISE TCAD emulation, two kinds of device drift regions Length is identical, and in the identical situation of drift doping concentration, the breakdown voltage of the device is improved compared to traditional silicon substrate VDMOS 3-4 times.For example, drift region length is 15 microns, the width L1 of everywhere N-type silicon carbide epitaxial layers is 7.5 microns, outside N-type silicon The lower width L2 for prolonging layer T font structure is 1 micron, and the distance L3 of N-type silicon carbide epitaxial layers to device surface is 1 micron, device The pressure resistance of part can reach 400V.

VDMOS in the present invention may be P-type channel, and structure is equal with N-channel VDMOS, also should be regarded as belonging to this Apply for scope of protection of the claims, details are not described herein.

In VDMOS of the invention, 802 and 803 can also be different type with homotype, it may be assumed that 802 be N-type silicon carbide epitaxy Layer, 803 may be P-type silicon epitaxial layer；Can also be with 802 for p-type silicon carbide epitaxial layers, 803 be N-type silicon epitaxy layer；It can also be with 802 be p-type silicon carbide epitaxial layers, and 803 be P-type silicon epitaxial layer.Its structure is equal with the present invention, should also be regarded as belonging to this Shen Please scope of protection of the claims, details are not described herein.