阅读说明：本技术 集成磁隔离芯片的边沿检测电路及边沿转换电路 (The edge sense circuit and edge conversion circuit of integrated Magnetic isolation chip ) 是由 王佐 袁思彤 文守甫 王建斌 罗和平 程瑜 李威 于 2019-08-22 设计创作，主要内容包括：集成磁隔离芯片的边沿检测电路和边沿转换电路,涉及集成电路技术。本发明包括：第一PMOS管,其源极接参考高电平,漏极接第二PMOS管的源极,栅极接信号输入端和第一输出点；第二PMOS管,其漏极接第二参考点,其栅极接第三PMOS管的栅极和漏极；第三PMOS管,其源极接参考高电平,其漏极通过第一电流源接地；第四NMOS管,其源极接地,栅极和漏极接第五NMOS管的栅极,漏极还接第二电流源的输出端；第五NMOS管,其源极接第六NMOS管的漏极,其漏极接第二输出点,漏极还通过电容接地；第六NMOS管,其源极接地,栅极接信号输入端。本发明的优点是电压比较稳定,没有了漏极寄生电容充放电的问题,开关速度快,而且没有电荷分流的问题。同时解决了数字控制信号电荷注入的问题。(The edge sense circuit and edge conversion circuit of integrated Magnetic isolation chip, are related to integrated circuit technique.The present invention includes: the first PMOS tube, and source electrode connects with reference to high level, and drain electrode connects the source electrode of the second PMOS tube, and grid connects signal input part and the first output point；Second PMOS tube, drain electrode connect the second reference point, and grid connects grid and the drain electrode of third PMOS tube；Third PMOS tube, source electrode connect with reference to high level, and drain electrode is grounded by the first current source；4th NMOS tube, source electrode ground connection, grid and drain electrode connect the grid of the 5th NMOS tube, and drain electrode also connects the output end of the second current source；5th NMOS tube, source electrode connect the drain electrode of the 6th NMOS tube, and drain electrode connects the second output point, and drain electrode also passes through capacity earth；6th NMOS tube, source electrode ground connection, grid connect signal input part.It is an advantage of the invention that voltage is more stable, the problem of without drain parasitic capacitance charge and discharge, switching speed is fast, and the problem of shunt without charge.Solves the problems, such as the injection of digital controlled signal charge simultaneously.)

1. the edge sense circuit of integrated Magnetic isolation chip characterized by comprising

First PMOS tube (M1), source electrode connect with reference to high level, and drain electrode connects the source electrode of the second PMOS tube (M2), and it is defeated that grid connects signal Enter end and the first output point (N1)；

Second PMOS tube (M2), drain electrode connect the second reference point (N2), and grid connects grid and the drain electrode of third PMOS tube (M3)；

Third PMOS tube (M3), source electrode connect with reference to high level, and drain electrode is grounded by the first current source；

4th NMOS tube (M4), source electrode ground connection, grid and drain electrode connect the grid of the 5th NMOS tube, and drain electrode also connects the second current source Output end；

5th NMOS tube (M5), source electrode connect the drain electrode of the 6th NMOS tube (M6), and drain electrode connects the second output point (N2), and drain electrode is also It is grounded by capacitor (C2)；

6th NMOS tube (M6), source electrode ground connection, grid connect signal input part.

2. the edge conversion circuit of the edge sense circuit with integrated Magnetic isolation chip described in claim 1, feature exist In, the first input end of the first output point (N1) connection and door, the second input terminal of the second output point (N2) connection and door, Output end with the output end of door as rising edge short pulse.

3. edge conversion circuit as claimed in claim 2, which is characterized in that the first output point (N1) is concatenated non-by two The first input end of door connection and door, the second input terminal that the second output point (N2) passes through two concatenated NOT gate connections and door.

4. the edge conversion circuit of the edge sense circuit with integrated Magnetic isolation chip described in claim 1, feature exist In first output point (N1) connects the first input end of nor gate, and the second of the second output point (N2) connection nor gate is defeated Enter end, output end of the output end of nor gate as failing edge short pulse.

5. edge conversion circuit as claimed in claim 4, which is characterized in that the first output point (N1) is concatenated non-by two The first input end of door connection nor gate, the second output point (N2) connect the second input of nor gate by two concatenated NOT gates End.

Technical field

The present invention relates to integrated circuit techniques.

Background technique

The effect of isolator is that will respectively have independent function in circuit system in the occasions such as medical treatment, communication, industrial bus control The circuit module of energy is kept apart, and is avoided influencing each other between each functional module, is protected sensitive circuit not by dangerous voltage With the damage of electric current.Two ground are shown in figs. 2,3 and 4, i.e. gnd1 and gnd2, gnd1 and gnd2 may be at difference Potential.

The circuit isolating device largely used for a long time is optocoupler, but the optocoupler service life is short, data transmission Rate is low, performance is unstable, volume is excessive, and disadvantage is clearly.

The new isolation method of one kind occurred nearly ten years be use on piece integrated transformer as isolating device progress every From, that is, the isolation of magnetic coupling.On piece integrated transformer is processed on silicon wafer, is had between the former end-coil of transformer and secondary end-coil One layer of isolated material, to play buffer action.The isolation of magnetic coupling utilizes the law of electromagnetic induction, passes through the variation between two coils Magnetic field realizes the data communication on separation layer.The isolation of magnetic coupling has long service life, message transmission rate height, performance stabilization, body The advantages that product is small.

Fig. 1 (a) is the schematic diagram of such chip architecture, and DIE1, DIE2 and DIE3 are respectively encoder chip, decoding in figure Device chip and silicon substrate transformer chip, DIE1 and DIE2 are designed using conventional CMOS technology, and DIE3 uses independent research Manufacturing process.This three pieces of bare dies of DIE1, DIE2 and DIE3 are integrated in inside encapsulation, pass through packaging line progress between them Connection.

Since integrated magnetic coupling isolating device is small in size, winding inductance quantity is small, and former end-coil and secondary end-coil are in high band The coefficient of coup is higher, more conducively transmission signal, so generally to be encoded to the low-frequency square-wave signal of input, to its frequency into Row is promoted, so that it is transmitted by transformer.A kind of common method for promoting frequency is exactly to the square wave of input letter Number carry out edge detection, the rising edge and failing edge of square-wave signal are converted to the short arteries and veins that a duration was about two nanoseconds Punching after this pulse passes through transformer, then reverts to them the rising edge or failing edge of square wave.This method has one to ask Topic is how the problem of distinguishing rising edge and failing edge.Fig. 1 (b) is the flow chart of this encoding-decoding process.

Document [1] describes a kind of method for transmitting rising edge pulse and failing edge pulse respectively using two transformers, As shown in Figure 2.In this scenario, the rising edge and failing edge for inputting square wave are all converted to a pulse, then this Two pulses are transmitted with two different transformers respectively, and after transformer, the two pulses are extensive respectively again It is again rising edge and failing edge.The shortcomings that this way is exactly to need to use two transformers, wastes chip area.

Document [2] and document [3] describe a kind of double-pulse encoding scheme, as shown in Figure 3.In this scenario, rise Dipulse expression is continued to use, pulse expression is continued to use in decline.The shortcomings that this scheme be decoding circuit need to recognize dipulse and Pulse, dipulse influence whether transmission rate (the i.e. input side of data with needing a certain distance between pulse in this way There is certain distance between the rising edge and failing edge of wave signal, so that the frequency of square-wave signal cannot be too high).Meanwhile coding, Decoding circuit comparatively can be more complicated.

Through retrieving, the peak transfer rate of magnetic coupling isolated product is that (bps is bit per to 150Mbps currently on the market Second, i.e. bits per second are applied to non-return-to-zero signal, similarly hereinafter), i.e. 75MHz square wave frequency (see document [4]).

Bibliography:

[1]B.Chen,J.Wynne,and R.Lkiger,“High speed digital isolators using microscale on-chip transformers,”Elektronik Mag.,2003.

[2]B.Chen,“Fully integrated isolated DC-DC converter using microtransformers,”in Proc.23rd Annual IEEE Applied Power Electronics Conf., Feb.2008,pp.335–338.

[3]B.Chen,“Isolated half-bridge gate driver with integrated high-side supply,”in Proc.IEEE Power Electronics Specialists Conf.,Jun.2008,pp.3615– 3618.

[4] Digital-Isolator-Product-Selection-Guide.pdf,

http://www.analog.com/media/en/technical-documentation/product- selector-card/Digital-Isolator-Product-Selection-Guide.pdf

Summary of the invention

Pulse width caused by traditional edge sense circuit is influenced by integrated circuit fabrication process, voltage, temperature It is larger, affect the stability and reliability of isolator chip performance.For this problem, the invention proposes a kind of new sides Along detection circuit, pulse width can be greatly reduced to the dependence of integrated circuit fabrication process, voltage and temperature, improve pulse The stability of width, to improve the stability and reliability of isolator chip.

The present invention solve the technical problem the technical solution adopted is that, integrate Magnetic isolation chip edge sense circuit, It is characterised by comprising:

First PMOS tube, source electrode connect with reference to high level, and drain electrode connects the source electrode of the second PMOS tube, and grid connects signal input part With the first output point；

Second PMOS tube, drain electrode connect the second reference point, and grid connects grid and the drain electrode of third PMOS tube；

Third PMOS tube, source electrode connect with reference to high level, and drain electrode is grounded by the first current source；

4th NMOS tube, source electrode ground connection, grid and drain electrode connect the grid of the 5th NMOS tube, and drain electrode also connects the second current source Output end；

5th NMOS tube, source electrode connect the drain electrode of the 6th NMOS tube, and drain electrode connects the second output point, and drain electrode also passes through capacitor Ground connection；

6th NMOS tube, source electrode ground connection, grid connect signal input part.

The present invention also provides a kind of edge conversion circuit of edge sense circuit with aforementioned integrated Magnetic isolation chip, It is characterized in that, the first input end of the first output point connection and door, the second input terminal of the second output point connection and door, with Output end of the output end of door as rising edge short pulse.First output point passes through two concatenated NOT gate connections and the first of door Input terminal, the second output point connect the second input terminal with door by two concatenated NOT gates,

The present invention also provides a kind of edge conversion circuit of edge sense circuit with aforementioned integrated Magnetic isolation chip, It is characterized in that, the first input end of the first output point connection nor gate, the second output point connects the second input of nor gate End, output end of the output end of nor gate as failing edge short pulse.First output point by two concatenated NOT gates connections or The first input end of NOT gate, the second output point connect the second input terminal of nor gate by two concatenated NOT gates.

It is an advantage of the invention that voltage is more stable, the problem of without drain parasitic capacitance charge and discharge, switching speed is fast, And the problem of being shunted without charge.Solves the problems, such as the injection of digital controlled signal charge simultaneously.Capacitor is filled using electric current The stability for required time of discharging and the charge-discharge performance that source switch charge pump is excellent, source switch charge pump applications In edge sense circuit, duration relatively stable output pulse is realized.

The pulse width that the present invention generates is by integrated circuit fabrication process deviation, chip mains ripple and chip temperature The influence for spending variation is smaller, and the deviation of output pulse width is only 1/5th (only consideration temperature of traditional edge sense circuit Degree influences) to one third (while the influence for considering technique, voltage and temperature), isolator chip work can be substantially improved Stability and reliability.

Detailed description of the invention

Fig. 1 is the chip architecture and data transmission stream journey schematic diagram of circuit isolator, and wherein a is chip architecture signal Figure, b are data transmission stream journey figure.

Fig. 2 is the dual transformer coding and decoding scheme of positive pulse.

Fig. 3 is double-pulse coding and decoding scheme.

Fig. 4 is the schematic diagram of the rising edge conversion circuit of the prior art.

Fig. 5 is the schematic diagram of the failing edge conversion circuit of the prior art.

Fig. 6 is the circuit diagram of rising edge conversion circuit of the invention.

Fig. 7 is the circuit diagram of failing edge conversion circuit of the invention.

Fig. 8 is that input square wave rising edge detects timing diagram.

Specific embodiment

Existing edge sense circuit is to generate short pulse using the delay effect of digital logic gate, such as Fig. 4 and Fig. 5 institute Show, wherein Fig. 4 is used to detect the rising edge of input square wave, and Fig. 5 is used to detect the failing edge of input square wave.Input square-wave signal warp Two-way reaches and door or nor gate, directly reaches all the way, in addition passes through odd number phase inverter all the way, input square wave is prolonged When and reverse phase, finally and the output end of door obtain a short pulse corresponding with rising edge, obtained in the output end of nor gate One short pulse corresponding with failing edge.The duration of pulse depends on the delay time of delay circuit.The effect of capacitor is Increase the delay time of delay circuit.Be delayed using phase inverter, there have the shortcomings that be obvious, is exactly the delay of phase inverter by work Skill deviation, supply voltage variation and temperature change are affected, and are not easy to get fixed delay very much.

Referring to Fig. 6, when the first PMOS tube M1 (according to marking abbreviation M1 in figure, other devices similarly referred to as) is closed, M6 is beaten When opening, M2 provides constant electric current, charges to C2, and output end voltage rises；When M6, which closes M1, to be opened, M5 provides constant Electric current, discharge capacitor C2, output end voltage decline.

Fig. 6 is used to detect the rising edge of input square-wave signal, when rising edge temporarily, to export a short pulse；Fig. 7 is used for The failing edge of detection input square-wave signal, when failing edge temporarily, to export a short pulse.Now by taking Fig. 6 as an example, and combine figure 8 timing diagram, to illustrate the working principle of the circuit.The working principle of Fig. 7 can refer to Fig. 6, and difference is the gate circuit of latter end.

In Fig. 6, IB is a fixed bias current, is used for bias current mirror M2 and M3 and M4 and M5.When input square wave letter When number also in low level, M1 is closed, and M6 is opened, and current source M2 charges to capacitor C2 with constant electric current IB, capacitor C2 It is charged to supply voltage.When the rising edge of square-wave signal arrives, M1 is closed, and M6 is opened, and C2 is by M5 with constant electric current IB discharges, and the voltage on node N2 starts linear decline.When the voltage of N2 drops to the threshold voltage of phase inverter INV3, The voltage of INV3 overturning, N4 and then jumps (see Fig. 8).N4 is the delay and reverse phase for inputting square wave N1, and delay time is C2 from electricity Source tension discharge adds the delay of INV3 and INV4 to the threshold voltage required time of INV3；N3 is to input prolonging for square wave N1 Late, delay time is the delay that INV1 adds INV2.N3 and N4 is generated on one and input square wave finally by with door at N5 It rises along corresponding pulse.Since INV1 is equal to the delay that INV3 adds INV4 plus the delay of INV2, so this pulse is held The continuous time is only determined by the discharge time of C2.In order to improve the noise robustness of circuit, phase inverter INV1 and INV3 can also be used Schmidt trigger replaces.

Assuming that IB is invariable, with certain 0.5 micron of composite signal integrated circuits technique to Fig. 4's and Fig. 6 Circuit is emulated, and simulation result is shown in Table one and table two.Table one is not consider process deviation and voltage fluctuation, only considers temperature In the case where degree variation, obtained pulse width；Table two is while in view of integrated circuit fabrication process deviation, chip is powered In the case where voltage fluctuation and temperature change, obtained pulse width.In table one, simulated temperature range is -55 DEG C to 125 ℃；Table two be to circuit carry out full process corner emulation as a result, wherein resistance range be about ± 10%, capacitance variations range It is about ± 15% for ± 14%, NMOS and PMOS threshold voltage variation range, voltage change range is ± 10%, simulated temperature model Enclose is -55 DEG C to 125 DEG C.Pulsion phase in table is to deviation definition are as follows:

Table one: only consider the pulse width simulation result that temperature change obtains

Table two: while considering the pulse width simulation result that process deviation, voltage fluctuation and temperature change obtain

From the simulation result of table one and table two it is found that can be greatly reduced using the edge sense circuit of source switch charge pump Pulse width deviation.

Emulation in table one and table two has used constant bias current IB, and in actual circuit, bias current IB is same It will receive the influence of process deviation, voltage fluctuation and temperature change.Through consulting, if only consider that temperature influences, biased electrical The temperature coefficient of bias current caused by current circuit is only 30ppm/ DEG C or smaller (see document [4] and [5]), that is, It says, within the scope of -55 DEG C to 125 DEG C, bias current inaccuracies are only 0.5%, and the contribution of this deviation in Table 1 can be ignored Disregard.If simultaneously consider process deviation, voltage fluctuation and temperature change, the deviation of bias current also only 10% it Interior (see document [6] and [7]) can be modified the data in table two with this deviation.By edge sense circuit institute itself Caused pulse width variation and pulse width variation caused by bias current are irrelevant, inclined to 6 pulse widths by following formula Difference is modified:

Wherein Δ t is total deviation, Δ t₁For deviation caused by edge sense circuit itself, i.e., 25.8%, Δ t₂For biased electrical The deviation of stream, i.e., 10% obtain Δ t=27.7%, that is to say, that even if considering bias current inaccuracies, apply source electrode finally Pulse width deviation caused by the edge sense circuit of switch-charge pump is only the one third of traditional edge sense circuit.

Conclusion: using source switch charge pump as the delay circuit of edge sense circuit, output pulse width it is inclined Difference is only that 1/5th (only considering that temperature influences) of traditional edge sense circuit (while considering technique, electricity to one third The influence of pressure and temperature).