阅读说明：本技术 有源矩阵基板及其制造方法 (Active-matrix substrate and its manufacturing method ) 是由 上田辉幸 北川英树 大东彻 今井元 铃木正彦 西宫节治 菊池哲郎 伊藤俊克 原健吾 于 2018-03-19 设计创作，主要内容包括：有源矩阵基板的氧化物半导体TFT(201)具有：氧化物半导体层(107)；上部栅极电极(112),其隔着栅极绝缘层配置在氧化物半导体层的一部分上；以及源极电极(113)和漏极电极(114),氧化物半导体层(107)在从基板的法线方向观看时包含：第1部分(p1),其与上部栅极电极重叠；以及第2部分(p2),其位于第1部分与源极接触区域或漏极接触区域之间,栅极绝缘层未覆盖第2部分,上部栅极电极(112)具有包含与栅极绝缘层接触的合金层(112L)和配置在合金层上的金属层(112U)的层叠结构,金属层由第1金属元素M形成,合金层由包含第1金属元素M的合金形成,第1金属元素M是Cu、Mo或Cr。(The oxide semiconductor TFT (201) of active-matrix substrate includes oxide semiconductor layer (107)；Upper gate electrode (112), across gate insulating layer configuration in a part of oxide semiconductor layer；And source electrode (113) and drain electrode (114), oxide semiconductor layer (107) include when watching from the normal direction of substrate: part 1 (p1), it is Chong Die with upper gate electrode；And part 2 (p2), it is between part 1 and source contact regions or drain contact areas, gate insulating layer does not cover part 2, upper gate electrode (112) has the stepped construction of the metal layer (112U) of the alloy-layer (112L) comprising contacting with gate insulating layer and configuration over the alloyed layer, metal layer is formed by the 1st metallic element M, alloy-layer is formed by the alloy comprising the 1st metallic element M, and the 1st metallic element M is Cu, Mo or Cr.)

1. a kind of active-matrix substrate has substrate and is supported in the oxide semiconductor TFT of aforesaid substrate, which is characterized in that

Above-mentioned oxide semiconductor TFT is included

Oxide semiconductor layer, it includes: channel region；And source contact regions and drain contact areas, it is respectively configured In the two sides of above-mentioned channel region；

Upper gate electrode, across gate insulating layer configuration in a part of above-mentioned oxide semiconductor layer；And

The above-mentioned source contact regions of source electrode and drain electrode, above-mentioned source electrode and above-mentioned oxide semiconductor layer connect Touching, above-mentioned drain electrode are contacted with the above-mentioned drain contact areas of above-mentioned oxide semiconductor layer,

Above-mentioned oxide semiconductor layer includes when watching from the normal direction of aforesaid substrate: part 1, with above-mentioned top grid The overlapping of pole electrode；And part 2, it is located at above-mentioned part 1 and above-mentioned source contact regions or above-mentioned drain contact areas Between, above-mentioned gate insulating layer does not cover above-mentioned part 2,

Above-mentioned upper gate electrode has the alloy-layer comprising contacting with above-mentioned gate insulating layer and configuration on above-mentioned alloy-layer Metal layer stepped construction,

Above-mentioned metal layer is formed by the 1st metallic element M, and above-mentioned alloy-layer is formed by the alloy comprising above-mentioned 1st metallic element M, Above-mentioned 1st metallic element M is Cu, Mo or Cr.

2. active-matrix substrate according to claim 1,

Above-mentioned alloy is the alloy based on above-mentioned 1st metallic element M.

3. active-matrix substrate according to claim 1 or 2,

Above-mentioned alloy includes above-mentioned 1st metallic element M and the 2nd metallic element X,

Above-mentioned 1st metallic element M is Cu, and above-mentioned 2nd metallic element X is Mg, Al, Ca, Mo, Mn or Zr.

4. according to claim 1 to active-matrix substrate described in any one in 3,

Above-mentioned gate insulating layer with a thickness of 90nm or more 200nm or less.

5. according to claim 1 to active-matrix substrate described in any one in 4,

At least the above part 1 and above-mentioned part 2 in above-mentioned oxide semiconductor layer include concentration relative to oxide half Conductor is more than 0 atom % and 0.5 atom % above-mentioned 1st metallic element M below.

6. according to claim 1 to active-matrix substrate described in any one in 5,

It is also equipped with:

Bottom gate electrode configures between above-mentioned oxide semiconductor layer and aforesaid substrate；And

Lower insulation layer configures between above-mentioned bottom gate electrode and above-mentioned oxide semiconductor layer,

When being watched from the normal direction of aforesaid substrate, the above-mentioned channel region of above-mentioned oxide semiconductor layer and above-mentioned top grid At least one party's overlapping in pole electrode and above-mentioned bottom gate electrode,

From the normal direction of aforesaid substrate watch when, above-mentioned oxide semiconductor layer have be located at above-mentioned channel region with it is above-mentioned Offset area between source contact regions or above-mentioned drain contact areas, above-mentioned offset area include above-mentioned part 2 extremely Few a part.

7. active-matrix substrate according to claim 6,

From the normal direction of aforesaid substrate watch when, a part of the above-mentioned part 2 of above-mentioned oxide semiconductor layer with it is upper State the overlapping of bottom gate electrode.

8. a kind of active-matrix substrate has substrate and is supported in the oxide semiconductor TFT and crystalline silicon half of aforesaid substrate Conductor TFT, which is characterized in that

Display area is included, is provided by being arranged as rectangular multiple pixel regions；And neighboring area, it is located at above-mentioned The periphery of display area, each of above-mentioned multiple pixel regions pixel region includes above-mentioned oxide semiconductor TFT, above-mentioned Neighboring area includes above-mentioned crystalline silicon semiconductor TFT,

Above-mentioned crystalline silicon semiconductor TFT is included

Crystalline silicon semiconductor layer, it includes: the 1st channel region；And the 1st source contact regions and the 1st drain contact areas, Its two sides for being arranged respectively at above-mentioned 1st channel region；

1st gate electrode, across the configuration of the 1st gate insulating layer in above-mentioned crystalline silicon semiconductor layer；And

1st source electrode and the 1st drain electrode, above-mentioned 1st source of above-mentioned 1st source electrode and above-mentioned crystalline silicon semiconductor layer The contact of pole contact area, above-mentioned 1st drain electrode and above-mentioned 1st drain contact areas of above-mentioned crystalline silicon semiconductor layer connect Touching,

Above-mentioned oxide semiconductor TFT is included

Oxide semiconductor layer, it includes: the 2nd channel region；And the 2nd source contact regions and the 2nd drain contact areas, It is arranged respectively at the two sides of above-mentioned 2nd channel region；

2nd gate electrode, across the configuration of the 2nd gate insulating layer in a part of above-mentioned oxide semiconductor layer；And

2nd source electrode and the 2nd drain electrode, above-mentioned 2nd source electrode of above-mentioned 2nd source electrode and above-mentioned oxide semiconductor layer Contact area contact, above-mentioned 2nd drain electrode are contacted with above-mentioned 2nd drain contact areas of above-mentioned oxide semiconductor layer,

Above-mentioned crystalline silicon semiconductor layer includes when watching from the normal direction of aforesaid substrate: third portion, with the above-mentioned 1st Gate electrode overlapping；And the 4th part, it is located at above-mentioned third portion and above-mentioned 1st source contact regions or above-mentioned 1st drain electrode Between contact area, above-mentioned 1st gate insulating layer covers at least the above third portion of above-mentioned crystalline silicon semiconductor layer and above-mentioned 4th part,

Above-mentioned oxide semiconductor layer includes when watching from the normal direction of aforesaid substrate: part 1, with above-mentioned 2nd grid The overlapping of pole electrode；And part 2, it is located at above-mentioned part 1 and is connect with above-mentioned 2nd source contact regions or above-mentioned 2nd drain electrode It touching between region, above-mentioned 2nd gate insulating layer covers above-mentioned part 1 and does not cover above-mentioned part 2,

Above-mentioned 2nd gate electrode has the alloy-layer comprising contacting with above-mentioned 2nd gate insulating layer and configuration in above-mentioned alloy-layer On metal layer stepped construction, above-mentioned metal layer formed by the 1st metallic element M, and above-mentioned alloy-layer is by including above-mentioned 1st metal The alloy of element M is formed, and above-mentioned 1st metallic element M is Cu, Mo or Cr.

9. active-matrix substrate according to claim 8,

Above-mentioned 1st gate electrode has stepped construction identical with above-mentioned 2nd gate electrode.

10. according to claim 1 to active-matrix substrate described in any one in 9,

Above-mentioned oxide semiconductor layer includes In-Ga-Zn-O based semiconductor.

11. active-matrix substrate according to claim 10,

Above-mentioned oxide semiconductor layer includes crystalline part.

12. according to claim 1 to active-matrix substrate described in any one in 11,

Above-mentioned oxide semiconductor layer has stepped construction.

13. a kind of manufacturing method of active-matrix substrate is the manufacturer for having the active-matrix substrate of oxide semiconductor TFT Method, characterized by comprising:

The process of oxide semiconductor layer is formed on substrate；

The process of gate insulating layer is formed in a manner of covering above-mentioned oxide semiconductor layer；

It is formed in a manner of being contacted with the upper surface of above-mentioned gate insulating layer comprising the 1st metallic element on above-mentioned gate insulating layer The alloy film of M then forms the metal film formed by above-mentioned 1st metallic element M on above-mentioned alloy film, so that formation includes The process of the grid conductive film of above-mentioned alloy film and above-mentioned metal film；

Resist layer is formed in a part of above-mentioned grid conductive film, carries out above-mentioned grid for above-mentioned resist layer as mask The patterning of pole conductive film, thus the process for forming upper gate electrode；

The etching that above-mentioned gate insulating layer is carried out using above-mentioned resist layer and above-mentioned upper gate electrode as mask, to make State the process that a part of oxide semiconductor layer is exposed；

Using anticorrosive additive stripping liquid controlling by above-mentioned resist layer from above-mentioned upper gate stripping electrode, and remove above-mentioned resist Liquid is contacted with the part of the exposing of above-mentioned oxide semiconductor layer, to make the be dissolved in above-mentioned anticorrosive additive stripping liquid controlling the above-mentioned 1st The process that metallic element M is mixed into above-mentioned oxide semiconductor layer；And

Form the interlayer insulating film for covering above-mentioned oxide semiconductor layer, above-mentioned gate insulating layer and above-mentioned upper gate electrode Process.

14. the manufacturing method of active-matrix substrate according to claim 13,

Above-mentioned oxide semiconductor layer includes In-Ga-Zn-O based semiconductor.

15. the manufacturing method of active-matrix substrate according to claim 14,

Above-mentioned oxide semiconductor layer includes crystalline part.

16. the manufacturing method of active-matrix substrate described in any one in 3 to 15 according to claim 1,

Above-mentioned oxide semiconductor layer has stepped construction.

Technical field

The present invention relates to active-matrix substrates, more particularly to the active-matrix substrate for having oxide semiconductor TFT.

Background technique

Active-matrix substrate used in liquid crystal display device etc. has thin film transistor (TFT) (Thin Film by each pixel Transistor；The following are " TFT ") etc. switch elements.As this switch element, it is widely used back and forth with amorphous silicon Film is the TFT (the following are " non-crystalline silicon tfts ") of active layer or (the following are " polysilicons using polysilicon film as the TFT of active layer TFT”)。

In recent years, it has been suggested that use oxide semiconductor as the material of the active layer of TFT instead of amorphous silicon, polysilicon Material.It is known as " oxide semiconductor TFT " as the TFT of active layer for oxide semiconductor film.Patent document 1 discloses The active layer of TFT uses the active-matrix substrate of the semiconductor film of In-Ga-Zn-O system.

Oxide semiconductor has the mobility higher than amorphous silicon.Therefore, oxide semiconductor TFT can compare non-crystalline silicon tft It acts at high speed.In addition, oxide semiconductor film is formed with the technique than polysilicon film simplicity, therefore can also apply to need The device of large area.

Active-matrix substrate generally has display area and neighboring area.Display area include be arranged as it is rectangular multiple Pixel (pixel region), also referred to as active region.Neighboring area is located at the periphery of display area, also referred to as frame region.

The TFT formed by each pixel is provided in display area；It is electrically connected respectively to gate electrode, the source electrode of TFT The grid bus of electrode and drain electrode, source bus line and pixel electrode.

Configured with the drive for driving grid bus (scan wiring) and source bus line (signal wiring) in neighboring area Dynamic circuit.Specifically, configuring the gate drivers of oriented grid bus supply grid signal (scanning signal), being used for source electrode Bus supplies the source electrode driver of source signal (display signal).The driving circuits such as gate drivers, source electrode driver sometimes by It (is installed in a manner of COG (Chip On Glass: chip on glass)) as semiconductor-chip-mounting, sometimes monolithic (one) It is formed in active-matrix substrate.The driving circuit being monolithically formed is known as " driver monolithic circuit ".Driver monolithic circuit It is constituted usually using TFT.

In the specification of the present application, the TFT in each pixel of display area as switch element configuration is known as " pixel The TFT for constituting the peripheral circuits such as driving circuit is known as " circuit TFT " by TFT ".

Oxide semiconductor TFT usually has bottom grating structure (such as patent document 1), but also has top-gated knot sometimes Structure.Such as patent document 2 discloses the top (side opposite with substrate) in oxide semiconductor layer across gate insulating film The oxide semiconductor TFT of top gate structure configured with gate electrode.It is proposed in patent document 2 using gate electrode as covering The patterning (self-registered technology) of mould progress gate insulating film.

Summary of the invention

Problems to be solved by the invention

However, present inventor it has been investigated that, such as with the oxidation of top gate structure disclosed in the patent document 2 In object semiconductor TFT, the electric current (cut-off leakage current) that TFT flows between source drain when ending becomes larger, it is possible to cannot obtain Stable characteristic.It is described in detail later.

The present invention is to complete in view of the above problems, and its purpose is to provide have the oxidation that can reduce cut-off leakage current The active-matrix substrate of object semiconductor TFT.

The solution to the problem

The active-matrix substrate of one embodiment of the present invention has substrate partly leads with the oxide for being supported in aforesaid substrate Body TFT, in above-mentioned active-matrix substrate, above-mentioned oxide semiconductor TFT includes oxide semiconductor layer, it includes: channel Region；And source contact regions and drain contact areas, it is arranged respectively at the two sides of above-mentioned channel region；Upper gate electricity Pole, across gate insulating layer configuration in a part of above-mentioned oxide semiconductor layer；And source electrode and drain electrode, Above-mentioned source electrode is contacted with the above-mentioned source contact regions of above-mentioned oxide semiconductor layer, above-mentioned drain electrode and above-mentioned oxidation The above-mentioned drain contact areas of object semiconductor layer contacts, and above-mentioned oxide semiconductor layer is watched from the normal direction of aforesaid substrate When include: part 1, it is Chong Die with above-mentioned upper gate electrode；And part 2, it is located at above-mentioned part 1 and above-mentioned source Between pole contact area or above-mentioned drain contact areas, above-mentioned gate insulating layer does not cover above-mentioned part 2, above-mentioned upper gate Electrode has the alloy-layer comprising contacting with above-mentioned gate insulating layer and configures the stacking knot of the metal layer on above-mentioned alloy-layer Structure, above-mentioned metal layer are formed by the 1st metallic element M, and above-mentioned alloy-layer is formed by the alloy comprising above-mentioned 1st metallic element M, on Stating the 1st metallic element M is Cu, Mo or Cr.

It is also possible to above-mentioned alloy and is the alloy based on above-mentioned 1st metallic element M.

Being also possible to above-mentioned alloy includes above-mentioned 1st metallic element M and the 2nd metallic element X, above-mentioned 1st metallic element M It is Cu, above-mentioned 2nd metallic element X is Mg, Al, Ca, Mo, Mn or Zr.

Be also possible to above-mentioned gate insulating layer with a thickness of 90nm or more 200nm or less.

At least the above part 1 and above-mentioned part 2 being also possible in above-mentioned oxide semiconductor layer include concentration phase It is more than 0 atom % and 0.5 atom % above-mentioned 1st metallic element M below for oxide semiconductor.

In certain embodiment, above-mentioned active-matrix substrate is also equipped with: bottom gate electrode, is configured in above-mentioned oxide Between semiconductor layer and aforesaid substrate；And lower insulation layer, configuration is in above-mentioned bottom gate electrode and above-mentioned oxide half Between conductor layer, from the normal direction of aforesaid substrate watch when, the above-mentioned channel region of above-mentioned oxide semiconductor layer with it is upper At least one party's overlapping in upper gate electrode and above-mentioned bottom gate electrode is stated, is watched from the normal direction of aforesaid substrate When, above-mentioned oxide semiconductor layer, which has, is located at above-mentioned channel region and above-mentioned source contact regions or above-mentioned drain contact areas Between offset area, above-mentioned offset area include above-mentioned part 2 at least part.

In certain embodiment, from the normal direction of aforesaid substrate watch when, above-mentioned oxide semiconductor layer it is above-mentioned A part of part 2 is Chong Die with above-mentioned bottom gate electrode.

The active-matrix substrate of another embodiment of the present invention has substrate and is supported in the oxide half of aforesaid substrate Conductor TFT and crystalline silicon semiconductor TFT, in above-mentioned active-matrix substrate, comprising: display area, by being arranged as matrix Multiple pixel regions of shape provide；And neighboring area, in the periphery of above-mentioned display area, above-mentioned multiple pixel regions Each pixel region include above-mentioned oxide semiconductor TFT, above-mentioned neighboring area include above-mentioned crystalline silicon semiconductor TFT, above-mentioned crystalline silicon semiconductor TFT include crystalline silicon semiconductor layer, it includes: the 1st channel region；And the 1st source electrode Contact area and the 1st drain contact areas are arranged respectively at the two sides of above-mentioned 1st channel region；1st gate electrode, every The 1st gate insulating layer configuration in above-mentioned crystalline silicon semiconductor layer；And the 1st source electrode and the 1st drain electrode, it is above-mentioned 1st source electrode is contacted with above-mentioned 1st source contact regions of above-mentioned crystalline silicon semiconductor layer, above-mentioned 1st drain electrode with Above-mentioned 1st drain contact areas of above-mentioned crystalline silicon semiconductor layer contacts, and above-mentioned oxide semiconductor TFT includes oxide Semiconductor layer, it includes: the 2nd channel region；And the 2nd source contact regions and the 2nd drain contact areas, it is arranged respectively at The two sides of above-mentioned 2nd channel region；2nd gate electrode is configured across the 2nd gate insulating layer in above-mentioned oxide semiconductor layer A part on；And the 2nd source electrode and the 2nd drain electrode, above-mentioned 2nd source electrode and above-mentioned oxide semiconductor layer Above-mentioned 2nd source contact regions contact, above-mentioned 2nd drain contact of above-mentioned 2nd drain electrode and above-mentioned oxide semiconductor layer Region contact, above-mentioned crystalline silicon semiconductor layer include when watching from the normal direction of aforesaid substrate: third portion, and upper State the overlapping of the 1st gate electrode；And the 4th part, it is located at above-mentioned third portion and above-mentioned 1st source contact regions or the above-mentioned 1st Between drain contact areas, above-mentioned 1st gate insulating layer cover above-mentioned crystalline silicon semiconductor layer at least the above third portion and Above-mentioned 4th part, above-mentioned oxide semiconductor layer include when watching from the normal direction of aforesaid substrate: part 1, and upper State the overlapping of the 2nd gate electrode；And part 2, it is located at above-mentioned part 1 and above-mentioned 2nd source contact regions or the above-mentioned 2nd Between drain contact areas, above-mentioned 2nd gate insulating layer covers above-mentioned part 1 and does not cover above-mentioned part 2, and above-mentioned the 2 gate electrodes have the alloy-layer comprising contacting with above-mentioned 2nd gate insulating layer and configure the metal layer on above-mentioned alloy-layer Stepped construction, above-mentioned metal layer formed by the 1st metallic element M, and above-mentioned alloy-layer is by the conjunction comprising above-mentioned 1st metallic element M Gold is formed, and above-mentioned 1st metallic element M is Cu, Mo or Cr.

It is also possible to above-mentioned alloy and is the alloy based on above-mentioned 1st metallic element M.

It is also possible to above-mentioned 1st gate electrode with stepped construction identical with above-mentioned 2nd gate electrode.

Being also possible to above-mentioned oxide semiconductor layer includes In-Ga-Zn-O based semiconductor.

Being also possible to above-mentioned oxide semiconductor layer includes crystalline part.

It is also possible to above-mentioned oxide semiconductor layer with stepped construction.

The manufacturing method of the active-matrix substrate of one embodiment of the present invention is have oxide semiconductor TFT active The manufacturing method of matrix base plate includes: the process of oxide semiconductor layer is formed on substrate；It is partly led with covering above-mentioned oxide The process that the mode of body layer forms gate insulating layer；It is connect on above-mentioned gate insulating layer with the upper surface with above-mentioned gate insulating layer The mode of touching forms the alloy film comprising the 1st metallic element M, then, is formed on above-mentioned alloy film by above-mentioned 1st metallic element The metal film that M is formed, thus the process for forming the grid conductive film comprising above-mentioned alloy film and above-mentioned metal film；In above-mentioned grid Resist layer is formed in a part of pole conductive film, carries out above-mentioned grid conductive film for above-mentioned resist layer as mask Patterning, thus the process for forming upper gate electrode；Using above-mentioned resist layer and above-mentioned upper gate electrode as mask into The etching of the above-mentioned gate insulating layer of row, thus the process for exposing a part of above-mentioned oxide semiconductor layer；Use resist Above-mentioned resist layer from above-mentioned upper gate stripping electrode, and is made above-mentioned anticorrosive additive stripping liquid controlling and above-mentioned oxide by stripper The part of the exposing of semiconductor layer contacts, so that the above-mentioned 1st metallic element M for being dissolved in above-mentioned anticorrosive additive stripping liquid controlling be made to be mixed into The process of above-mentioned oxide semiconductor layer；And formed cover above-mentioned oxide semiconductor layer, above-mentioned gate insulating layer and on The process for stating the interlayer insulating film of upper gate electrode.

It is also possible to above-mentioned alloy film and is the alloy film based on above-mentioned 1st metallic element M.

Being also possible to above-mentioned oxide semiconductor layer includes In-Ga-Zn-O based semiconductor.

Being also possible to above-mentioned oxide semiconductor layer includes crystalline part.

It is also possible to above-mentioned oxide semiconductor layer with stepped construction.

Invention effect

Embodiment according to the present invention can provide the oxide semiconductor for having and capable of further decreasing cut-off leakage current The active-matrix substrate of TFT.

Detailed description of the invention

(a) and (b) of Fig. 1 is the sectional view and top view of the oxide semiconductor TFT201 of illustrated embodiment 1 respectively.

(a) and (b) of Fig. 2 is the oxide semiconductor TFT201 and existing oxide half for showing embodiment 1 respectively The sectional view of a part of conductor TFT900.

Fig. 3 A is the sectional view for showing another oxide semiconductor TFT202 of embodiment 1.

(a) and (b) of Fig. 3 B is the section for showing another oxide semiconductor TFT203 in embodiment 1,204 respectively Figure.

(a) and (b) of Fig. 4 is to show the sectional view of the another oxide semiconductor TFT205 of embodiment 1 and bow respectively View.

(a) of Fig. 5~(d) is namely for illustrating the process of the manufacturing method of the oxide semiconductor TFT of embodiment 1 Sectional view.

(a) of Fig. 6~(c) is namely for illustrating the process of the manufacturing method of the oxide semiconductor TFT of embodiment 1 Sectional view.

Fig. 7 is the top view for schematically showing the active-matrix substrate 100 of embodiments of the present invention.

Fig. 8 is the sectional view for schematically showing active-matrix substrate 100, and left side shows the electricity for being set to neighboring area FR Road TFT, right side show the pixel TFT for being set to display area DR.

Fig. 9 is the top view for schematically showing active-matrix substrate 100, shows 1 pixel region P.

Figure 10 is the sectional view for showing the active-matrix substrate 900 of comparative example.

(a) of Figure 11~(d) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 100.

(a) of Figure 12~(d) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 100.

(a) of Figure 13~(c) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 100.

(a) and (b) of Figure 14 is the process sectional view for illustrating the manufacturing method of active-matrix substrate 100.

(a) and (b) of Figure 15 is the process sectional view for illustrating the manufacturing method of active-matrix substrate 100.

Figure 16 is the sectional view for schematically showing the active-matrix substrate 200 of embodiments of the present invention.

(a) of Figure 17~(d) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 200.

(a) of Figure 18~(c) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 200.

(a) of Figure 19~(c) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 200.

Figure 20 is the sectional view for schematically showing the active-matrix substrate 300 of embodiments of the present invention.

(a) of Figure 21~(d) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 300.

(a) of Figure 22~(c) is the process sectional view for illustrating the manufacturing method of active-matrix substrate 300.

(a) and (b) of Figure 23 is the process sectional view for illustrating the manufacturing method of active-matrix substrate 300.

Figure 24 is to illustrate the top view for the peripheral circuit that active-matrix substrate 100,200 and 300 has.

Specific embodiment

As previously mentioned, in the existing oxide semiconductor TFT with top gate structure disclosed in such as patent document 2, There are problems that cut-off leakage current becomes larger.Therefore, use the oxide semiconductor TFT with top gate structure as such as sometimes Plain TFT is difficult.

An important factor for present inventor becomes larger to cut-off leakage current study and has obtained following discovery.In In TFT structure disclosed in patent document 2, source electrode and drain electrode are (to claim with a part of oxide semiconductor layer respectively For " source contact regions " and " drain contact areas ") contact.Between source contact regions and drain contact areas, in oxygen Gate electrode (also referred to as upper gate electrode or top-gated) is configured with across gate insulating film on compound semiconductor layer.In patent text It offers in 2, gate insulating film is formed self-aligned using upper gate electrode as mask.In this configuration, in order to avoid Conducting between source/drain-grid is deposited in the source contact regions in oxide semiconductor layer and between drain contact areas In the part for both not covered by gate electrode or not covered by gate insulating film.Speculate that the part in a manufacturing process can be by low electricity Resistanceization, as a result, cut-off leakage current becomes larger.

It is furthermore conceivable that even if in the case where having the double-gate structure of both top-gated and bottom gate, it is also possible to It can lead to the problem of same.

In the present specification, when being watched from the normal direction of substrate, by oxide semiconductor layer and upper gate The part of electrode overlapping is known as " part 1 ", will between part 1 and source contact regions or drain contact areas and not " part 2 " is known as by the part that upper gate electrode and gate insulating film cover.

In the oxide semiconductor TFT with above-mentioned structure, in order to reduce cut-off leakage current, it is desirable that inhibit oxide The low resistance of the part 2 of semiconductor layer.

In this regard, present inventor is conceived to the oxide semiconductor when oxide semiconductor is mixed into the metals such as Cu Resistance can get higher this point, and find that the metals such as the Cu for being included using upper gate electrode can inhibit oxide semiconductor layer Low resistance.According to an embodiment of the present invention, oxide half is deliberately mixed by the metal for being included by gate electrode Conductor layer, can be by the part 1 high resistance of oxide semiconductor layer and/or the low resistance of inhibition part 2.Its result It is that can reduce cut-off leakage current, is able to achieve desired TFT characteristic.

Hereinafter, being described with reference to embodiments of the present invention.The active-matrix substrate of embodiments of the present invention is extensive Applied to various display devices, electronic equipment etc..Additionally, this invention is not limited to the following embodiments and the accompanying drawings.

(embodiment 1)