阅读说明：本技术 核脉冲电荷时间转换方法与系统 (Core pulse charge time translation method and system ) 是由 王永纲 宋政奇 孔晓光 于 2019-06-03 设计创作，主要内容包括：本发明公开了一种核脉冲电荷时间转换系统与方法,其系统包括：积分电路、电压比较器、数字信号延时器、FPGA管脚、时间数字变换器和一个校正表。本发明具有结构简单、基线稳定、测量精度高、测量死时间小等优点,在核信号处理与核技术应用领域有重要应用价值。(The invention discloses a kind of core pulse charge time converting system and method, system includes: integrating circuit, voltage comparator, digital signal delayer, FPGA pin, time-digital converter and a checking list.The present invention has many advantages, such as that structure is simple, baseline stability, measurement accuracy are high, the measurement dead time is small, has significant application value in Nuclear signal processing and Application of Nuclear Technology field.)

1. a kind of core pulse charge time converting system characterized by comprising integrating circuit (1), voltage comparator (2), number Word signal delayer (5), FPGA pin (7), time-digital converter (3) and a checking list (4), wherein

The integrating circuit (1) is for receiving core pulse current signal and output voltage signal；

The voltage comparator (2) is used for by the voltage signal compared with a preset threshold voltage, and according to comparison result Realize the level overturning of its output signal, wherein the preset threshold voltage is less than the described of the integrating circuit (1) output The peak value of voltage signal；

The digital signal delayer (5) is used to overturn output control according to the level of the voltage comparator (2) output signal Signal, the control signal include opening discharge control signal and electric discharge stopping control signal, wherein the unlatching control of discharge It is exported again after signal delay, the electric discharge stops controlling signal and is not delayed direct output；

The FPGA pin (7) is used for the voltage signal and the digital signal delayer exported in the voltage comparator (2) (5) it is discharged with constant electric current under control the integrating circuit (1)；

The time-digital converter (3) is defeated at the time of being used to be overturn according to the level of the voltage comparator (2) output signal Timestamp out；

The checking list (4) is used to obtain the charge value of core pulse according to the timestamp.

2. core pulse charge time converting system as described in claim 1, which is characterized in that further include:

Discharge resistance (6), between the integrating circuit (1) and the FPGA pin (7), for controlling the discharge current Size.

3. core pulse charge time converting system as described in claim 1, which is characterized in that the integrating circuit (1) includes Operational amplifier and integrating circuit, wherein the integrating circuit is separately connected negative input end and the output of the operational amplifier End.

4. core pulse charge time converting system as claimed in claim 3, which is characterized in that the integrating circuit includes integral Capacitor and integrating resistor, and the integrating capacitor and integrating resistor are connected in parallel to the operational amplifier.

5. core pulse charge time converting system as claimed in claim 4, which is characterized in that the checking list content are as follows:

Wherein, K is the quantity of electric charge of the core pulse；i₀It is the current value of FPGA pin (7) electric discharge；T is two times The difference of stamp；T_dIt is the amount of delay of the digital signal delayer (5)；U₁It (T) is that the core pulse passes through the integrating circuit (1) normalization waveform of the integrated signal exported；R is the resistance value of the integrating resistor；C is the capacitor of the integrating capacitor Value.

6. core pulse charge time converting system as described in claim 1, which is characterized in that the voltage comparator (2), FPGA pin (7), digital signal delayer (5) and time-digital converter (3) are integrated on a piece of fpga chip；Wherein, The voltage comparator (2) realizes that time-digital converter (3) is realized inside FPGA by the LVDS differential receiver of FPGA, The checking list (4) is realized using embedded memory inside FPGA or is realized outside FPGA.

7. a kind of core pulse charge time translation method characterized by comprising

Integrating circuit (1) receives core pulse current signal, and generates voltage signal in output end；

Voltage comparator (2) by the voltage signal compared with a preset threshold voltage less than the voltage signal peak value, When the voltage signal is more than the threshold voltage, the output signal progress first time level of the voltage comparator (2) is turned over Turn；

Time-digital converter (3) exports at the time of overturning according to the first time level of the voltage comparator (2) output signal It stabs at the first time；

Digital signal delayer (5) is flipped open electric discharge according to the first time level of the output signal of the voltage comparator (2) It is exported after control signal and delay；

FPGA pin (7) under the control of the voltage comparator (2) output signal and the digital signal delayer (5), It is discharged with constant electric current the integrating circuit (1)；

When deteriorating to less than the threshold voltage by the voltage signal that discharges, the output signal of the voltage comparator (2) Carry out second of level overturning；

Time-digital converter (3) exports at the time of overturning according to second of level of the voltage comparator (2) output signal Second timestamp；

Checking list (4) obtains the charge value of the core pulse with the second timestamp according to first time stamp.

8. core pulse charge time translation method as claimed in claim 7, which is characterized in that the first time level, which is overturn, is Low level overturning is high level；It is low level that second of level overturning, which is high level overturning,.

9. core pulse charge time translation method as claimed in claim 7, which is characterized in that the integrating circuit (1) receives Before core pulse current signal further include: adjust discharge resistance (6) size to control the discharge current size.

10. such as the described in any item core pulse charge time translation methods of claim 7-9, which is characterized in that the checking list (4) include: according to the charge value that first time stamp obtains the core pulse with the second timestamp

Using first time stamp and the difference of the second time as input；

The charge value of the pulse is calculated according to the difference and the checking list (4)；

The checking list are as follows:

Wherein, K is the quantity of electric charge of the core pulse；i₀It is the current value of FPGA pin (7) electric discharge；T is two times The difference of stamp；T_dIt is the amount of delay of the digital signal delayer (5)；U₁It (T) is that the core pulse passes through the integrating circuit (1) normalization waveform of the integrated signal exported；R is the resistance value of the integrating resistor；C is the capacitor of the integrating capacitor Value.

Technical field

The invention belongs to nuclear signal fields of measurement, it is related to a kind of core pulse charge time translation method and system.

Background technique

General nuclear detector exports a current pulse signal after detecting an incoming particle.The current impulse with The integral of time is exactly charge caused by incoming particle acts on the detector, it is equal to the energy of incoming particle.Measurement The charge of core pulse is the basic task in Nuclear signal processing field.Traditionally, the measurement of energy is that current signal is given to one Charge integrating circuit exports as integrated signal, with analog digital converter (ADC) sampled signal waveform, the maximum value of sampled point It is exactly the energy value of core pulse.With the development of nuclear detector technology, port number contained by a detector is more and more, each The energy measuring method of a high-speed ADC sample waveform is all used in a channel, and measurement electronics scale can be made increasing.By core The quantity of electric charge that signal is included is converted to time quantum, and charge measurement is realized by time quantum measurement, is current Nuclear signal processing One major technique developing direction in field.However, existing charge time converted measurement technology, has measurement accuracy low, electricity The disadvantages of road is complicated, and the measurement dead time is long, is not able to satisfy multichannel, high integration, the demand of high measurement performance.How using most Simplified circuit realizes high performance charge measurement, becomes technical problem urgently to be solved.

Summary of the invention

(1) technical problems to be solved

In view of the above technical problem, the present invention provides a kind of core pulse charge time translation method and systems, at least Part solves above-mentioned technical problem.

(2) technical solution

According to an aspect of the present invention, a kind of core pulse charge time converting system is provided, comprising: integrating circuit, voltage Comparator, digital signal delayer, FPGA pin, time-digital converter and a checking list, wherein

The integrating circuit is for receiving core pulse current signal and output voltage signal；

The voltage comparator is used for by the voltage signal compared with a preset threshold voltage, and according to comparison result Realize the level overturning of its output signal, wherein the preset threshold voltage is less than the electricity of integrating circuit output Press the peak value of signal；

The digital signal delayer is used to overturn output control letter according to the level of the voltage comparator output signal Number, the control signal includes opening discharge control signal and electric discharge stopping control signal, wherein the unlatching control of discharge letter It is exported again after number delay, the electric discharge stops controlling signal and is not delayed direct output；

Voltage signal and the digital signal delayer of the FPGA pin for being exported in the voltage comparator It is discharged with constant electric current under control the integrating circuit；

The time-digital converter is used to export at the time of overturning according to the level of the voltage comparator output signal Timestamp；

The checking list is used to obtain the charge value of core pulse according to the timestamp.

In a further embodiment, the core pulse charge time converting system further include:

Discharge resistance, between the integrating circuit and the FPGA pin, for controlling the discharge current size.

In a further embodiment, the integrating circuit includes operational amplifier and integrating circuit, wherein the product Subnetwork is separately connected the negative input end and output end of the operational amplifier.

In a further embodiment, the integrating circuit includes integrating capacitor and integrating resistor, and the integral is electric Hold and integrating resistor is connected in parallel to the operational amplifier.

In a further embodiment, the checking list content are as follows:

Wherein, K is the quantity of electric charge of the core pulse；i₀It is the current value of the FPGA pin electric discharge；T is described in two The difference of timestamp；T_dIt is the amount of delay of the digital signal delayer；U₁It (T) is that the core pulse passes through the integrating circuit The normalization waveform of the integrated signal of output；R is the resistance value of the integrating resistor；C is the capacitance of the integrating capacitor.

In a further embodiment, the voltage comparator, FPGA pin, digital signal delayer and time number Word converter is integrated on a piece of fpga chip；Wherein, the voltage comparator is realized by the LVDS differential receiver of FPGA, when Between digitalizer realized inside FPGA, the checking list realized inside FPGA using embedded memory or outside FPGA it is real It is existing.

According to another aspect of the present invention, a kind of core pulse charge time translation method is provided, comprising:

Integrating circuit receives core pulse current signal, and generates voltage signal in output end；

Voltage comparator by the voltage signal compared with a preset threshold voltage less than the voltage signal peak value, When the voltage signal is more than the threshold voltage, the output signal of the voltage comparator carries out the overturning of first time level；

Time-digital converter exports the at the time of overturning according to the first time level of the voltage comparator output signal One timestamp；

Digital signal delayer is flipped open to discharge according to the first time level of the output signal of the voltage comparator and control It is exported after signal processed and delay；

FPGA pin is under the control of the voltage comparator output signal and the digital signal delayer, to described Integrating circuit is discharged with constant electric current；

When deteriorating to less than the threshold voltage by the voltage signal that discharges, the output signal of the voltage comparator Carry out second of level overturning；

Time-digital converter exports the at the time of overturning according to second of level of the voltage comparator output signal Two timestamps；

Checking list obtains the charge value of the core pulse with the second timestamp according to first time stamp.

In a further embodiment, it is high level that the first time level overturning, which is low level overturning,；Described second It is low level that secondary level overturning, which is high level overturning,.

In a further embodiment, before the integrating circuit reception core pulse current signal further include: adjusting is put Electric resistance sizes are to control the discharge current size.

In a further embodiment, the checking list is obtained according to first time stamp with the second timestamp described The charge value of core pulse includes:

Using first time stamp and the difference of the second time as input；

The charge value of the pulse is calculated according to the difference and the checking list；

The checking list are as follows:

Wherein, K is the quantity of electric charge of the core pulse；i₀It is the current value of the FPGA pin electric discharge；T is described in two The difference of timestamp；T_dIt is the amount of delay of the digital signal delayer；U₁It (T) is that the core pulse passes through the integrating circuit The normalization waveform of the integrated signal of output；R is the resistance value of the integrating resistor；C is the capacitance of the integrating capacitor.

(3) beneficial effect

The present invention is fixed by generating the voltage signal of integrating circuit output end compared with a fixed low voltage threshold When export, its generate level overturning when pass through time-digital converter output time stamp, finally obtained according to the difference of timestamp To the quantity of electric charge of core pulse, system structure is simple, is conducive to the high integration of multichannel, and has measurement accuracy height, measurement The advantages that dead time is small.

Detailed description of the invention

Fig. 1 is a kind of structure composition schematic diagram of core pulse charge time converting system provided by the invention；

Fig. 2 is the actual waveform figure of main node in one embodiment of the invention circuit system；

Fig. 3 is the system linear degree test curve after one embodiment of the invention is corrected；

Fig. 4 is the energy spectrum diagram for the 22Na radioactive source that one embodiment of the invention measurement obtains；

Fig. 5 is a kind of flow diagram of core pulse charge time translation method provided by the invention.

Specific embodiment

To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference Attached drawing, the present invention is described in further detail.

One embodiment of the disclosure provides a kind of core pulse charge time converting system, refering to fig. 1, in conjunction with Fig. 2-Fig. 4, System shown in Figure 1 structure is described in detail.

The time converting system of core pulse charge described in the present embodiment specifically include that integrating circuit 1, voltage comparator 2, when Between digitalizer 3, checking list 4, digital signal delayer 5, discharge resistance 6 and FPGA pin 7.

The integrating circuit 1 is made of operational amplifier and RC integrating circuit, and RC integrating circuit connects operational amplifier Output end and negative input, the integrating circuit includes integrating capacitor and integrating resistor, and the integrating capacitor and integral are electric Resistance is connected in parallel to the operational amplifier.One input terminal of the voltage comparator 2 is connected to the operational amplifier Another input terminal of output end, the voltage comparator 2 connects a threshold voltage.The input terminal of digital signal delayer 5 connects It is connected to the output end of the voltage comparator 2, the output of the digital signal delayer 5 is after the FPGA pin 7 output It is connected to one end of the discharge resistance 6.The other end of the discharge resistance 6 is connected to the negative sense input of the integrating circuit 1 End.The input terminal of the time-digital converter 3 is connected to the output end of the voltage comparator 2.The time digital transformation The output end of device 3 is connected to the input terminal of the checking list 4.

Converting system working principle by taking core pulse signal is negative pulsed current signal as an example, in the disclosure are as follows: integral electricity 1 pair of the road pulsed current signal for inputting its input terminal integrates, and corresponding in output end one voltage signal of generation.Voltage The voltage signal that the integrating circuit 1 exports is compared by comparator 2 with the Low threshold Vth that one pre-sets.Work as voltage When signal is more than threshold voltage, the output of voltage comparator 2 is high level by low level overturning, that is, exports a step signal. Digit time converter 3 detects the step signal that voltage comparator 2 exports, and exports first timestamp, which is exactly The leading edge time of tested core pulse signal.The step signal that voltage comparator 2 exports passes through the delay one of digital signal delayer 5 After the section time, the level that FPGA pin 7 is exported is height by low overturning, and it is V that this, which makes FPGA pin 7 export a size,_H/Rd Electric current discharge integrating circuit 1, FPGA pin 7 is seen as constant-current source at this time.When FPGA pin 7 starts to product When parallel circuit 1 is discharged, the core pulse current signal for being input to integrating circuit 1 still charges to integrating circuit 1.Together When, the integrating resistor R on integral RC network in integrating circuit 1 also provides discharge loop to the charge on integrating capacitor C. Therefore, the voltage signal that integrating circuit 1 exports integrates RC network and current source electric discharge electricity by the core pulse current signal inputted Stream codetermines.The voltage signal that the discharge current that FPGA pin 7 exports exports integrating circuit 1 declines rapidly, works as voltage When signal is lower than threshold voltage vt h, the output of voltage comparator 2 is overturn by high level to low level.On the one hand, time figure becomes It is the low level moment that parallel operation 3, which detects that the output of voltage comparator 2 is overturn by high level, exports second timestamp；Another party Face, the output of voltage comparator 2 make 7 level of FPGA pin become low at once after being overturn from high level to low level, stop It discharges integrating circuit 1.By first timestamp, second timestamp inputs checking list 4, the electricity of core pulse signal can be obtained Charge values.

Specifically, in this converting system, when the output of FPGA pin 7 is high level V_HWhen, just due to operational amplifier To input end grounding, negative input is virtual earth, so the size of current for flowing through discharge resistance 6 that FPGA pin 7 exports is V_H/Rd.Since the core pulse signal of input integral circuit 1 is a pulse negative current signal, the electric current of integrating capacitor C is flowed through The current direction for flowing through integrating capacitor C that direction and FPGA pin 7 export is on the contrary, therefore, input pulse signal is to integrating capacitor It charges, the electric current that FPGA pin 7 exports discharges to integrating capacitor.Since the sloping portion of core pulse signal meets finger The rule of number decaying integrates, it usually needs integrating circuit 1 to guarantee that all charges of core pulse signal are all integrated circuit 1 Time of integration length be greater than three times of core pulse signal exponential decay time constant.In a core pulse measurement, integral electricity The effective integral time on road 1 should terminate when stopping and discharging to FPGA pin 7 since core pulse arrival signal.Pass through adjusting The resistance value of discharge resistance 6 can control constant-current source discharge current size, to control the time that FPGA pin 7 stops electric discharge, make The time of integration for obtaining integrating circuit 1 is not less than three times of core pulse signal damping time constant.

This converting system is by the voltage signal forward position of 1 output end of integrating circuit compared with a fixed low voltage threshold Vth To generate timing output, this method is also referred to as lead edge timing technology.Lead edge timing is simplest timing technology, circuit letter It is single, be conducive to the high integration of multichannel.The precision of lead edge timing is heavily dependent on the size of threshold voltage vt h.For The higher precision of acquisition, the noise level that threshold voltage is slightly higher than circuit system is arranged in we.The electricity that integrating circuit 1 exports When pressure signal leading edge is more than low voltage threshold Vth, the output of voltage comparator 2 is high level, time figure by low level overturning Converter 3 can detect the overturning moment, and export first timestamp, when which represents the forward position of core pulse signal Between.Therefore the temporal information that this converting system realizes core pulse signal is read.

The output of voltage comparator 2 is additionally coupled to digital signal delayer 5.After 2 output end level of voltage comparator is got higher, By the delay of digital signal delayer 5, the level on FPGA pin 7 can also be got higher.By the way that a fixation preset Be delayed Td, which can make the level of FPGA pin 7 attached in the time to peak of 1 output voltage signal of integrating circuit Closely become high, and starts to discharge to integrating circuit 1.After FPGA pin starts electric discharge, the signal of integrating circuit input terminal according to It so charges to integrating circuit, while the integrating resistor R in product RC network also provides a discharge loop.These because Under the collective effect of element, the output voltage of integrating circuit 1 starts to reduce, and when voltage drop is as low as threshold voltage vt h, voltage compares The state that device 2 exports is low by high tumble.The overturning of this state is recorded by TDC, exports second timestamp.This is turned over simultaneously Turn immediately so that the level on FPGA pin 7 also overturn be it is low, the electric discharge of FPGA pin terminates.The length and input of discharge time The quantity of electric charge of core pulse signal is related.According to the time difference T between second timestamp and first timestamp, we can be counted It calculates and obtains the quantity of electric charge of input core pulse signal, physical relationship are as follows:

In above-mentioned relation (1), U₁(T) be the integrated signal that core pulse is exported by the integrating circuit normalization wave Shape, it be the integrated voltage signal waveform of core pulse is directly acquired using high-speed oscilloscope, and by amplitude normalization it is average with It obtains afterwards.Acquire U₁During, FPGA pin 7 is not involved in the electric discharge to integrating circuit 1.RC is the product in integrating circuit 1 Subnetwork, RC value be pass through into integrating circuit 1 input a step signal and measure output signal die-away time obtain 's.Above-mentioned relation (1) is obtained by solving the following differential equation (2), when FPGA pin 7 participates in putting to integrating circuit 1 When electric, the differential equation (2) describes the variation of the output voltage signal Vo of integrating circuit 1:

Wherein i (t) is the pulsed current signal that detector is output to converting system, and u (t) represents unit step signal, i₀ Discharge current size when discharging for FPGA pin 7.It may be seen that the output Vo of integrating circuit 1 is by detector current i (t) electric current of charging, the electric discharge of FPGA pin 7, and integral RC network releases what three processes codetermined.By (2) I Available Vo waveform meet:

Two timestamps that time-digital converter 3 exports have respectively represented waveform Vo and a low voltage threshold Vth phase Two moment handed over.Approximation meets above-mentioned relation (1) between the difference and quantity of electric charge K of two timestamps.Use depositing in FPGA Module is stored up, checking list 4 is established with above-mentioned relation (1).The input of checking list 4 is that time-digital converter 3 measures between timestamp Time difference T, export as the quantity of electric charge of input pulse signal.After electric discharge, measuring system is restored to reset condition, under waiting The arrival of one input pulse signal.

Examples detailed above only for input circuit signal be pulse negative current signal the case where.When input signal is negative for pulse When voltage signal, it is thus only necessary to input voltage signal can be converted to electricity in input terminal one input resistance of series connection of amplifier Signal is flowed, and other settings are constant.

The voltage comparator 2 of the present apparatus, time-digital converter 3, checking list 4, delayer 5 and FPGA pin 7 are constituted Switched current source completion can be designed on a piece of FPGA.Voltage comparator 2 is that the LVDS in FPGA in difference pin connects Receive device.Time-digital converter 3 and delayer are designed by using the logic unit inside FPGA to be completed.Checking list 4 by Ram module building inside FPGA.FPGA pin 7 is configured for the output of LVCMOS25 level, when its output is height When, the voltage on pin is 2.5V.FPGA reduces the use of discrete analog element outside piece, is conducive to increase the integrated of circuit Degree.

Another embodiment of the present disclosure provides a kind of core pulse charge time translation method, show the party referring to Fig. 5 The flow chart of method comprising:

Step S1: integrating circuit 1 receives core pulse current signal, and generates voltage signal in output end；

Step S2: voltage comparator 2 is by the preset threshold value less than the voltage signal peak value of the voltage signal and one Voltage compares, and when the voltage signal is more than the threshold voltage, the output signal of the voltage comparator 2 is carried out for the first time Level overturning；

Step S3: time-digital converter 3 according to the first time level of 2 output signal of voltage comparator overturn when Output is carved to stab at the first time；

Step S4: delayed digital signal device 5 is rotated according to the first time level of the output signal of the voltage comparator 2 It opens discharge control signal and is exported after postponing；

Control of the step S5:FPGA pin 7 in 2 output signal of voltage comparator and the digital signal delayer 5 Under system, discharged with constant electric current the integrating circuit 1；

Step S6: when deteriorating to less than the threshold voltage by the voltage signal that discharges, the voltage comparator 2 Output signal carries out second of level overturning；

Step S7: time-digital converter 3 according to second of level of 2 output signal of voltage comparator overturn when Carve the second timestamp of output；

Step S8: checking list 4 obtains the charge value of the core pulse with the second timestamp according to first time stamp.

In the present embodiment, it is high level that the first time level overturning, which is low level overturning,；Second of level turns over Switching to high level overturning is low level.

In the present embodiment, before step S1 further include: it is big to control the discharge current to adjust 6 size of discharge resistance It is small.

In the present embodiment, step S8 is specifically included:

Using first time stamp and the difference of the second time as input；

The charge value of the pulse is calculated according to the difference and the checking list 4.

According to foregoing description, by a specific exemplary embodiment, the present invention is further described, the conversion system System builds integrating circuit 1 using based on AD8066 operational amplifier.The value of feedback score RC network is respectively as follows: R=1000 Ω Ω, C=510pF.It is connected to the resistance value of the discharge resistance 7 of integrating circuit are as follows: Rd=1000 Ω.Voltage comparator 2, time figure Converter 3, checking list 4, delayer 5 are realized on Xilinx Kintex-7FPGA (xc7k325t).FPGA pin 7 with put Resistance 6 together constitutes a switched current source, when the level of pin 7 is arranged to high, exports the electricity of a 2.5V Pressure, current source start to discharge to integrating circuit 1, and discharge current size is 2.5V/Rd=2.5mA.Time based on FPGA Digitalizer 3 has the time precision of 3.9ps, the measurement dead time of 3.6ns.Measurement result is read by USB2.0 interface Position machine.It will be connected by the photoelectric conversion detector and converting system that silicon photomultiplier (SiPM) and LYSO scintillation crystal form It connects, which can be used for detecting the arrival time and energy size for the gamma ray that radioactive source is launched.

Referring to Fig.2, which show after a current pulse signal input conversion system of the output of photoelectric conversion detector, The variation of some key signal waveforms.2 output waveform of voltage comparator is 1 output waveform of integrating circuit and threshold value at Vo at Vc The comparison result of Vth.After the waveform forward position of Vo is more than threshold value Vth, the waveform overturning that voltage comparator 2 exports at Vc is height. After the delay of delayer 5 in FPGA, the voltage of pin 7 is also reversed as height, and can regard a constant-current source as to integral Circuit 1 discharges.When waveform voltage at Vo is quickly fallen under threshold value Vth under the influence of pin 7 discharges, at Vc The waveform voltage overturning that voltage comparator 2 exports is low, and the voltage of pin 7 is also lower at once, and measuring system is restored as former state, Wait the arrival of next measuring signal.

It is input in converting system using the signal of a high-precision arbitrarily signal generating device analog photoelectricity conversion detector, The function of the converting system is verified with this.The amplitude for changing signal generator output analog signal, measures each input signal The time difference T between two timestamps and the signal charge after the correction of corrected table 4 that lower time-digital converter 3 measures Amount, it is hereby achieved that the energy measurement precision of converting system.Refering to Fig. 3, the obtained linearity is 100%, illustrates the conversion System has very high measurement accuracy.

It uses²²Na radiation source will be visited based on the photoelectric conversion of silicon photomultiplier (SiPM) and LYSO scintillation crystal Device is surveyed, detector output signal is measured into the test device with this²²The power spectrum of Na is as shown in Figure 4.The energy resolution measured Rate is 11.8%, identical as the energy resolution for using other mainstream measurement methods to obtain, and thus proves that the converting system can Obtaining, there are the data of high energy resolution to read.

Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects Describe in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in protection of the invention Within the scope of.