阅读说明：本技术 一种固态存储ic扩容封装方法及结构 (A kind of solid-state storage IC dilatation packaging method and structure ) 是由 李修录 尹善腾 朱小聪 吴健全 于 2019-09-06 设计创作，主要内容包括：本发明公开了一种固态存储IC扩容封装方法,其包括有如下步骤：步骤S1,构建多个初级DIE单元及一桥接芯片；步骤S2,将多个初级DIE单元连接于所述桥接芯片；步骤S3,所述桥接芯片将多个初级DIE单元转换为多个次级DIE单元,并且所述次级DIE单元的数量少于所述初级DIE单元的数量；步骤S4,将所述桥接芯片与多个次级DIE单元封装为Flash芯片。本发明将多个DIE单元进行叠加后,通过桥接芯片组成新的Flash芯片,在不改变DIE单元的基础上实现容量提升。(The invention discloses a kind of solid-state storage IC dilatation packaging methods comprising has the following steps: step S1, constructs multiple primary DIE units and a bridging chip；Multiple primary DIE units are connected to the bridging chip by step S2；Step S3, multiple primary DIE cell translations are multiple secondary DIE units by the bridging chip, and the quantity of the secondary DIE unit is less than the quantity of the primary DIE unit；The bridging chip and multiple secondary DIE units are encapsulated as Flash chip by step S4.After multiple DIE units are overlapped by the present invention, new Flash chip is made up of bridging chip, realizes capacity boost on the basis of not changing DIE unit.)

1. a kind of solid-state storage IC dilatation packaging method, which is characterized in that comprise the following steps that

Step S1 constructs multiple primary DIE units (1) and a bridging chip (2)；

Multiple primary DIE units (1) are connected to the bridging chip (2) by step S2；

Multiple primary DIE units (1) are converted to multiple secondary DIE units (3), and institute by step S3, the bridging chip (2) The quantity for stating secondary DIE unit (3) is less than the quantity of the primary DIE unit (1)；

The bridging chip (2) and multiple secondary DIE units (3) are encapsulated as Flash chip (4) by step S4.

2. solid-state storage IC dilatation packaging method as described in claim 1, which is characterized in that the primary DIE unit (1) Quantity is 2 times of the secondary DIE unit (3).

3. solid-state storage IC dilatation packaging method as described in claim 1, which is characterized in that the primary DIE unit (1) Quantity is more times of the secondary DIE unit (3).

4. solid-state storage IC dilatation packaging method as described in claim 1, which is characterized in that encapsulated in the step S4 Flash chip (4) is bga chip.

5. a kind of solid-state storage IC dilatation encapsulating structure, which is characterized in that include multiple primary DIE units (1) and a bridge joint Chip (2), multiple primary DIE units (1) are connected to the bridging chip (2), will be multiple by the bridging chip (2) Primary DIE unit (1) is converted to multiple secondary DIE units (3), and the quantity of the secondary DIE unit (3) is first less than described The quantity of grade DIE unit (1), then the bridging chip (2) and multiple secondary DIE units (3) are encapsulated as Flash chip (4).

6. solid-state storage IC dilatation encapsulating structure as claimed in claim 5, which is characterized in that the primary DIE unit (1) Quantity is 2 times of the secondary DIE unit (3).

7. solid-state storage IC dilatation encapsulating structure as claimed in claim 5, which is characterized in that the primary DIE unit (1) Quantity is more times of the secondary DIE unit (3).

8. solid-state storage IC dilatation encapsulating structure as claimed in claim 5, which is characterized in that the Flash chip (4) is Bga chip.

Technical field

The present invention relates to solid-state storage IC more particularly to a kind of solid-state storage IC dilatation packaging methods and structure.

Background technique

Summary of the invention

The technical problem to be solved in the present invention is that in view of the deficiencies of the prior art, provide it is a kind of by multiple DIE units into After row superposition, new Flash chip is made up of bridging chip, and capacity boost is realized on the basis of not changing DIE unit Solid-state storage IC dilatation packaging method and structure.

In order to solve the above technical problems, the present invention adopts the following technical scheme that.

A kind of solid-state storage IC dilatation packaging method comprising have the following steps: it is mono- to construct multiple primary DIE by step S1 Member and a bridging chip；Multiple primary DIE units are connected to the bridging chip by step S2；Step S3, the bridging chip It is multiple secondary DIE units by multiple primary DIE cell translations, and the quantity of the secondary DIE unit is less than the primary The quantity of DIE unit；The bridging chip and multiple secondary DIE units are encapsulated as Flash chip by step S4.

Preferably, the quantity of the primary DIE unit is 2 times of the secondary DIE unit.

Preferably, the quantity of the primary DIE unit is more times of the secondary DIE unit.

Preferably, the Flash chip encapsulated in the step S4 is bga chip.

A kind of solid-state storage IC dilatation encapsulating structure comprising have multiple primary DIE units and a bridging chip, Duo Gechu Grade DIE unit is connected to the bridging chip, by multiple primary DIE cell translations is multiple secondary by the bridging chip Grade DIE unit, and the quantity of the secondary DIE unit is less than the quantity of the primary DIE unit, then by the bridging chip Flash chip is encapsulated as with multiple secondary DIE units.

In solid-state storage IC dilatation packaging method disclosed by the invention, by adding one inside the Flash chip Then bridging chip folds the method for DIE unit to increase Flash capacity, for example, two single 256G using Flash chip After DIE unit superposition in chip, it is converted into the chip of a 512G by the bridging chip, DIE unit is not carried out Essential improvement, while chip capacity can be expanded again, and then realize the promotion of Flash chip capacity, application demand is met, In the application 8T SSD, 16TBSSD even greater capacity SSD especially in future market, all has and preferably answer Use prospect.

Detailed description of the invention

Fig. 1 is the structure composed figure of existing solid-state storage IC integrated circuit；

Fig. 2 is the structural schematic diagram of Flash chip encapsulation front and back；

Fig. 3 is the flow chart of solid-state storage IC dilatation packaging method.

Specific embodiment

The present invention is described in more detail with reference to the accompanying drawings and examples.

The invention discloses a kind of solid-state storage IC dilatation packaging methods, in conjunction with shown in Fig. 2 and Fig. 3 comprising have as follows Step:

Step S1 constructs multiple primary DIE units 1 and a bridging chip 2；

Multiple primary DIE units 1 are connected to the bridging chip 2 by step S2；

Multiple primary DIE units 1 are converted to multiple secondary DIE units 3 by step S3, the bridging chip 2, and described The quantity of secondary DIE unit 3 is less than the quantity of the primary DIE unit 1；

The bridging chip 2 is encapsulated as Flash chip 4 with multiple secondary DIE units 3 by step S4.

In the above method, by adding a bridging chip 2 inside the Flash chip, Flash chip is then used The method of DIE unit is folded to increase Flash capacity, for example, leading to after the DIE unit superposition in two single 256G chips The chip that the bridging chip 2 is converted into a 512G is crossed, essential improvement is not carried out to DIE unit, while core can be expanded again Piece capacity, and then the promotion of Flash chip capacity is realized, meet application demand, the 8T especially in future market In the application SSD, 16TBSSD even greater capacity SSD, all with good application prospect.

Fig. 3 is referred to as a preferred method, and the quantity of the primary DIE unit 1 is the secondary DIE unit 3 2 times.Alternatively, the quantity of the primary DIE unit 1 is more times of the secondary DIE unit 3.

In the present embodiment, the Flash chip 4 encapsulated in the step S4 is bga chip.In practical application, Flash chip After folded DIE unit, it is embedded in one solid-state storage IC integrated circuit of bridging chip and composition, is presented in the form of BGA.

In practical application, the capacity of NAND Flash single chip DIE is limited, in order to obtain higher capacity, needs Several DIE units are stacked in one case chip, and the present embodiment is by encapsulation bridging chip, to improve capacity, this can also To break through the capacity limit of script, Fig. 3 is referred to, it might even be possible to produce 16 primary DIE units 4 times by bridging chip Grade DIE unit, then carries out the encapsulation of Flash flash memory.

In order to better describe technical solution of the present invention, the invention also discloses a kind of solid-state storage IC dilatation encapsulation to tie Structure, in conjunction with shown in Fig. 2 and Fig. 3 comprising have multiple primary DIE units 1 and a bridging chip 2, multiple primary DIE units 1 divide It is not connected to the bridging chip 2, it is mono- that multiple primary DIE units 1 are converted to multiple secondary DIE by the bridging chip 2 Member 3, and the quantity of the secondary DIE unit 3 is less than the quantity of the primary DIE unit 1, then by the bridging chip 2 and Multiple secondary DIE units 3 are encapsulated as Flash chip 4.

In above structure, the quantity of the primary DIE unit 1 is 2 times or more times of the secondary DIE unit 3.And The Flash chip 4 is bga chip.

Solid-state storage IC dilatation packaging method and structure disclosed by the invention, beneficial effect compared to existing technologies It is, the present invention can make the SSD of the even higher capacity of large capacity 16TB, 32TB, and stability, reliability are stronger. Meanwhile solid-state storage of the present invention encapsulates IC method of designing integrated circuit, achieves progress outstanding in SSD industry, is suitble at this Field promotes and applies, and with good application prospect.

The above is preferred embodiments of the present invention, is not intended to restrict the invention, all in technology model of the invention Interior done modification, equivalent replacement or improvement etc. are enclosed, should be included in the range of of the invention protect.