阅读说明：本技术 半导体装置及其制作方法 (Semiconductor device and preparation method thereof ) 是由 龚达渊 柳瑞兴 朱振梁 姚智文 雷明达 于 2019-04-15 设计创作，主要内容包括：本发明实施例涉及半导体装置及其制作方法,所述半导体装置包括半导体衬底、栅极介电质、栅极电极及一对源极/漏极区域。所述栅极介电质安置于所述半导体衬底中以具有界定低于所述半导体衬底的上表面的上边界的凹形轮廓。所述栅极电极安置于所述栅极介电质上方。所述对源极/漏极区域安置于所述栅极介电质的对置侧上。(The present embodiments relate to semiconductor device and preparation method thereof, the semiconductor device includes semiconductor substrate, gate dielectric, gate electrode and a pair of of regions and source/drain.The gate dielectric is placed in the semiconductor substrate to have the recessed profile for the coboundary for defining the upper surface lower than the semiconductor substrate.The gate electrode is placed in above the gate dielectric.On the opposite side for being placed in the gate dielectric to regions and source/drain.)

1. a kind of semiconductor device, it includes:

Semiconductor substrate；

Gate dielectric is located in the semiconductor substrate with upper lower than the upper surface of the semiconductor substrate with defining The recessed profile on boundary；

Gate electrode is placed in above the gate dielectric；And

A pair of of regions and source/drain is located on the opposite side of the gate dielectric.

2. semiconductor device according to claim 1, wherein the gate electrode has recessed profile.

3. semiconductor device according to claim 1, wherein the gate dielectric includes the extended in a first direction A part and the second part extended in a second direction, and the first part and the second part connect to each other to form institute State recessed profile.

4. semiconductor device according to claim 1 further includes multiple isolation junctions in the semiconductor substrate Structure.

5. semiconductor device according to claim 4, wherein the depth of the gate dielectric is substantially the same in described The depth of isolation structure.

6. semiconductor device according to claim 1 further includes in the semiconductor substrate and distinguishes position In first well region of a pair to below regions and source/drain, wherein the doping type to the first well region is identical to institute The doping type to regions and source/drain is stated, and the doping concentration to the first well region is lower than described to regions and source/drain Doping concentration.

7. semiconductor device according to claim 6 further includes in the semiconductor substrate and between institute It states to the second well region between the first well region, wherein the doping type of second well region and the doping class to the first well region Type is on the contrary, and described separated the first well region by second well region.

8. a kind of semiconductor device, it includes:

Semiconductor substrate；

First semiconductor device, it includes:

First grid dielectric medium is located in the semiconductor substrate and defines the upper surface lower than the semiconductor substrate to have The first coboundary recessed profile；

First gate electrode is placed in above the first grid dielectric medium；And

A pair of first regions and source/drain, is located on the opposite side of the first grid dielectric medium；And

Second semiconductor device, it includes:

Second grid dielectric medium is located at the semiconductor substrate, wherein the second grid dielectric medium, which has, is higher than institute State the second coboundary of the upper surface of semiconductor substrate；

Second grid electrode is placed in above the second grid dielectric medium；And

A pair of second regions and source/drain, is located on the opposite side of the second grid dielectric medium.

9. semiconductor device according to claim 8 further includes multiple isolation junctions in the semiconductor substrate Structure, and the substantially the same depth in the isolation structure of depth of the first grid dielectric medium.

10. a kind of method for making semiconductor device, it includes:

Receive semiconductor substrate；

The first isolation structure is formed in the semiconductor substrate；

A part of first isolation structure is removed from upper surface portion to form the gate dielectric with recessed profile；

Gate electrode is formed above the gate dielectric；And

A pair of of regions and source/drain is formed in the semiconductor substrate on the opposite side of the gate dielectric.

Technical field

The embodiment of the present invention is related semiconductor device and preparation method thereof.

Background technique

Such as the high-voltage semiconductor device of high voltage MOS (HVMOS) device is usually used in such as power supply In the various electronic devices of management system, AC/DC converter, input/output (I/O) circuit etc..HVMOS device is designed to High voltage is maintained, therefore, the size and structure of HVMOS device are different from the other semiconductors being formed in identical semiconductor substrate Device (such as logic device).It is attributed to its different structure and size, during manufacturing integrating HVMOS device and other semiconductors dress It sets and faces the challenge.

Summary of the invention

One embodiment of the invention discloses a kind of semiconductor device, it includes: semiconductor substrate；Gate dielectric, position To have the recessed profile for the coboundary for defining the upper surface lower than the semiconductor substrate in the semiconductor substrate；Grid Electrode is placed in above the gate dielectric；And a pair of of regions and source/drain, it is located at pair of the gate dielectric It sets on side.

One embodiment of the invention discloses a kind of semiconductor device, it includes: semiconductor substrate；First semiconductor device, It includes the first grid dielectric mediums in the semiconductor substrate, the first grid that is placed in above the first grid dielectric medium The first regions and source/drain of a pair on the opposite side of electrode and the first grid dielectric medium, the first grid dielectric medium Recessed profile with the first coboundary for defining the upper surface lower than the semiconductor substrate；And second semiconductor device, Second grid dielectric medium comprising the semiconductor substrate, the second grid being placed in above the second grid dielectric medium The second regions and source/drain of a pair on the opposite side of electrode and the second grid dielectric medium, wherein the second grid is situated between Electric matter has the second coboundary of the upper surface higher than the semiconductor substrate.

One embodiment of the invention discloses a kind of method for making semiconductor device, it includes: receive semiconductor lining Bottom；The first isolation structure is formed in the semiconductor substrate；One of first isolation structure is removed from upper surface portion Divide to form the gate dielectric with recessed profile；Gate electrode is formed above the gate dielectric；And in the grid A pair of of regions and source/drain is formed in the semiconductor substrate on the opposite side of pole dielectric medium.

Detailed description of the invention

From [embodiment] being read in conjunction with the accompanying drawings most preferably understand the embodiment of this exposure in terms of.It should be noted that root According to professional standard way, various structures are not drawn on scale.In fact, it is clear to make to discuss, it can arbitrarily increase or reduce various The size of structure.

Fig. 1 is the side for being used to make semiconductor device for being painted the various aspects of one or more embodiments according to this exposure The flow chart of method.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J and 2K are the production according to one or more embodiments of this exposure The schematic diagram of one of the various operations of semiconductor device.

Fig. 3 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.

Fig. 4 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.

Fig. 5 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.

Fig. 6 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.

Fig. 7 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.

Specific embodiment

It discloses below and many different embodiments or example of the different characteristic for implementing provided theme is provided.Hereafter will The particular instance of element and arrangement is described to simplify this exposure.Certainly, these are only example and are not intended to limit.For example, with In lower description, make first component be formed in above second component or second component on may include wherein formed directly contact it is described The embodiment of first component and the second component, and may also include wherein additional member and can be formed in the first component and institute State the embodiment that be not directly contacted with the first component and the second component can.In addition, this exposure Can in various examples repeat element symbol and/or letter.This repeats to be in order to simple and clear and itself do not indicate to be begged for Relationship between the various embodiments and/or configuration of opinion.

In addition, for ease of description, spatially relative term (such as " beneath ", " lower section ", "lower", " top ", " ... on Side ", "upper", " ... on " etc.) can be used to describe the pass of element or component and another (a little) elements or component herein System, as depicted in figure.Spatially relative term except covering in figure in addition to discribed orientation, be also intended to cover device using or Being differently directed in operation.It (can be rotated by 90 ° or according to other orientations) according to other way orientation equipment, and can also therefore solve translation Space relative descriptors as used herein.

As used herein, for example, the term of " first ", " second " and " third " describe various elements, component, region, Layer and/or section, these elements, component, region, layer and/or section should not be so limited to these terms.These terms can be only used for Element, component, region, layer or section is set to be distinguished from each other.Unless interior text clearly indicates, otherwise used herein such as " One ", the not implicit sequence of the term of " second " and " third " or sequence.

As used herein, term " approximation ", " generally ", " essence " and " about " is for describing and considering small variation. When binding events or situation in use, term can be related to the example that the event or situation wherein accurately occurs and wherein substantially send out The example of the raw event or situation.For example, when in conjunction with numerical value in use, term can be related to less than or equal to the numerical value ± 10% mobility scale, e.g., less than or equal to ± 5%, be less than or equal to ± 4%, be less than or equal to ± 3%, be less than or equal to ± 2%, be less than or equal to ± 1%, be less than or equal to ± 0.5%, be less than or equal to ± 0.1% or be less than or equal to ± 0.05%.For example, if difference between two values be less than or equal to the average of described value ± 10% (be, for example, less than or wait In ± 5%, it is less than or equal to ± 4%, is less than or equal to ± 3%, is less than or equal to ± 2%, is less than or equal to ± 1%, is less than Or be equal to ± 0.5%, be less than or equal to ± 0.1% or less than or equal to ± 0.05%), then it is assumed that described value " generally " It is identical or equal.For example, " generally " can be related to the angular variable range relative to 0 ° in parallel, less than or equal to ± 10 °, such as Less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than or equal to ± 3 °, be less than or equal to ± 2 °, be less than or equal to ± 1 °, it is small In or be equal to ± 0.5 °, be less than or equal to ± 0.1 ° or be less than or equal to ± 0.05 °.For example, " generally " vertically can be related to phase For 90 ° of angular variable range, it is less than or equal to ± 10 °, e.g., less than or equal to ± 5 °, be less than or equal to ± 4 °, be less than Or be equal to ± 3 °, be less than or equal to ± 2 °, be less than or equal to ± 1 °, be less than or equal to ± 0.5 °, be less than or equal to ± 0.1 ° or Less than or equal to ± 0.05 °.

In one or more embodiments of this exposure, a kind of semiconductor device with gate dielectric, the grid are provided Pole dielectric medium has the recessed profile being formed in semiconductor substrate.The recessed profile is defined lower than the semiconductor substrate The coboundary of upper surface and gate electrode.The recessed profile of the gate dielectric allows relative to the semiconductor substrate The upper surface reduce gate electrode formed thereon.Therefore, with the semiconductor device (example of thicker gate dielectric Such as HVMOS device) it can be integrally formed with having other semiconductor devices (such as logic mos device) compared with thin dielectric substance.Therefore, Production operation can be simplified and production cost can be reduced.

Fig. 1 is the side for being used to make semiconductor device for being painted the various aspects of one or more embodiments according to this exposure The flow chart of method.Method 100 starts from the operation 110 for wherein receiving semiconductor substrate.Method 100 continues wherein to serve as a contrast in semiconductor The operation 120 of the first isolation structure is formed in bottom.Method 100 continues wherein to remove the one of the first isolation structure from upper surface portion Part is to form the operation 130 of the gate dielectric with recessed profile.Method 100 continues wherein rectangular on gate dielectric At the operation 140 of gate electrode.Method continues wherein to be formed in the semiconductor substrate on the opposite side of gate dielectric a pair of The operation 150 of regions and source/drain.

Method 100 is only an example, and is not intended to limit this exposure beyond the content clearly described in claims. Operation bidirectional can be provided before method 100, after 100 period of method and method 100, and the Additional examples of composition of method can be directed to Replacement, elimination or mobile described some operations.

Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J and 2K are the production according to one or more embodiments of this exposure The schematic diagram of one of the various operations of semiconductor device.If shown in Fig. 2A, semiconductor substrate 10 is received.Semiconductor substrate 10 may include bulk substrate or compound substrate.In some embodiments, the material of semiconductor substrate 10 may include such as silicon, germanium Deng element semiconductive material or such as III-V group semi-conductor material compound semiconductor materials (it include GaAsP, AlGaAs, GaInP, GaInAsP etc.).In some embodiments, semiconductor substrate 10 can (but being not limited to) mixed through such as p-type It is miscellaneous.Structure 12 is sacrificed to be formed in above the upper surface 10U of semiconductor substrate 10.For example, sacrificing structure 12 may include liner Layer 121 and mask layer 122.Laying 121 may include the silicon oxide layer that (but being not limited to) can be formed by thermal oxide.Laying 121 can be configured the adhesion coating between semiconductor substrate 10 and mask layer 122.In some embodiments, laying 121 may be used also It is configured as etching stopping layer.In some embodiments, mask layer 122 may include for example, by low-pressure chemical vapor deposition (LPCVD) etc. deposition is come the silicon nitride layer that is formed.Mask layer 122 is configured as covering for the etching of subsequent lithography operations Mould.

As shown in Fig. 2 B, photoresist layer 14 is formed above mask layer 122.Photoresist layer 14 includes Partial exposure mask layer 122 opening 14A.In some embodiments, photoresist layer 14 may include photoresist layer and can be by exposure and imaging operation come pattern Change.It can pass through opening 14A etching mask layer 122 and laying 121 to underlie semiconductor substrate 10 with Partial exposure.By (for example) Etching is to remove exposure semiconductor substrate 10 partially to form multiple groove 10T.It can be by selecting different etching operations and/or erosion Parameter is carved to control the edge contour of groove 10T.In some embodiments, groove 10T can have sloped edge profile, vertical edges Edge profile or curved rim profile.In fig. 2b, the sloped edge profile of groove 10T and vertical is drawn according to some embodiments Edge contour.

Then, as demonstrated in Figure 2 C, it can remove photoresist layer 14.Insulating materials 20 is formed in 12 top of sacrificial layer and groove In 10T.In some embodiments, the material of insulating materials 20 may include silica, silicon nitride, silicon oxynitride etc..It can be used Such as plasma enhanced chemical vapor deposition (PECVD), selective area chemical vapor deposition (SACVD) etc. is suitable heavy Product technology forms insulating materials 20.In some embodiments, can before forming insulating materials 20 in the bottom of groove 10T and Lining oxide layer in being formed on side wall.In some embodiments, interior lining oxide layer may include partly being led by oxidation etc. to be formed in Thermal oxide layer in the exposed of body substrate 10.It in some other embodiments, can be for example, by atomic layer deposition (ALD) etc. Deng deposition form interior lining oxide layer.

If shown in Fig. 2 D, the planarization Operation of such as chemically mechanical polishing (CMP) operation can be performed to remove mask The redundance of the insulating materials 20 of 122 top of layer is to form multiple isolation structures.In some embodiments, mask layer 122 can It is configured as CMP stop layer.In isolation structure, the grid that the first isolation structure 22 may be configured to form semiconductor device is situated between Electric matter, and the second isolation structure 24 can be configured as shallow trench isolation (STI).

As shown in Fig. 2 E, mask layer 122 and laying 121 are removed from the upper surface 10U of semiconductor substrate 10.It can lead to The etching of such as wet etching is crossed to remove mask layer 122 and laying 121.In some embodiments, clean operation can be performed Carry out the upper surface 10U of clean semiconductor substrate 10.In some embodiments, the first isolation can be formed simultaneously by same operation Structure 22 and the second isolation structure 24, therefore, the upper surface 22U of the first isolation structure 22 generally with the second isolation structure 24 Upper surface 24U is flushed, and the lower surface 22B of the first isolation structure 22 is generally neat with the lower surface 24B of the second isolation structure 24 It is flat.In some embodiments, the upper surface 22U of the first isolation structure 22 generally (but being not limited to) and semiconductor substrate 10 is upper Surface 10U is flushed.

As shown in Fig. 2 F, a pair of first well region 30 is formed in semiconductor substrate 10.In some embodiments, have The photoresist layer 32 of opening 32A is formed in 10 top of semiconductor substrate with Partial exposure semiconductor substrate 10.Then, through opening 32A executes impurity implantation to form the first well region in semiconductor substrate 10 to 30.In some embodiments, high voltage will be manufactured NMOS device, and the first well region has n-type doping type to 30 and is configured as high voltage N trap (HVNW).Semiconductor substrate 10 There can be the opposite dopant type of such as p-type.In some other embodiments, high voltage P mos device, and the first trap will be manufactured Area has p-type doping type to 30 and is configured as high voltage P trap (HVPW).Semiconductor substrate 10 can have the phase of such as N-type Contra-doping type.

As shown in Fig. 2 G, removing photoresistance layer 32 is removed.Second well region 34 is formed in semiconductor substrate 10.In some implementations In example, there is another photoresist layer 36 of opening 36A to be formed in 10 top of semiconductor substrate with Partial exposure semiconductor substrate 10.It connects , another impurity implantation is executed through opening 36A to form the second well region 34 in semiconductor substrate 10.Second well region 34 has The doping type (such as p-type) opposite with doping type of first well region to 30, and the second well region 34 is configured as high voltage P trap (HVPW).Second well region 34 is placed in 22 lower section of the first isolation structure.Second well region 34 is placed in the first well region between 30, makes The first well region is obtained to be separated to 30 by the second well region 34.In some embodiments, the first well region is right relative to the second well region 34 to 30 Claim arrangement.In some embodiments, one or more third well regions 38 can be formed together with the second well region 34.Third well region 38 can (but being not limited to) has the doping type and doping concentration for being identical to the second well region 34.

As shown in Fig. 2 H, removing photoresistance layer 36 is removed.A part of the first isolation structure 22 is removed from the part upper surface 22U To form the groove 22R with bottom 22RB extended in the first isolation structure 22.In some embodiments, photoetching can be passed through Operation is to form groove 22R.For example, photoresist layer 40 is formed in 10 top of semiconductor substrate, split shed 40A Partial exposure First isolation structure 22.Then, it executes etching operation and forms groove 22R to etch the first isolation structure 22.

As shown in Fig. 2 I, removing photoresistance layer 40 is removed, and the first isolation structure 22 can form the grid with recessed profile Dielectric medium 23.In some embodiments, the depth (such as by lower interface 23B indicate) of gate dielectric 23 is substantially the same in the The depth (such as being indicated by lower interface 24B) of two isolation structures 24.In some embodiments, gate dielectric 23 may include first Part 231 and second part 232.First part 231 is placed in the bottom of groove 22R and extends along first direction D1.Second Part 232 is connected to first part 231 and D2 extends in a second direction.First part 231 and second part 232 are collectively formed recessed Shape profile, so that the coboundary 231U of first part 231 is lower than the upper surface 10U of semiconductor substrate 10.For example, first party To D1 substantially lateral, and the substantially vertical direction second direction D2.In some other embodiments, second direction D2 can be for relative to the inclined direction first direction D1.

The thickness of gate dielectric 23 can be configured based on the different requirements of different semiconductor devices.For example, when grid is situated between When electric matter 23 is in HVMOS device, the thickness (such as thickness of first part 231) of gate dielectric 23 is generally from about In the range of 800 angstroms to about 1200 angstroms.It can thickness based on the first isolation structure 22, the thickness of gate dielectric 23 and to be formed The thickness of gate electrode determine the depth of groove 22R.For example, the depth of groove 22R is selected so that gate dielectric 23 Thickness can meet HVMOS device voltage maintain require.Consider the thickness of gate electrode to be formed also to determine groove 22R Depth so that the difference in height between the upper surface of gate electrode and the upper surface 10U of semiconductor substrate 10 can be controlled.

As shown in Fig. 2 J, gate electrode 42 is formed above gate dielectric 23.Gate electrode 42 is by for example adulterating (several) conductive material of semiconductive material (such as DOPOS doped polycrystalline silicon) or other suitable conductive materials (such as metal) is formed.In In some embodiments, gate electrode 42 can have recessed profile.For example, gate electrode 42 may include the first section 421 and connection To the second section 422 of the first section 421.First section 421 can be placed in 231 top of first part, and the second section 422 can Extend along second part 232.In some embodiments, the upper surface 421U of the first section 421 is upper lower than semiconductor substrate 10 Surface 10U, and the upper surface 422U of the second section 422 can be higher than, less than or equal to the upper surface 10U of semiconductor substrate 10.In In some other embodiments, the upper surface 421U of the first section 421 can be higher than or generally be flush to the upper of semiconductor substrate 10 Surface 10U.In some embodiments, spacer 27 can be formed on the opposite side of gate electrode 23.

In some embodiments, the first part 231 of the adjacent gate dielectric 23 of gate electrode 42 and second part 232. The thickness of gate electrode 42 can be configured based on the different requirements of different device.For example, the thickness (such as first of gate electrode 42 The thickness of section 421) generally in the range of from about 600 angstroms to about 1200 angstrom.

As shown in Fig. 2 K, formed in the semiconductor substrate 10 on the opposite side of gate dielectric 23 a pair of of source electrode/ Drain region 44.Regions and source/drain is placed in respectively to 44 and is electrically connected to the first well region to 30 tops.In some embodiments In, regions and source/drain is identical to the first well region to 30 doping type to 44 doping type, and regions and source/drain pair 44 doping concentration is higher than the first well region to 30 doping concentration.In some embodiments, one or more contact areas 46 can shape At in semiconductor substrate 10 and being electrically connected respectively to third well region 38.In some embodiments, doping of the contact area to 46 Type is identical to the doping type of third well region 38, and the doping concentration of contact area 46 is dense higher than the doping of third well region 38 Degree.In some embodiments, contact area 46 can be configured to provide voltage to semiconductor substrate 10 through third well region 38.

In some embodiments, over the semiconductor substrate 10 it is rectangular at interlayer dielectric (ILD) 50 to cover gate electrode 42.Therefore, semiconductor device 1 is formed.In some embodiments, the thickness of gate dielectric 23 can have from about 800 angstroms to about 1200 angstroms of range, and the thickness of gate electrode 42 is in the range of from about 600 angstroms to about 1200 angstrom.The thickness of ILD50 can be small In the summation of the thickness of the thickness and gate electrode 42 of gate dielectric 23.For example, the thickness of ILD 50 can be about 1300 angstroms.By In the recessed profile of gate dielectric 23, ILD 50 can cover gate electrode 42.

In some embodiments, semiconductor device 1 is symmetrical NMOS device.Semiconductor substrate 10 can be P type substrate.First Well region 30 can be N-type.Second well region 34 and third well region 38 can be p-type.

With reference to Fig. 3.Fig. 3 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.Such as institute's exhibition in Fig. 3 Show, semiconductor device 2 may include being integrally formed in the first semiconductor device 2A and the second half of the top of semiconductor substrate 10 to lead Body device 2B.In some embodiments, the first semiconductor device 2A can be semiconductor device 1 depicted in such as Fig. 2 K HVMOS device, and the details of the first semiconductor device 2A is described.In some other embodiments, the first semiconductor device 2A can For semiconductor device 3,4,5 or 6 depicted in the other embodiments of this exposure.Second semiconductor device 2B can fill for logic It sets, middle voltage MOS (MVMOS) device, low-voltage MOS (LVMOS) device etc..Second semiconductor device 2B may include trap 70, Second grid dielectric medium 72, second grid electrode 74, a pair of second regions and source/drain 76 and the second spacer 78.Second gate Pole dielectric medium 72 is located at 10 top of semiconductor substrate.Compared with the gate dielectric 23 of the first semiconductor device 2A, second grid Dielectric medium 72 is relatively thin, and can be formed in above the flat of semiconductor substrate 10.Second grid dielectric medium 72, which has, is higher than half The second coboundary 72U of the upper surface 10U of conductor substrate 10.Second grid electrode 74 is placed on second grid dielectric medium 72 Side.Second regions and source/drain is placed in the semiconductor substrate 10 on the opposite side of second grid dielectric medium 72 to 76.One In a little embodiments, the second semiconductor device 2B can further comprise the second spacer on the opposite side of second grid electrode 74 78.Semiconductor device 2 further comprises the ILD 50 for covering gate electrode 42 and second grid electrode 74.

For the HVMOS device of such as the first semiconductor device 2A, gate dielectric 23 is maintained frequently with thicker degree High voltage.The thicker gate dielectric thickness of HV device requires to be difficult to manufacture and frequently with relatively thin gate dielectric and thinner layer Between dielectric medium (ILD) other semiconductor devices (such as second semiconductor device 2B) (its be configured to logic device, MVMOS dress Set or LVMOS device) it is integrated.Since ILD 50 is shared by the first semiconductor device 2A and the second semiconductor device 2B, so ILD 50 need to meet the requirement of both the first semiconductor device 2A and the second semiconductor device 2B.For example, the grid of HVMOS device The range that the thickness of pole dielectric medium 23 can have from about 800 angstroms to about 1200 angstrom, and the thickness of the gate electrode 42 of HVMOS device In the range of from about 600 angstroms to 1200 angstroms.The thickness of ILD 50 cannot be too thick to meet the requirement of logic device, but sometimes may be used It is reduced to about 1300 angstroms.In this case, the overall thickness of gate dielectric 23 and gate electrode 42 can be more than the thickness of ILD 50 Degree.In this case, the upper surface of the gate electrode 42 of HVMOS device can be more than ILD 50 and therefore not covered by ILD 50 Lid.This challenge becomes more severe in advanced semiconductor manufacture (such as at 28 nanometers or more than in the manufacture of 28 nanometer nodes). Due to the recessed profile of gate dielectric 23, gate electrode 42 is lowered, so that ILD 50 can cover the first semiconductor device 2A Gate electrode 42 and both second grid electrodes 74 of the second semiconductor device 2B.

Semiconductor device and preparation method thereof is not only restricted to above-described embodiment, but can have other different embodiments.For Simplify description and be each embodiment convenient for relatively this exposure, the phase in following embodiment is marked using similar elements symbol Same component.To be easier to the difference between comparing embodiment, the difference between different embodiments will be explained in detail and will not by being described below Redundancy description same characteristic features.

Fig. 4 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.As demonstrated in Figure 4, with Fig. 2 K Semiconductor device 1 compare, semiconductor device 3 further comprises ILD 50 and the ILD above the upper surface of semiconductor substrate 10 Multiple contact accesses 52 in 50.Contact access 52 may be electrically connected to gate electrode 42, regions and source/drain to 44 and/or connect Region 46 is touched to provide a signal to or receive signal from gate electrode 42, regions and source/drain to 44 and/or contact area 46. Semiconductor device 3 can further comprise interconnection structure 60 comprising one or more inter-metal dielectrics (IMD) 62 and for example heavy cloth The circuit layer 64 of layer (RDL).Semiconductor device 3 can further comprise the passivation through 60 top of interconnection structure 60 and interconnection structure Layer 82 is electrically connected to gate electrode 42, regions and source/drain to 44 and/or the engagement pad 80 of contact area 46.

As demonstrated in Figure 4, at least part of gate electrode 42 and gate dielectric 23 is lower than semiconductor substrate 10 Upper surface 10U.Therefore, the level of gate electrode 42 can be reduced.Therefore, ILD 50 can cover gate electrode 42, and contact access 52 can extend across ILD 50 and be electrically connected to gate electrode 42, even if the thickness of ILD 50 is thinner than gate dielectric 23 and grid The overall thickness of electrode 42.

Fig. 5 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.As demonstrated in Figure 5, with Fig. 2 K Semiconductor device 1 compare, semiconductor device 4 can be symmetrical PMOS device.Semiconductor device 4 can further comprise being formed in N-type deep-well region 39 in the P-type semiconductor substrate 10 of 38 lower section of one well region 30, the second well region 34 and third well region.First well region 30 can be p-type.Second well region 34 and third well region 38 can be N-type.In some embodiments, contact area 46 can be configured with saturating It crosses third well region 38 and provides voltage to deep-well region 39.In some embodiments, semiconductor device 4 can further comprise one or more 4th well region 41 and one or more contact areas 43 for being electrically connected to the 4th well region 41.4th well region 41 and contact area 43 can be P-type, and the doping concentration of contact area 43 is higher than the doping concentration of the 4th well region 41.In some embodiments, contact area 43 It can be configured to provide voltage to semiconductor substrate 10 through the 4th well region 41.

Fig. 6 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.As illustrated in figure 6, with partly lead Body device 1 is compared, and semiconductor device 5 is asymmetric NMOS device, wherein the first well region is not right relative to the second well region 34 to 30 Claim arrangement.Semiconductor substrate 10 is p-type.In some embodiments, the identical doping class that the first well region can have such as N-type to 30 Type but different levels of doping.For example, the first well region is smaller than another first well region 30 and shallow and by the second well region 34 to one of 30 It surrounds.Smaller and shallower first well region 30 can (but being not limited to) have higher than another first well region 30 doping concentration.Second trap Area 34 is p-type.In some embodiments, semiconductor device 5 further comprises being located in semiconductor substrate 10 and being electrically connected to the The contact area 45 of two well regions 34.Contact area 45 can have the doping type (example for the doping type for being identical to the second well region 34 Such as p-type), but the doping concentration of contact area 45 is higher than the doping concentration of the second well region 34.Contact area 45 can be configured with saturating It crosses the second well region 34 and provides voltage to semiconductor substrate 10.

Fig. 7 is the schematic diagram according to the semiconductor device of some embodiments of this exposure.As shown in fig. 7, semiconductor Device 6 is asymmetric PMOS device, wherein the first well region is to 30 relative to 34 unsymmetrical arrangement of the second well region.With semiconductor device 5 compare, and semiconductor device 6 can further comprise the p-type for being formed in 38 lower section of the first well region 30, the second well region 34 and third well region N-type deep-well region 39 in semiconductor substrate 10.First well region 30 can be p-type.Second well region 34 and third well region 38 can be N-type. In some embodiments, contact area 46 can be configured to provide voltage to deep-well region 39 through third well region 38.In some realities It applies in example, semiconductor device 6 can further comprise one or more the 4th well regions 41 and be electrically connected to the one or more of the 4th well region 41 A contact area 43.4th well region 41 and contact area 43 can be p-type, and the doping concentration of contact area 43 is higher than the 4th well region 41 doping concentration.In some embodiments, contact area 43 can be configured to penetrate the 4th well region 41 to semiconductor substrate 10 Voltage is provided.

In some embodiments of this exposure, the semiconductor device and preparation method thereof of such as HVMOS device is provided.With example Such as middle voltage MOS (MVMOS) device, low-voltage metal-oxide semiconductor (MOS) (LVMOS) device or logic Other semiconductor devices of mos device are compared, and HVMOS device has thicker gate dielectric, therefore, the manufacture of HVMOS device It can not be compatible with other semiconductor devices.For example, the ILD for logic device cannot be too thick with covering due to capacitor is considered The gate electrode of HVMOS device.The gate dielectric for the semiconductor device being recessed from the isolation structure of such as STI reduces grid electricity The upper surface of pole, while still may achieve thicker gate dielectric thickness.Therefore, have the HVMOS device for reducing gate electrode can It is integrally formed with other semiconductor devices, and shares phase with other semiconductor devices on another device region in same substrate With ILD thickness.Therefore, production operation can be simplified, and production cost can be reduced.

In some embodiments, a kind of semiconductor device includes semiconductor substrate, gate dielectric, gate electrode and a pair Regions and source/drain.The gate dielectric is placed in the semiconductor substrate to have to define and serve as a contrast lower than the semiconductor The recessed profile of the coboundary of the upper surface at bottom.The gate electrode is placed in above the gate dielectric.It is described to source electrode/ Drain region is placed on the opposite side of the gate dielectric.

In some embodiments, a kind of semiconductor device includes semiconductor substrate, the first semiconductor device and the second half leads Body device.First semiconductor device includes first grid dielectric medium, first gate electrode and a pair of first source/drain regions Domain.The first grid dielectric medium is placed in the semiconductor substrate to have the upper table defined lower than the semiconductor substrate The recessed profile of first coboundary in face.The first gate electrode is placed in above the first grid dielectric medium.It is described right First regions and source/drain is placed on the opposite side of the first grid dielectric medium.Second semiconductor device includes the Two gate dielectrics, second grid electrode and a pair of second regions and source/drain.The second grid dielectric medium is placed in described Semiconductor substrate, wherein the second grid dielectric medium has second of the upper surface higher than the semiconductor substrate Coboundary.The second grid electrode is placed in above the second grid dielectric medium.It is described that second regions and source/drain is pacified It is placed on the opposite side of the second grid dielectric medium.

In some embodiments, a kind of method for making semiconductor device includes following operation.Receive semiconductor lining Bottom.The first isolation structure is formed in the semiconductor substrate.One of first isolation structure is removed from upper surface portion Divide to form the gate dielectric with recessed profile.In the groove and on the upper surface of first isolation structure It is rectangular at gate electrode.A pair of of source/drain is formed in the semiconductor substrate on the opposite side of the gate dielectric Region.

The structure for having summarized several embodiments above, so that those skilled in the art preferably understands the side of this exposure Face.It will be understood by one of ordinary skill in the art that it can be easy to be used to design or modify by this exposure to be used to implement identical mesh And/or basis that reach other programs of the same advantage of introduced embodiment and structure herein.The skill of fields Art personnel should also recognize, these equivalent buildings should not deviate from the spirit and scope of this exposure, and it can be without departing substantially from this exposure To being variously modified, replace and change herein in the case where spirit and scope.

Symbol description

1 semiconductor device

2 semiconductor devices

The first semiconductor device of 2A

The second semiconductor device of 2B

3 semiconductor devices

4 semiconductor devices

5 semiconductor devices

6 semiconductor devices

10 semiconductor substrates

The upper surface 10U

10T groove

12 sacrifice structure/sacrificial layer

14 photoresist layers

14A opening

20 insulating materials

22 first isolation structures

The lower surface 22B

22R groove

The bottom 22RB

The upper surface 22U

23 gate dielectrics

Interface under 23B

24 second isolation structures

The lower surface 24B/lower interface

The upper surface 24U

27 spacers

30 first well regions

32 photoresist layers

32A opening

34 second well regions

36 photoresist layers

36A opening

38 third well regions

39 N-type deep-well regions

40 photoresist layers

40A opening

41 the 4th well regions

42 gate electrodes

43 contact areas

44 regions and source/drains

45 contact areas

46 contact areas

50 interlayer dielectrics (ILD)

52 contact accesses

60 interconnection structures

62 inter-metal dielectrics (IMD)

64 circuit layers

70 traps

72 second grid dielectric mediums

The second coboundary 72U

74 second grid electrodes

76 second regions and source/drains

78 second spacers

80 engagement pads

82 passivation layers

100 methods

110 operations

120 operations

121 layings

122 mask layers

130 operations

140 operations

150 operations

231 first parts

The coboundary 231U

232 second parts

421 first sections

The upper surface 421U

422 second sections

The upper surface 422U

D1 first direction

D2 second direction