阅读说明：本技术 一种集存算一体的全铁电场效应晶体管 (A kind of collection deposits the full ferro-electric field effect transistor of calculation one ) 是由 江安全 柴晓杰 汪超 江钧 张焱 于 2019-08-01 设计创作，主要内容包括：本发明涉及一种集存算一体的全铁电场效应晶体管,包括基底、源电极、漏电极、栅电极和铁电凸块,所述源电极和漏电极通过铁电凸块相隔离地设置于基底上,栅电极和源电极、漏电极隔离设置,所述基底由具有畴壁导电特性的铁电材料制成。与现有技术相比,本发明从根本上解决了铁电体的高度集成化的问题。(The full ferro-electric field effect transistor for calculating one is deposited the present invention relates to a kind of collection, including substrate, source electrode, drain electrode, gate electrode and ferroelectricity convex block, the source electrode and drain electrode is separated by liftoff be set in substrate by ferroelectricity convex block, gate electrode and source electrode, drain electrode isolation setting, the substrate are made of the ferroelectric material with domain wall conductive characteristic.Compared with prior art, the present invention fundamentally solves the problems, such as ferroelectric Highgrade integration.)

1. it is a kind of collection deposit calculate one full ferro-electric field effect transistor, including substrate (10), source electrode (20), drain electrode (30), Gate electrode (40) and ferroelectricity convex block (50), the source electrode (20) and drain electrode (30) are separated by liftoff set by ferroelectricity convex block (50) It is placed on substrate (10), gate electrode (40) and source electrode (20), drain electrode (30) isolation setting, which is characterized in that the substrate (10) it is made of the ferroelectric material with domain wall conductive characteristic.

2. collection according to claim 1 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the substrate (10) when consistent with the electricdomain polarization direction of ferroelectricity convex block (50), full ferro-electric field effect transistor is normal status；

When substrate (10) is opposite with the electricdomain polarization direction of ferroelectricity convex block (50), full ferro-electric field effect transistor is normally open.

3. collection according to claim 1 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that gate electrode (40) Vacantly, the source electrode (20), drain electrode (30) and ferroelectricity convex block (50) form non-volatile ferroelectric memory.

4. collection according to claim 1 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the gate electrode (40) it is set to the top of ferroelectricity convex block (50), and gate electrode (40) width is less than the width of ferroelectricity convex block (50).

5. collection according to claim 4 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the ferroelectricity is convex It is 0 angle that the polarized direction of electricdomain and gate electrode (40) plane normal, which exist not, in block (50), and the electricdomain is in source electrode (20), important on the line direction of drain electrode (30).

6. collection according to claim 4 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the gate electrode (40) insulating layer is provided between the ferroelectricity convex block (50).

7. collection according to claim 1 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the gate electrode (40) it is set to the lower section of substrate (10).

8. collection according to claim 1 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that the ferroelectricity is convex Block (50) thickness is more than or equal to 1nm and is less than or equal to 500nm.

9. -8 any collection deposit the full ferro-electric field effect transistor for calculating one according to claim 1, which is characterized in that also wrap Substrate (60) are included, which is located at the bottom of field effect transistor.

10. it is a kind of collection deposit calculate one full ferro-electric field effect transistor, including substrate (10), source electrode (20), drain electrode (30), Ferroelectricity convex block (50) and substrate (60), the source electrode (20) and drain electrode (30) are separated by liftoff setting by ferroelectricity convex block (50) In on substrate (10), which is characterized in that the substrate (10) is made of the ferroelectric material with domain wall conductive characteristic, the substrate It (60) is the p-type or N-type silicon chip of heavy doping.

11. a kind of collection deposits the full ferro-electric field effect transistor for calculating one, including substrate (10), source electrode (20), drain electrode (30) With substrate (60), which is characterized in that the substrate (10) is made of the ferroelectric material with domain wall conductive characteristic, the source electrode (20) and drain electrode (30) micro-nano technique be separated by it is liftoff be set on substrate (10), the substrate (60) be heavy doping p-type or Person's N-type silicon chip.

12. a kind of collection deposits the full ferro-electric field effect transistor for calculating one, including substrate (10), source electrode (20), drain electrode (30) With gate electrode (40), which is characterized in that the substrate (10) is made of the ferroelectric material with domain wall conductive characteristic, the source electricity Pole (20) and drain electrode (30) micro-nano technique be separated by it is liftoff be set in substrate, the gate electrode (40) is set under substrate (10) Side.

13. collection according to claim 12 deposits the full ferro-electric field effect transistor for calculating one, which is characterized in that further include lining Bottom (60), the substrate (60) are located at the bottom of field effect transistor.

Technical field

The invention belongs to FERROELECTRICS MEMORIES TECHNOLOGY field and fet logic field more particularly to a kind of collection Deposit the full ferro-electric field effect transistor for calculating one.

Background technique

Ferroelectric integrated mainly integrate ferroelectric thin-flim materials and semiconductor material forms with a certain Or the device of certain specific functions, it is widely used in ferroelectric memory device, opto-electronic device, ultrasonic wave and surface acoustic wave device In part, infrared acquisition and image device.

In six the seventies of twentieth century, due to being influenced by microelectronic component thin-film integration technique, memory iron Conductive film is developed.But there is compatibility issues between ferroelectric thin film and semiconductor technology, until twentieth century 80 Mid-nineties 90, with the development of silicon integrated technology, ferroelectric memory becomes research hotspot again.In 1987, ferroelectric random was deposited Access to memory and complementary mos device are successfully integrated.

Currently, preparation process, process and rear end integrated technique of film etc. all can be right since process conditions are limited Ferroelectric thin film characteristic generates certain negative effect, to will also result in certain negative effect to performance of integrated circuits.At present The compatibility of ferro-electric device and standard CMOS process there is also some problems, if if the characteristic size of processing line reduces again, that To its compatibility, just more stringent requirements are proposed.In existing ferro-electric field effect transistor, due to ferro-electric device and standard The compatibility of CMOS technology there is also some problems, so as to cause ferro-electric field effect transistor large-scale integrated.

The ferroelectric memory device based on domain wall conduction has been proposed (referring to China Patent Publication No. in present inventor 107123648A, 104637948A, 104637949A, 105655342A, 107481751A and U.S. Patent Publication No. The patent of US9685216B2, international patent application no PCT/CN2018/07748 5), disclose a kind of nondestructive read-out (NDRO) ferroelectric memory is that non-Destructive readout is realized with electric current reading manner (i.e. non-destructive electric current is read). On the one hand, ON state read current can reach 10^-7A to 10^-6A, read current are big；Another aspect ON state electric current and Off state electric current ratio are (i.e. On-off ratio) 10 can be reached⁶More than, data retention can be good, has and prepares the advantages such as simple, at low cost, storage density is high, therefore It is paid close attention to by industry.

The application is researched and developed based on the exploration of the above-mentioned prior art and a kind of is able to solve the new of ferroelectric Highgrade integration problem Type field effect transistor.

Summary of the invention

It a kind of collection is provided deposits and calculate the full iron of one it is an object of the invention to overcome the problems of the above-mentioned prior art Field effect transistor.

The purpose of the present invention can be achieved through the following technical solutions:

A kind of collection deposits the full ferro-electric field effect transistor of calculation one, including substrate, source electrode, drain electrode, gate electrode and iron Electric convex block, the source electrode and drain electrode by ferroelectricity convex block be separated by it is liftoff be set in substrate, gate electrode and source electrode, electric leakage Pole isolation setting, the substrate are made of the ferroelectric material with domain wall conductive characteristic.

Further, during the full ferro-electric field effect transistor work, wherein apply between gate electrode and source-drain electrode Voltage is less than the coercive field voltage of domain reversal between gate electrode and source-drain electrode.

Further, the substrate is ferroelectric thin film or ferro-electricity single crystal substrate.

Preferably, the ferroelectric thin film or ferro-electricity single crystal substrate are selected from tantalic acid lithium salts LiTaO₃, niobic acid lithium salts LiNbO₃；

Alternatively, selected from doping MgO, Mn₂O₅、Fe₂O₃Or La₂O₃Tantalic acid lithium salts LiTaO₃, niobic acid lithium salts LiNbO₃；

Alternatively, being the tantalic acid lithium salts LiTaO of melanism₃Or niobic acid lithium salts LiNbO₃。

As optional, the gate electrode, source electrode and drain electrode using tungsten, Titanium, metallic copper, metallic aluminium, Metal platinum, metal iridium, metal, ruthenium, tungsten nitride, titanium nitride, tantalum nitride, yttrium oxide, ruthenium-oxide, tungsten carbide, titanium carbide, silication In tungsten, titanium silicide and tantalum silicide any one or both more than combination.

Further, when the substrate is consistent with the electricdomain polarization direction of ferroelectricity convex block, full ferro-electric field effect transistor is Normal status；

When substrate is opposite with the electricdomain polarization direction of ferroelectricity convex block, full ferro-electric field effect transistor is normally open.

Further, gate electrode is hanging, and the source electrode, drain electrode and ferroelectricity convex block form non-volatile ferroelectricity storage Device.

Further, the gate electrode is set to the top of ferroelectricity convex block, and gate electrode width is less than ferroelectricity convex block Width avoids source and drain gate electrode short-circuit.

Further, it is not 0 angle that the polarized direction of electricdomain and gate electrode plane normal, which exist, in the ferroelectricity convex block, and And the electricdomain source electrode, drain electrode line direction on it is important.

Further, insulating layer is provided between the gate electrode and the ferroelectricity convex block.

As optional, the insulating layer using in silica material, oxidation germanium material, aluminium oxide and silicon oxynitride at least It is a kind of.

Further, the gate electrode is set to the lower section of substrate.

Further, the ferroelectricity convex block thickness is more than or equal to 1nm and is less than or equal to 500nm.

It further, further include substrate, which is located at the bottom of field effect transistor.

The full ferro-electric field effect transistor for calculating one, including substrate, source electrode, electric leakage are deposited the present invention also provides a kind of collection Pole, ferroelectricity convex block and substrate, the source electrode and drain electrode by ferroelectricity convex block be separated by it is liftoff be set in substrate, the substrate It is made of the ferroelectric material with domain wall conductive characteristic, the substrate is the p-type or N-type silicon chip of heavy doping.

The full ferro-electric field effect transistor for calculating one, including substrate, source electrode, drain electrode are deposited the present invention also provides a kind of collection And substrate, the substrate are made of the ferroelectric material with domain wall conductive characteristic, the source electrode and drain electrode micro-nano technique phase It is isolator set in substrate, the substrate is the p-type or N-type silicon chip of heavy doping.

The full ferro-electric field effect transistor for calculating one, including substrate, source electrode, drain electrode are deposited the present invention also provides a kind of collection And gate electrode, the substrate are made of the ferroelectric material with domain wall conductive characteristic, the source electrode and drain electrode micro-nano technique Be separated by it is liftoff be set in substrate, the gate electrode is set to below substrate.

Compared with prior art, the invention has the following beneficial effects:

The present invention is made from substrate of the ferroelectric material with domain wall conductive characteristic, by the change of electricdomain polarization direction, It realizes that the switch state of field effect transistor changes, solves asking for the compatibility of ferroelectricity ferro-electric device and standard CMOS process Topic can use the independent realization CMOS function of ferroelectric material, and then fundamentally solve the problems, such as ferroelectric Highgrade integration, Collection is realized on traditional ferroelectric material deposits the full ferro-electric field effect transistor for calculating one.

Detailed description of the invention

From the following detailed description in conjunction with attached drawing, it will keep above and other purpose and advantage of the invention more complete It is clear, wherein the same or similar element, which is adopted, to be indicated by the same numeral.

Fig. 1 is that collection deposits the full ferro-electric field effect transistor structural schematic diagram for calculating one in first embodiment of the invention；

Fig. 2 is the schematic diagram of the transfer characteristic curve of full ferro-electric field effect transistor in Fig. 1 embodiment；

Fig. 3 is vertical view scanning electron microscope (SEM) schematic diagram of full ferro-electric field effect transistor in Fig. 1 embodiment；

Fig. 4 is that collection deposits the full ferro-electric field effect transistor structural schematic diagram for calculating one in second embodiment of the invention；

Fig. 5 is that collection deposits the full ferro-electric field effect transistor structural schematic diagram for calculating one in third embodiment of the invention；

Fig. 6 is that collection deposits the full ferro-electric field effect transistor structural schematic diagram for calculating one in fourth embodiment of the invention；

Fig. 7 is that collection deposits the full ferro-electric field effect transistor structural schematic diagram for calculating one in fifth embodiment of the invention.

Specific embodiment

The present invention is described in detail with specific embodiment below in conjunction with the accompanying drawings.The present embodiment is with technical solution of the present invention Premised on implemented, the detailed implementation method and specific operation process are given, but protection scope of the present invention is not limited to Following embodiments.

In the accompanying drawings, for the sake of clarity, the thickness of layer and region is exaggerated, the size ratio between each section in diagram Example relationship does not reflect actual dimension scale relationship.

In the examples below, clear for description, electricdomain direction or polarization direction are illustratively given, still It is to be understood that the electricdomain direction of ferroelectric memory or polarization direction are not limited to the direction for implementing to exemplify as shown in the figure.

In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people The model that the present invention protects all should belong in member's every other embodiment obtained without making creative work It encloses.

First embodiment

Collection provided in this embodiment deposits the cross section structure schematic diagram such as Fig. 1 institute for calculating the full ferro-electric field effect transistor of one Show, mainly includes the gate electrode 40 and ferroelectricity convex block that substrate 10, source electrode 20 and drain electrode 30 and source-drain electrode are isolated 50.Wherein substrate 10 is made of the ferroelectric material with domain wall conductive characteristic.In the present embodiment, substrate is additionally provided with below substrate 10 60.Source electrode 20, drain electrode 30 and ferroelectricity convex block 50 constitute non-volatile ferroelectric memory；Source electrode 20 and drain electrode 30, The gate electrode 40 and ferroelectricity convex block 50 being isolated with source-drain electrode constitute field-effect tube, deposit calculation one to realize.

The electricdomain polarization direction of electricdomain polarization direction and underbump substrate 10 is on the contrary, at electricdomain interface in ferroelectricity convex block 50 Place forms the domain wall channel of high conductance (in Fig. 1 shown in grey filled lines).The domain wall channel of high conductance is as the full ferroelectricity of open type The conducting channel of field-effect tube.When substrate 10 is consistent with the electricdomain polarization direction of ferroelectricity convex block 50, full ferro-electric field effect transistor For normal status；When substrate 10 and the electricdomain polarization direction of ferroelectricity convex block 50 on the contrary, full ferro-electric field effect transistor is normally opened shape State can regulate and control the electric current in the domain wall channel of high conductance by gate electrode voltage, thus by the shutdown in domain wall channel, and then realize iron Field effect pipe function.

It is significant to note that depositing the full ferro-electric field effect transistor for calculating one, gate electrode and source based on this framework Ferroelectricity electricdomain between drain electrode can not or can not be inverted with gate voltage.

Ferroelectric material is ferro-electricity single crystal piece or ferroelectric thin film, is selected from tantalic acid lithium salts LiTaO₃, niobic acid lithium salts LiNbO₃；Alternatively, Selected from doping MgO, Mn₂O₅、Fe₂O₃Or La₂O₃Tantalic acid lithium salts LiTaO₃, niobic acid lithium salts LiNbO₃；Alternatively, being the tantalic acid of melanism Lithium salts LiTaO₃Or niobic acid lithium salts LiNbO₃。

The thickness of ferroelectricity convex block 50 is more than or equal to 1nm and is less than or equal to 500nm.

Source electrode 20 and drain electrode 30 are arranged in the two sides of ferroelectricity convex block 50 and are at least separated by the ferroelectricity convex block 50；Grid Electrode 40 is set to the top of ferroelectricity convex block 50, and 40 width of gate electrode is less than the width of ferroelectricity convex block 50.

As optional, settable insulating layer or barrier layer (do not show in figure between gate electrode 40 and the ferroelectricity convex block 50 Out).Insulating layer or barrier layer are using at least one of silica material, oxidation germanium material, aluminium oxide and silicon oxynitride.

It is especially noted that in ferroelectricity convex block 50 the polarized direction of electricdomain and 40 plane normal of gate electrode there are non- 0 angle and keep the electricdomain important on the line direction of source-drain electrode.When gate electrode 40 is hanging, source electrode at this time 20, drain electrode 30 and ferroelectricity convex block 50 constitute non-volatile ferroelectric memory and work.Present inventor is in Chinese patent public affairs The number of opening 107123648A, 104637948A, 104637949A, 105655342A, 107481751A and U.S. Patent Publication No. It did and was discussed in detail in the patents such as patent, the international patent application no PCT/CN2018/077485 of US9685216B2.

It is illustrated in figure 2 collection in the present embodiment and deposits the transfer characteristic curve for calculating the full ferro-electric field effect transistor of one, The on-off ratio of middle electric current can achieve 5 orders of magnitude, and subthreshold swing SS=216mV/dec, realize traditional field-effect The function of pipe.With the improvement of device manufacturing process, SS can be smaller, and driving current is bigger.Fig. 3 show collection in the present embodiment and deposits Calculate vertical view scanning electron microscope (SEM) schematic diagram of the full ferro-electric field effect transistor of one.

It is above-mentioned to deposit the full ferro-electric field effect transistor for calculating one, nonvolatile memory can be achieved at the same time in single ferroelectric Function and field-effect tube function.

Second embodiment

As shown in fig.4, the structure of the present embodiment and first embodiment is essentially identical, difference is: gate electrode layer 40 In the lower section of substrate 10, back-gate electrode is formed.

It should be noted that depositing the full ferro-electric field effect transistor for calculating one, gate electrode and source and drain electricity based on this framework Ferroelectric domain between pole will not change with gate voltage and be inverted.

3rd embodiment

As shown in fig.5, the structure of the present embodiment and second embodiment is essentially identical, difference is: substrate 60 is heavily doped Miscellaneous p-type or N-type silicon chip, can be used as back-gate electrode.This embodiment simplifies technical process, do not need to do back-gate electrode.

Fourth embodiment

As shown in fig.6, the structure of the present embodiment and second embodiment is essentially identical, difference is: source-drain electrode can be straight It is placed separately above ferroelectric thin film layer to connect micro-nano technology room, realizes with there are the similar function of ferroelectricity convex block, does not then need shape At ferroelectricity convex block.

5th embodiment

As shown in fig.7, the difference of the present embodiment and fourth embodiment is: substrate 60 is the p-type or N-type of heavy doping Silicon wafer.This embodiment simplifies technical process, do not need to do back-gate electrode.

The above case primarily illustrates a kind of full ferro-electric field effect transistor deposited and calculate one.Although only to some of real The mode of applying is described, but those of ordinary skill in the art it is to be appreciated that the present invention can without departing from its spirit with model Implement in enclosing in many other forms.Therefore, institute's presenting case is considered as illustrative and not restrictive with embodiment, In the case where not departing from the spirit and scope of the present invention as defined in appended claims, the present invention may cover various Modification and replacement.