阅读说明：本技术 具有自动校正功能的数字锁相回路及其自动校正方法 (Digital phase locked loop and its auto-correction method with zero offset capability ) 是由 陈璟泯 于 2018-06-04 设计创作，主要内容包括：本发明提供一种具有自动校正功能的数字锁相回路及其自动校正方法。数字锁相回路包含相位频率检测器、校正电路、频率相位锁定电路以及振荡电路。频率相位锁定电路输出初始控制信号。校正电路判断初始控制信号的初始频率未落入可容许校正误差范围时,校正电路校正初始频率,以输出具有初始校正频率的初始校正信号。频率相位锁定电路判断初始校正频率落入锁定频率范围时,锁定初始校正频率。振荡电路依据初始校正信号以及初始控制信号,输出振荡信号。本发明藉由对制程及环境导致的频率漂移进行自动校正,以提高振荡电路的分辨率。(The present invention provides a kind of digital phase locked loop and its auto-correction method with zero offset capability.Digital phase locked loop includes phase-frequency detector, correcting circuit, Frequency Phase Lock circuit and oscillating circuit.Frequency Phase Lock circuit output initial control signal.When correcting circuit judges that the original frequency of initial control signal does not fall within tolerable correction error range, correcting circuit corrects original frequency, to export the initial calibration signal with initial calibration frequency.When Frequency Phase Lock circuit judges initial calibration frequency falls into locking frequency range, initial calibration frequency is locked.Oscillating circuit is according to initial calibration signal and initial control signal, outputting oscillation signal.The present invention is automatically corrected by frequency drift caused by processing procedure and environment, to improve the resolution ratio of oscillating circuit.)

1. a kind of digital phase locked loop with zero offset capability, characterized by comprising:

Frequency Phase Lock circuit receives correction point control signal from outside, and exports corresponding initial control signal, the frequency The initial calibration frequency and initial phase of rate Phaselocked Circuit tracking initial calibration signal respectively fall in correction locking frequency model It encloses and when locking phase range, locks the initial calibration frequency and the initial phase, the Frequency Phase Lock electricity Road is judged respectively by except signal is by except frequency and by except phase respectively falls in locking frequency range and the locking phase model When enclosing, lock it is described by except frequency and it is described by remove phase；

Correcting circuit connects the Frequency Phase Lock circuit, and the correcting circuit stores tolerable correction error range, described When correcting circuit judges that the original frequency of the initial control signal does not fall within the tolerable correction error range, the correction Original frequency described in circuit calibration has the described first of the initial calibration frequency to generate the initial calibration frequency, and export Beginning correction signal；

Oscillating circuit connects the correcting circuit and the Frequency Phase Lock circuit, and the oscillating circuit is according to described first Beginning correction signal and the initial control signal, with outputting oscillation signal；

Divider connects the oscillating circuit, and the divider receives default divisor value indicative signal from outside, and the default is removed Numerical value signal designation defaults divider value, and the divider is by the frequency of oscillation of the oscillator signal divided by the default divisor Value is described by except signal to generate, and the default divider value is associated in the ratio of reference frequency and the frequency of oscillation；With And

Phase-frequency detector, connects the divider, and the phase-frequency detector detection is described by except frequency and the ginseng Examine frequency frequency difference and the phase difference value for being removed phase and fixed phase, and export the frequency difference and institute Phase difference value is stated to the Frequency Phase Lock circuit, using as judge it is described by except frequency with described by except phase is respectively fallen in The foundation of the locking frequency range and the locking phase range.

2. as described in claim 1 with the digital phase locked loop of zero offset capability, which is characterized in that the locking frequency Range includes coarse adjustment locking frequency range and fine tuning locking frequency range, and the locking phase range includes coarse adjustment locking phase Range and fine tuning locking phase range, the Frequency Phase Lock circuit includes:

Coarse adjustment lock-in circuit connects the phase-frequency detector and the oscillating circuit, the coarse adjustment lock-in circuit storage The coarse adjustment locking frequency range and the coarse adjustment locking phase range, the coarse adjustment lock-in circuit track the initial calibration Frequency is described when being fallen into the coarse adjustment locking frequency range except frequency, carries out frequency locking, and the tracking initial phase or It is described when being fallen into the coarse adjustment locking phase range except phase, locking phase is carried out, and exports corresponding coarse adjustment locking signal；And

Fine tuning lock-in circuit connects the phase-frequency detector and the oscillating circuit, the fine tuning lock-in circuit storage The fine tuning locking frequency range and the fine tuning locking phase range, the fine tuning lock-in circuit track the initial calibration Frequency is described when being fallen into the fine tuning locking frequency range except frequency, carries out frequency locking, and the tracking initial phase or It is described when being fallen into the fine tuning locking phase range except phase, locking phase is carried out, and exports corresponding fine tuning locking signal.

3. as claimed in claim 2 with the digital phase locked loop of zero offset capability, which is characterized in that described to have automatically The digital phase locked loop of calibration function also includes encoder, connect the coarse adjustment lock-in circuit, the fine tuning lock-in circuit and The oscillating circuit, the encoder encode the coarse adjustment locking signal and the fine tuning locking signal, with output locking control Signal processed to the oscillating circuit, the oscillating circuit exports another oscillator signal according to the lock control signal.

4. as described in claim 1 with the digital phase locked loop of zero offset capability, which is characterized in that the phase frequency Detector detects described by except signal is by except frequency and the reference frequency are by except frequency difference；

The correcting circuit reception is described to be removed frequency difference, is judged accordingly described by except frequency does not fall within the tolerable correction When error range, the correcting circuit correction is described to be removed frequency, and is exported corresponding by except correction signal includes by except correction Frequency；

When being fallen into the locking frequency range except correction frequency described in the Frequency Phase Lock circuit judges, the frequency phase Position lock-in circuit locking is described to be removed correction frequency, and exports corresponding lock control signal；

The oscillating circuit according to the lock control signal and it is described by remove correction signal, to export another oscillator signal.

5. a kind of auto-correction method of digital phase locked loop is suitable for having zero offset capability as described in claim 1 Digital phase locked loop, which is characterized in that the auto-correction method of the digital phase locked loop comprises the steps of:

(a) the Frequency Phase Lock circuit is utilized, the initial control signal is exported；

(b) correcting circuit is utilized, judges that the original frequency of the initial control signal does not fall within the tolerable school When positive error range, the original frequency is corrected to generate the initial calibration frequency using the correcting circuit, and export tool There is the initial calibration signal of the initial calibration frequency；

(c) the Frequency Phase Lock circuit is utilized, tracks whether the initial calibration frequency falls into the correction locking frequency Range if so, locking the initial calibration frequency, and then performs the next step rapid if it is not, repeating step (b)；

(d) oscillating circuit is utilized, according to the initial calibration signal and the initial control signal, to export the vibration Swing signal；

(e) divider is utilized, it is described by except signal to export by the oscillator signal divided by the default divider value；

(f) phase-frequency detector is utilized, is detected described by except the described of signal is removed frequency and the reference frequency The frequency difference, and the detection phase difference value for being removed phase and the fixed phase by except signal；

(g) the Frequency Phase Lock circuit is utilized, is tracked according to the frequency difference described by except whether frequency falls into institute Locking frequency range is stated, if it is not, keeping track by except frequency, if so, locking is described to be removed frequency, and is then performed the next step Suddenly；And

(h) the Frequency Phase Lock circuit is utilized, is tracked according to the phase difference value described by except whether phase falls into institute Locking phase range is stated, if it is not, keeping track described by except phase, if so, locking is described to be removed phase, and then executes step (d)。

6. the auto-correction method of digital phase locked loop as claimed in claim 5, which is characterized in that utilizing the frequency phase After position lock-in circuit tracks the step of initial calibration frequency falls into the correction locking frequency range (c), also include with Lower step:

Using the Frequency Phase Lock circuit, whether the initial phase for tracking the initial control signal falls into the lock Phase bit range if so, locking the initial phase, and then executes step (d), if it is not, repeating this step.

7. the auto-correction method of digital phase locked loop as claimed in claim 5, which is characterized in that the digital phase locked loop Auto-correction method also comprise the steps of:

Using coarse adjustment lock-in circuit, track whether the initial calibration frequency falls into coarse adjustment locking frequency range, if it is not, to described Initial calibration frequency is persistently tracked, if so, locking the initial calibration frequency, and is then performed the next step rapid；

Using the coarse adjustment lock-in circuit, whether tracking is described is fallen into the coarse adjustment locking frequency range except frequency, if it is not, right It is described to be persistently tracked except frequency, if so, being tracked with coarse adjustment described by except frequency carries out frequency locking, and export corresponding Coarse adjustment locking signal is to the oscillating circuit；And

Using fine tuning lock-in circuit, whether tracking is described is fallen into the fine tuning locking frequency range except frequency, if it is not, to described It is persistently tracked except frequency, if so, tracking with fine tuning described by except frequency carries out frequency locking, and exports corresponding fine tuning Locking signal is to the oscillating circuit.

8. the auto-correction method of digital phase locked loop as claimed in claim 7, which is characterized in that locked using the coarse adjustment After determining the step of circuit tracking initial calibration frequency falls into the coarse adjustment locking frequency range, the digital phase locked loop Auto-correction method also comprise the steps of:

Using the fine tuning lock-in circuit, track whether the initial calibration frequency falls into the fine tuning lock-in range, if it is not, right The initial calibration frequency is persistently tracked, if so, carrying out frequency locking, and output pair with the initial calibration frequency tracked The fine tuning locking signal answered is to the oscillating circuit.

9. the auto-correction method of digital phase locked loop as claimed in claim 5, which is characterized in that the digital phase locked loop Auto-correction method also comprise the steps of:

Using coarse adjustment lock-in circuit, track whether the initial phase falls into coarse adjustment locking phase range, if it is not, to described initial Phase is persistently tracked, if so, locking the initial phase, and is then performed the next step rapid；

Using the coarse adjustment lock-in circuit, whether tracking is described is fallen into the coarse adjustment locking phase range except phase, if it is not, right It is described to be persistently tracked except phase, if so, it is described by except phase carries out locking phase with what is tracked, and export corresponding coarse adjustment Locking signal is to the oscillating circuit；And

Using fine tuning lock-in circuit, whether tracking is described is fallen into the fine tuning locking phase range except phase, if it is not, to described It is persistently tracked except phase, if so, it is described by except phase carries out locking phase with what is tracked, and export corresponding fine tuning locking Signal is to the oscillating circuit.

10. the auto-correction method of digital phase locked loop as claimed in claim 9, which is characterized in that place utilizes described thick Lock-in circuit is adjusted, after tracking the step of initial phase falls into the coarse adjustment locking phase range, the digital servo-control is returned The auto-correction method on road also comprises the steps of:

Using the fine tuning lock-in circuit, track whether the initial phase falls into the fine tuning locking phase range, if it is not, right The initial phase is persistently tracked, if so, carrying out locking phase with the initial phase tracked, and is exported corresponding described Fine tuning locking signal is to the oscillating circuit.

11. the auto-correction method of digital phase locked loop as claimed in claim 7, which is characterized in that locked in the coarse adjustment Signal and the fine tuning locking signal are exported to before the oscillating circuit, the auto-correction method of the digital phase locked loop Also comprise the steps of:

Using encoder, the coarse adjustment locking signal and the fine tuning locking signal are encoded, to export lock control signal extremely The oscillating circuit；And

Using the oscillating circuit, according to the lock control signal and the initial calibration signal, to export another oscillation Signal.

12. the auto-correction method of digital phase locked loop as claimed in claim 5, which is characterized in that the digital servo-control returns The auto-correction method on road further includes following steps:

Using the phase-frequency detector, detect described by described by being removed except frequency and the reference frequency except signal Frequency difference；

Frequency difference is removed using correcting circuit reception is described, is judged accordingly described by except frequency does not fall within described may be allowed When correction error range, frequency is removed using correcting circuit correction is described, and export to have to be removed and correct being removed for frequency Correction signal；

Using the Frequency Phase Lock circuit, judge it is described when being fallen into the locking frequency range except correction frequency, it is described The locking of Frequency Phase Lock circuit is described to be removed correction frequency, and exports corresponding lock control signal；

Using the oscillating circuit, according to the lock control signal and it is described removed correction signal, to export another oscillation Signal.

Technical field

The invention relates to a kind of digital phase locked loops, and in particular to a kind of number with zero offset capability Word phase-locked loop and its auto-correction method.

Background technique

With the progress of electronics technology, electronic product has become tool indispensable in for people's lives.Such as into The communication product of row information exchange carries out information exchange with the external world by communication product, all must daily in people's life The work to be executed.In electronic communication product, most common is exactly PLL device.However, in phase locked loop system, The frequency of oscillator can be influenced by factors such as temperature in processing procedure and environment and be drifted about.Since traditional phase-locked loop does not have Have a zero offset capability and can not self-correction need to pass through additional board to solve the problems, such as this frequency drift and carry out frequency Correction, set based on processing procedure drift consider frequency domain, if or even resolution ratio need to be promoted, also need increase control digit, cause Higher cost need to be spent, it is inconvenient to use, and it is bad to correct efficiency.

Summary of the invention

For the missing for solving above-mentioned well-known technique, it is an object of the invention to it is exemplary provide it is a kind of have automatically correct function The digital phase locked loop of energy includes:

Frequency Phase Lock circuit receives correction point control signal from outside, and exports corresponding initial control signal, institute The initial calibration frequency and initial phase for stating Frequency Phase Lock circuit tracking initial calibration signal respectively fall in correction locking frequency When rate range and locking phase range, the initial calibration frequency and the initial phase, the frequency plot lock are locked Determine circuit to be judged respectively by except signal is by except frequency and by except phase respectively falls in locking frequency range and the locking phase Position range when, lock it is described by except frequency and it is described by remove phase；

Correcting circuit connects the Frequency Phase Lock circuit, and the correcting circuit stores tolerable correction error range, It is described when the correcting circuit judges that the original frequency of the initial control signal does not fall within the tolerable correction error range Correcting circuit corrects the original frequency to generate the initial calibration frequency, and exports the institute with the initial calibration frequency State initial calibration signal；

Oscillating circuit connects the correcting circuit and the Frequency Phase Lock circuit, and the oscillating circuit is according to institute Initial calibration signal and the initial control signal are stated, to export the oscillator signal；

Divider connects the oscillating circuit, and the divider receives default divisor value indicative signal from outside, described silent Recognize divisor value indicative signal instruction default divider value, the divider is by the frequency of oscillation of the oscillator signal divided by the default Divider value is described by except signal to generate, and the default divider value is associated in the ratio of reference frequency and the frequency of oscillation Example；And

Phase-frequency detector connects the divider, and the phase-frequency detector detection is described to be removed frequency and institute State reference frequency frequency difference and it is described by remove phase and fixed phase phase difference value, and export the frequency difference with And the phase difference value is to the Frequency Phase Lock circuit, using described by except frequency and described by except phase is distinguished as judging Fall into the foundation of the locking frequency range and the locking phase range.

Preferably, the locking frequency range includes coarse adjustment locking frequency range and fine tuning locking frequency range, described Locking phase range includes coarse adjustment locking phase range and fine tuning locking phase range, the Frequency Phase Lock circuit packet Contain:

Coarse adjustment lock-in circuit connects the phase-frequency detector and the oscillating circuit, the coarse adjustment lock-in circuit The coarse adjustment locking frequency range and the coarse adjustment locking phase range are stored, the coarse adjustment lock-in circuit tracking is described initial Correction frequency is described when being fallen into the coarse adjustment locking frequency range except frequency, carries out frequency locking, and the tracking initial phase Position is described when being fallen into the coarse adjustment locking phase range except phase, carries out locking phase, and exports corresponding coarse adjustment locking signal； And

Fine tuning lock-in circuit connects the phase-frequency detector and the oscillating circuit, the fine tuning lock-in circuit The fine tuning locking frequency range and the fine tuning locking phase range are stored, the fine tuning lock-in circuit tracking is described initial Correction frequency is described when being fallen into the fine tuning locking frequency range except frequency, carries out frequency locking, and the tracking initial phase Position is described when being fallen into the fine tuning locking phase range except phase, carries out locking phase, and exports corresponding fine tuning locking signal.

Preferably, the digital phase locked loop with zero offset capability further includes encoder, connects the coarse adjustment lock Determine circuit, the fine tuning lock-in circuit and the oscillating circuit, the encoder encodes the coarse adjustment locking signal and institute Fine tuning locking signal is stated, to export lock control signal to the oscillating circuit, the oscillating circuit is controlled according to the locking Signal exports another oscillator signal.

Preferably, the phase-frequency detector detects the quilt for being removed frequency and the reference frequency by except signal Except frequency difference；

The correcting circuit receive it is described removed frequency difference, judge described described to be allowed school except frequency is not fallen within accordingly When positive error range, the correcting circuit correction is described to be removed frequency, and is exported corresponding by except correction signal includes by except school Positive frequency；

When being fallen into the locking frequency range except correction frequency described in the Frequency Phase Lock circuit judges, the frequency The locking of rate Phaselocked Circuit is described to be removed correction frequency, and exports corresponding lock control signal；

The oscillating circuit according to the lock control signal and it is described removed correction signal, believed with exporting another oscillation Number.

A kind of auto-correction method of digital phase locked loop provided by the invention is suitable for the digital phase locked loop, from Dynamic bearing calibration comprises the steps of:

(a) the Frequency Phase Lock circuit is utilized, the initial control signal is exported；

(b) correcting circuit is utilized, judges that the original frequency of the initial control signal can hold described in not falling within Perhaps when correction error range, the original frequency is corrected to generate the initial calibration frequency using the correcting circuit, and defeated Provide the initial calibration signal of the initial calibration frequency；

(c) the Frequency Phase Lock circuit is utilized, tracks whether the initial calibration frequency falls into the correction locking Frequency range if so, locking the initial calibration frequency, and then performs the next step rapid if it is not, repeating step (b)；

(d) oscillating circuit is utilized, according to the initial calibration signal and the initial control signal, to export State oscillator signal；

(e) divider is utilized, it is described by except letter to export by the oscillator signal divided by the default divider value Number；

(f) phase-frequency detector is utilized, is detected described by except the described of signal is removed frequency with described with reference to frequency The frequency difference of rate, and the detection phase difference for being removed phase and the fixed phase by except signal Value；

(g) the Frequency Phase Lock circuit is utilized, is tracked according to the frequency difference described by except whether frequency falls Enter the locking frequency range, if it is not, keeping track by except frequency, if so, locking is described to be removed frequency, and then executes next Step；And

(h) the Frequency Phase Lock circuit is utilized, is tracked according to the phase difference value described by except whether phase falls Enter the locking phase range, if it is not, keeping track described by except phase, if so, locking is described to be removed phase, and then executes Step (d).

Preferably, the auto-correction method of the digital phase locked loop is tracked using the Frequency Phase Lock circuit The initial calibration frequency was fallen into after the step of correction locking frequency range (c), further included following steps:

Using the Frequency Phase Lock circuit, whether the initial phase for tracking the initial control signal falls into institute Locking phase range is stated, if so, locking the initial phase, and then step (d) is executed, if it is not, repeating this step.

Preferably, the auto-correction method of the digital phase locked loop, further includes following steps:

Using coarse adjustment lock-in circuit, track whether the initial calibration frequency falls into coarse adjustment locking frequency range, if it is not, right The initial calibration frequency is persistently tracked, if so, locking the initial calibration frequency, and is then performed the next step rapid；

Using the coarse adjustment lock-in circuit, whether tracking is described is fallen into the coarse adjustment locking frequency range except frequency, if It is no, it is persistently tracked to described except frequency, if so, being tracked with coarse adjustment described by except frequency carries out frequency locking, and is exported Corresponding coarse adjustment locking signal is to the oscillating circuit；And

Using fine tuning lock-in circuit, whether tracking is described is fallen into the fine tuning locking frequency range except frequency, if it is not, right It is described to be persistently tracked except frequency, if so, being tracked with fine tuning described by except frequency carries out frequency locking, and export corresponding Fine tuning locking signal is to the oscillating circuit.

Preferably, the auto-correction method of the digital phase locked loop, using described in coarse adjustment lock-in circuit tracking Initial calibration frequency was fallen into after the step of coarse adjustment locking frequency range, further included following steps:

Using the fine tuning lock-in circuit, track whether the initial calibration frequency falls into the fine tuning lock-in range, if It is no, the initial calibration frequency is persistently tracked, if so, frequency locking is carried out with the initial calibration frequency tracked, and The corresponding fine tuning locking signal is exported to the oscillating circuit.

Preferably, the auto-correction method of the digital phase locked loop, further includes following steps:

Using coarse adjustment lock-in circuit, track whether the initial phase falls into coarse adjustment locking phase range, if it is not, to described Initial phase is persistently tracked, if so, locking the initial phase, and is then performed the next step rapid；

Using the coarse adjustment lock-in circuit, whether tracking is described is fallen into the coarse adjustment locking phase range except phase, if It is no, it is persistently tracked to described except phase, if so, it is described by except phase carries out locking phase with what is tracked, and export correspondence Coarse adjustment locking signal to the oscillating circuit；And

Using fine tuning lock-in circuit, whether tracking is described is fallen into the fine tuning locking phase range except phase, if it is not, right It is described to be persistently tracked except phase, if so, it is described by except phase carries out locking phase with what is tracked, and export corresponding fine tuning Locking signal is to the oscillating circuit.

Preferably, the auto-correction method of the digital phase locked loop is utilizing the coarse adjustment lock-in circuit, described in tracking Initial phase was fallen into after the step of coarse adjustment locking phase range, further included following steps:

Using the fine tuning lock-in circuit, track whether the initial phase falls into the fine tuning locking phase range, if It is no, the initial phase is persistently tracked, if so, carrying out locking phase with the initial phase tracked, and exports correspondence The fine tuning locking signal to the oscillating circuit.

Preferably, the auto-correction method of the digital phase locked loop, in the coarse adjustment locking signal and the fine tuning Locking signal is exported to before the oscillating circuit, further includes following steps:

Using encoder, the coarse adjustment locking signal and the fine tuning locking signal are encoded, control letter is locked with output Number to the oscillating circuit；And

It is another to export according to the lock control signal and the initial calibration signal using the oscillating circuit Oscillator signal.

Preferably, the auto-correction method of the digital phase locked loop, further includes following steps:

Using the phase-frequency detector, detect described by except the described of signal is removed frequency and the reference frequency Removed frequency difference；

Frequency difference is removed using correcting circuit reception is described, is judged accordingly described by except frequency does not fall within the appearance Perhaps when correction error range, frequency is removed using correcting circuit correction is described, and export to have and removed the quilt for correcting frequency Except correction signal；

Using the Frequency Phase Lock circuit, judge it is described when being fallen into the locking frequency range except correction frequency, The Frequency Phase Lock circuit locking is described to be removed correction frequency, and exports corresponding lock control signal；

Using the oscillating circuit, according to the lock control signal and it is described removed correction signal, it is another to export Oscillator signal.

As described above, the digital phase locked loop and its auto-correction method provided by the invention with zero offset capability, It, can be for example in starting number when oscillating circuit is influenced by the various factors in processing procedure and environment and leads to the frequency drift of output When word phase-locked loop, drift frequency and phase are automatically corrected, without carrying out specifying calibration by additional board, in oscillating circuit Limited control digit under, the resolution ratio for improving oscillator can be optimized, and can effectively save cost.

Detailed description of the invention

Fig. 1 is that the digital phase locked loop with zero offset capability of first embodiment of the invention executes original frequency correction Block diagram.

Fig. 2 is that the digital phase locked loop with zero offset capability of second embodiment of the invention executes original frequency correction Block diagram.

Fig. 3 is the frequency of oscillation of the digital phase locked loop with zero offset capability of third embodiment of the invention to control The curve graph of signal.

Fig. 4 is the automatically correcting of the digital phase locked loop with zero offset capability of fourth embodiment of the invention, coarse adjustment Signal schematic representation under tracking and fine tuning tracking mode.

Fig. 5 is that the digital phase locked loop with zero offset capability of fifth embodiment of the invention executes original frequency and vibration Swing the block diagram of the correction of frequency.

Fig. 6 is that the auto-correction method of the digital phase locked loop of sixth embodiment of the invention executes the step of original frequency correction Rapid flow diagram.

Fig. 7 is execution original frequency and the oscillation of the auto-correction method of the digital phase locked loop of seventh embodiment of the invention The step flow diagram of frequency correction.

Specific embodiment

Various exemplary embodiments will be more fully described referring to alterations below, shown in alterations Exemplary embodiments.However, concept of the present invention may be embodied in many different forms, and it should not be construed as limited by institute herein The exemplary embodiments of elaboration.Specifically, providing these exemplary embodiments makes the present invention that will be detailed and complete, and will The scope of concept of the present invention is sufficiently conveyed to those who familiarize themselves with the technology.In all schemas, similar number indicates similar assembly always.

Referring to Fig. 1, it is that the digital phase locked loop with zero offset capability according to a first embodiment of the present invention is held The block diagram of row original frequency correction.As shown in Figure 1, the present embodiment has the digital phase locked loop of zero offset capability, include Phase-frequency detector 10, correcting circuit 20, Frequency Phase Lock circuit 30, oscillating circuit 40 and divider 50, wherein phase Bit frequency detector 10 connects correcting circuit 20, Frequency Phase Lock circuit 30 and divider 50, the connection frequency of correcting circuit 20 Rate Phaselocked Circuit 30, oscillating circuit 40 connect correcting circuit 20, Frequency Phase Lock circuit 30 and divider 50.

Firstly, Frequency Phase Lock circuit 30 can receive correction point control signal Cpc, this check point from external electronic Control signal Cpc can have the setpoint frequency of corresponding setting code.Frequency Phase Lock circuit 30 can be then according to check point control Signal Cpc processed, to export the initial control signal Ctrl with original frequency.

Correcting circuit 20 can be stored in advance one and allow correction error range, this allows correction error range to correspond to above-mentioned setting Frequency.Ideally, when correcting circuit 20 judges that original frequency falls into this and allows correction error range, correcting circuit 20 is not required to carry out Frequency correction.

It should be noted, however, that digital phase locked loop Chang Yin is by such as temperature shadow of the various factors in processing procedure and environment It rings, and leads to frequency drift.Therefore, in the digital phase locked loop of the present embodiment, it is provided with correcting circuit 20, is stored with and allows school Positive error range.When initial frequency shifts and amplitude of fluctuation it is excessive and cause not falling within allow correction error range when, school Positive circuit 20 can be corrected the original frequency of the initial control signal Ctrl from Frequency Phase Lock circuit 30, to generate Initial calibration frequency, and the initial calibration signal Tinit with this initial calibration frequency is exported, such as represent just with logical bit value Beginning correction signal Tinit is exported to Frequency Phase Lock circuit 30.

Frequency Phase Lock circuit 30 is also referred to as showing correction from the received correction point control signal Cpc of external electronic Locking frequency range and locking phase range.In implementation, when Frequency Phase Lock circuit 30 is received from correcting circuit 20 Initial calibration signal Tinit when, the initial calibration frequency of the traceable initial calibration signal Tinit of Frequency Phase Lock circuit 30 Whether correction locking frequency range is fallen into.Until when the initial calibration frequency tracked fall into correction locking frequency range when, frequency 30 lockable initial calibration frequency of rate Phaselocked Circuit.Wherein, correction locking frequency range can be greater than or equal to following applications In the locking frequency range for being removed frequency.

And after locking initial calibration frequency, the traceable initial calibration signal Tinit's of Frequency Phase Lock circuit 30 is first Whether beginning phase falls into locking phase range.Until when the initial phase tracked falls into locking phase range, frequency plot 30 lockable initial phase of lock-in circuit.In the present embodiment, it only corrects original frequency and does not correct initial phase, therefore track And locking initial phase.It should be understood that, if there is demand, can be also corrected to initial phase to generate initial calibration phase in practice Position, and track and lock the initial calibration phase fallen within the scope of locking phase.

Oscillating circuit 40 is numerically-controlled oscillator in the present embodiment, and the vibration of different kenels can be actually selected according to demand Swing device, such as voltage controlled oscillator etc., herein only for example, being not limited.Oscillating circuit 40 can be according to from correcting circuit 20 initial calibration signal Tinit (and initial control signal Ctrl of Frequency Phase Lock circuit 30), it is corresponding to export Oscillator signal Sdco.This oscillator signal Sdco can then feedback to phase-frequency detector 10.

Divider 50 can be integer divider or fractional divider, to receive and be stored in advance as integer or fractional value Default divider value.As in the present embodiment, divider 50 is applied to the division arithmetic of frequency, therefore is referred to alternatively as frequency eliminator again.It is real Shi Shang, divider 50 can receive a default divisor value indicative signal Sdin from external electronic.The vibration that oscillating circuit 40 exports When passing through divider 50 during swinging signal Sdco feedback to phase-frequency detector 10, divider 50 can be by oscillator signal The frequency of oscillation of Sdco is removed frequency divided by default divider value, to obtain.Then, the output of divider 50 has the quilt for being removed frequency Except signal Sdiv to phase-frequency detector 10.

By above-mentioned frequency elimination operation, the high-frequency signal that oscillating circuit 40 exports can be downconverted to phase-frequency detector 10 can The frequency of operation.It should be understood that the size of default divider value and the number of execution division arithmetic, may depend on phase-frequency detector The multiple proportion between frequency of oscillation that 10 operable reference frequency Fref and oscillating circuit 40 are exported.

Further, phase-frequency detector 10 can receive reference frequency Fref and fixed phase Pref from outside.Phase Frequency detector 10 receive from divider 50 by except signal Sdiv when, can detect by except signal Sdiv by except frequency with The frequency difference Fdivd of reference frequency Fref, and output frequency difference Fdivd is to Frequency Phase Lock circuit 30.Then, frequency Phaselocked Circuit 30 can lock when judgement/tracking is fallen within the scope of locking frequency except frequency according to this frequency difference Fdivd It is fixed to be removed frequency.

After locking is by except frequency, phase-frequency detector 10 is detectable by except signal Sdiv is by except phase and with reference to phase The phase difference value Pdivd of position Pref, and output phase difference Pdivd is to Frequency Phase Lock circuit 30.Then, frequency plot is locked Circuit 30 is determined according to this phase difference value Pdivd, and when judgement/tracking is fallen within the scope of locking phase except phase, lockable is removed Phase.

Referring to Fig. 2, it is that the digital phase locked loop with zero offset capability according to a second embodiment of the present invention is held The block diagram of row original frequency correction.It is identical with the first embodiment place, no longer this is repeated.As shown in Fig. 2, the present embodiment has The digital phase locked loop of zero offset capability includes phase-frequency detector 10, correcting circuit 20, Frequency Phase Lock circuit 30, oscillating circuit 40 and divider 50.Frequency Phase Lock circuit 30 includes coarse adjustment lock-in circuit 31, fine tuning lock-in circuit 32 And encoder 33, wherein coarse adjustment lock-in circuit 31 and fine tuning lock-in circuit 32 all connect phase-frequency detector 10, correction Circuit 20 and encoder 33.Encoder 33 connects oscillating circuit 40.Phase-frequency detector 10 and oscillating circuit 40 all connect Connect correcting circuit 20 and divider 50.

Frequency Phase Lock circuit 30 can receive correction point control signal Cpc from external electronic, can indicate coarse adjustment Locking frequency range and coarse adjustment locking phase range are provided to the storage of coarse adjustment lock-in circuit 31, and can indicate fine tuning locking frequency Range and fine tuning locking phase range are provided to the storage of fine tuning lock-in circuit 32.For example, coarse adjustment locking frequency range Upper limit value and lower limit value may respectively be ± the 5% of setpoint frequency, and the upper limit value of fine tuning locking frequency range can divide with lower limit value Not Wei setpoint frequency ± 1%, herein only for example, being not limited.

In implementation, 31 judgements of coarse adjustment lock-in circuit/tracking initial calibration signal Tinit initial calibration frequency falls into coarse adjustment When locking frequency range, frequency locking is carried out with the initial calibration frequency that coarse adjustment tracks.At this point, coarse adjustment lock-in circuit 31 is according to coarse adjustment The result of tracking exports coarse adjustment locking signal Clocked to oscillating circuit 40.In addition, optionally, coarse adjustment lock-in circuit 31 Coarse adjustment locking signal Clocked is exported to fine tuning lock-in circuit 32, when indicating that fine tuning lock-in circuit 32 is real-time or passes through one section Between after start carry out fine tuning tracking.

Optionally, fine tuning lock-in circuit 32 can carry out fine tuning to the initial calibration frequency of initial calibration signal Tinit Tracking.Until the initial calibration frequency when the judgement of fine tuning lock-in circuit 32 falls into fine tuning locking frequency range, tracked with fine tuning Rate carries out frequency locking.The result that fine tuning lock-in circuit 32 can be tracked according to fine tuning exports corresponding fine tuning locking signal Flocked extremely Encoder 33.

Then, encoder 33 can encode coarse adjustment locking signal Clocked and fine tuning locking signal Flocked, To export corresponding lock control signal Ctrlok.

Then, oscillating circuit 40 can be corresponded to according to initial calibration signal Tinit and lock control signal Ctrlok output Oscillator signal Sdco.The oscillator signal Sdco of oscillating circuit 40 is generated by 50 frequency elimination of divider by except signal Sdiv is fed back to Phase-frequency detector 10, to be removed frequency and reference frequency except signal Sdiv by the detection of phase-frequency detector 10 The frequency difference Fdivd of Fref, and detection is by the phase difference value for being removed phase and fixed phase Pref except signal Sdiv Pdivd。

Tracking and locking operation similar to above-mentioned initial calibration frequency and initial phase, will be described below by except signal The specific embodiment of Sdiv removed frequency and removed phase.

Coarse adjustment lock-in circuit 31 is according to frequency difference Fdivd, when judging to be fallen within the scope of coarse adjustment locking frequency except frequency, Lockable is removed frequency, and according to phase difference value Pdivdd, can when judging to be fallen within the scope of coarse adjustment locking frequency except phase Locking is removed phase.When fine tuning lock-in circuit 32 receive coarse adjustment lock-in circuit 31 or from other circuits representative coarse adjustment tracking After the indication signal of completion, fine tuning lock-in circuit 32 can be to being chased after except frequency and except signal Sdiv except phase carries out fine tuning Track.Until being tracked with fine tuning when 32 trackings of fine tuning lock-in circuit/judgement is fallen into fine tuning locking frequency range except frequency Frequency locking is carried out except frequency, and when tracking/judgement is fallen into fine tuning locking phase range except phase, is tracked with fine tuning Locking phase is carried out except phase.

Coarse adjustment lock-in circuit 31 and fine tuning lock-in circuit 32 can be according to tracking and lockings as a result, to export correspondence respectively Coarse adjustment locking signal Clocked and fine tuning locking signal Flocked to encoder 33.Coarse adjustment is locked by encoder 33 Signal Clocked and fine tuning locking signal Flocked are encoded, to export corresponding lock control signal Ctrlok to vibration Swing circuit 40.Finally, oscillating circuit 40 is according to lock control signal Ctrlok (and initial calibration signal Tinit), with output Corresponding another oscillator signal.

Referring to Fig. 3, it is the oscillation of the digital phase locked loop with zero offset capability of third embodiment of the invention Curve graph of the frequency to control signal.As shown in figure 3, the longitudinal axis is frequency of oscillation Fout, horizontal axis is initial control signal Ctrl.

Correcting circuit can be stored and be tabled look-up, and multiple codes can be had by tabling look-up, comprising minimum code CodeMin as shown in Figure 3, Maximum code CodeMax, and the setting code between minimum code CodeMin and maximum code CodeMax CodePoint.In addition, the multiple setpoint frequencies for respectively corresponding multiple codes can be had by tabling look-up, corresponding initial control signal Ctrl Original frequency.Curve Ctrim as shown in Figure 3 represents different multiple codes and respectively corresponds different multiple setpoint frequencies, Wherein setting code CodePoint corresponds to setpoint frequency Ftrim.The positive slope of curve Ctrim as shown in Figure 3 it can be seen that, In In the present embodiment, code value is directly proportional to the size of frequency values, in fact, vice versa.

Correcting circuit can according to Frequency Phase Lock circuit the frequency of setting indicated by received correction point control signal Cpc Rate Ftrim from the middle wherein code for searching corresponding setpoint frequency Ftrim of tabling look-up, and is obtained and corresponding is allowed correction error model It encloses.In operation, when to judge that original frequency is fallen into acquired when allowing correction error range for correcting circuit, this means that initial frequency Rate is equal to when allowing the upper limit value of correction error range, lower limit value or numerical value between upper limit value and lower limit value, be not required into Line frequency correction, curve C2 as shown in Figure 3.

On the contrary, when to judge that original frequency is not fallen within acquired when allowing correction error range for correcting circuit, such as Fig. 3 institute The curve C1 shown indicates that original frequency is more than to allow correction error range and curve C3 to indicate that original frequency is lower than to allow to correct Error range, correcting circuit are corrected original frequency based on acquired setpoint frequency, the school if obtaining different codes Just to different correspondence setpoint frequencies.For example, as shown in figure 3, curve C1 and curve C3 are corrected to curve Ctrim.

Referring to Fig. 4, it is the automatic of the digital phase locked loop with zero offset capability of fourth embodiment of the invention Signal schematic representation under correction, coarse adjustment tracking and fine tuning tracking mode.

As shown in figure 4, the operation mode of digital phase locked loop be broadly divided into automatically correct, coarse adjustment tracking and fine tuning tracking mould Formula.Firstly, can provide reset signal RST when starting digital phase locked loop, to reset digital phase locked loop.Then, digital phase-locking Phase circuit, which enters, automatically corrects mode, is corrected to the original frequency of initial control signal, also can be further to vibration in practice Signal is swung to be corrected.

After the correction that correcting circuit completes initial control signal, correcting state indication signal as shown in Figure 4 CaliDone switchs to high level from low level, and display has corrected completion, and correcting circuit can produce to have and represent correction completion Code CailGood initial calibration signal Tinit.

Then, digital phase locked loop enters coarse adjustment tracking mode, includes coarse adjustment track phase and coarse adjustment locked stage.In Under coarse adjustment track phase, the coarse adjustment lockin signal Clocked of coarse adjustment lock-in circuit output is low level, represents coarse adjustment lock-in circuit Coarse adjustment tracking is being carried out to the initial calibration frequency of the initial calibration signal Tinit of correcting circuit output.It is tracked until working as When initial calibration frequency is fallen within the scope of coarse adjustment locking frequency, into coarse adjustment locked stage, coarse adjustment lock-in circuit is exported at this time Coarse adjustment lockin signal Clocked switchs to high level output to encoder from low level.

Mode is tracked fine tuning after coarse adjustment locking after a period of time, can be entered, comprising fine tuning track phase and carefully Adjust locked stage.Under thin track phase, the fine tuning lockin signal Flocked of fine tuning lock-in circuit output is low level, is represented Fine tuning lock-in circuit in digital phase locked loop is carrying out fine tuning tracking to initial calibration frequency.Initial school is tracked until working as When positive frequency is fallen within the scope of fine tuning locking frequency, into fine tuning locked stage, fine tuning lock-in circuit exports high level at this time Fine tuning lockin signal Flocked is to encoder.

Finally, the place value of coarse adjustment lockin signal Clocked and fine tuning lockin signal Flocked are encoded into tool by encoder The lock control signal Ctrlok of bit streams, the coarse adjustment comprising representing coarse adjustment locking frequency encodes ClockedCode, and represents The fine tuning of fine tuning locking frequency encodes FlockedCode.

Referring to Fig. 5, the digital phase locked loop with zero offset capability that it is fifth embodiment of the invention executes just Begin to control signal and by the block diagram of the frequency correction except signal.As shown in figure 5, in the present embodiment, in addition to such as above-mentioned implementation Example the original frequency of initial control signal Ctrl can be corrected it is outer, also can further to by except signal by except frequency into Row correction, and lock and removed frequency after correction.It is described in detail below for by the frequency calibration except signal.

In oscillating circuit 40 according to initial control signal Tinit outputting oscillation signal Sdco1, and pass through 50 frequency elimination of divider And after acquirement is fed back to phase-frequency detector 10 except signal Sdiv, phase-frequency detector 10 is detectable to be removed signal Sdiv The difference for being removed frequency and reference frequency Fref, with output by except frequency difference Fdivd.Correcting circuit 20 receives and is removed frequency Difference Fdivd, track accordingly by except signal Sdiv by except frequency do not fall within allow correction error range when, to by except frequency into Row correction is removed correction signal Tdiv1 except correction frequency to export to have.

Coarse adjustment lock-in circuit 31 and fine tuning lock-in circuit 32 can receive coarse adjustment locking frequency range and fine tuning lock respectively Determine frequency range.Coarse adjustment lock-in circuit 31 and fine tuning lock-in circuit 32 are sequentially tracked by except correction signal Tdiv1 is by except school When positive frequency falls into coarse adjustment locking frequency range and fine tuning locking frequency range, coarse adjustment locking signal Clocked1 is exported respectively And fine tuning locking signal Flocked1.Encoder 33 encodes coarse adjustment lockin signal Clocked1 and fine tuning lockin signal Flocked1, to export lock control signal Ctrlok1.

Finally, oscillating circuit 40 is according to lock control signal Ctrlok1 and is removed correction signal Tdiv1, it is another to export One oscillator signal Sdco2.This another oscillator signal Sdco2 and other oscillator signals of subsequent generation can be used similar to above-mentioned Mode is realized by except the correction of frequency, tracking and locking operation.

Referring to Fig. 6, the auto-correction method that it is the digital phase locked loop of sixth embodiment of the invention executes initial control The step flow diagram of the frequency correction of signal and oscillator signal processed.As shown in fig. 6, the digital phase locked loop of the present embodiment Auto-correction method is suitable for above-mentioned digital phase locked loop, may include following steps S601~S629.

Step S601: resetting numerical digit phase-locked loop.

Step S603: utilizing Frequency Phase Lock circuit, receives correction point control signal from outside, and exports corresponding first Begin control signal.

Step S605: utilizing correcting circuit, and whether judgement/tracking initial control signal original frequency falls into tolerable school Positive error range, if it is not, executing step S607: original frequency is corrected using correcting circuit, it is initial after correction Frequency (being referred to herein as convenience of description, initial calibration frequency) falls into tolerable correction error range, and output has initial school The initial calibration signal of positive frequency, and step S609 is then executed, if so, without correction, directly execution step S609.

Step S609: coarse adjustment lock-in circuit is utilized, judges that the initial calibration frequency of initial calibration signal (is corrected When) or original frequency (when not being corrected) whether fall into correction locking frequency range (can be replaced it is following be applied to removed The coarse adjustment locking frequency range of frequency), if it is not, step S607 is repeated, if so, executing step S611: locking using coarse adjustment Circuit, the initial calibration frequency or original frequency that locking coarse adjustment tracks, and then execute step S613.Wherein, correction locking Frequency range is applied to can have bigger or identical value range by the coarse adjustment locking frequency range except frequency compared to following.

Optionally, the auto-correction method of the digital phase locked loop of the present embodiment more may include the following steps: tracking Whether the initial phase of initial control signal falls into locking phase range, if it is not, the step of repeating this tracking initial phase, If so, locking initial phase, and then execute step S613.

Step S613: utilizing oscillating circuit, according to initial calibration frequency (when being corrected) and initial control signal, Export frequency of oscillation.

Step S615: utilizing divider, by the frequency of oscillation of oscillator signal divided by default divider value, has with output and is removed Frequency is removed signal.

Step S617: phase-frequency detector is utilized, detection is by the difference on the frequency for being removed frequency and reference frequency except signal Value, and detection is by the phase difference value for being removed phase and fixed phase except signal.

Step S619: utilizing coarse adjustment lock-in circuit, according to frequency difference to judge/track by except whether frequency falls into coarse adjustment Locking frequency range, and removed whether phase falls into coarse adjustment locking phase range according to phase difference value to judge/track, if not (by frequency is removed), executes step S621: to by except frequency carries out coarse adjustment tracking, if not (by phase is removed), executing step S621: right Coarse adjustment tracking is carried out except phase, if (by frequency is removed), executes step S623: being locked with the frequency of being removed that coarse adjustment tracks Frequently, if (by phase is removed), executes step S623: carrying out locking phase with the phase of being removed that coarse adjustment tracks.Frequency locking and locking phase it Afterwards, step S625 is then executed.Alternatively, can only step S621~S623 tracking and locking frequency, until step S625~ The S629 beginning carries out chasing after phase and locking phase.

Step S625: utilizing fine tuning lock-in circuit, according to frequency difference to judge/track by except whether frequency falls into fine tuning Locking frequency range, and removed whether phase falls into fine tuning locking phase range according to phase difference value to judge/track, if not (by frequency is removed), executes step S627: to by except frequency carries out fine tuning tracking, if not (by phase is removed), executing step S627: right Fine tuning tracking is carried out except phase, if (by frequency is removed), executes step S629: being locked with the frequency of being removed that fine tuning tracks Frequently, if (by phase is removed), executes step S629: carrying out locking phase with the phase of being removed that fine tuning tracks.Complete frequency locking and lock After phase, when utilizing frequency of oscillation to generate oscillator signal again, it can be directed to newly generated oscillator signal, repeat step S615~S629.

In addition, the auto-correction method of the present embodiment can further include following steps: using fine tuning lock-in circuit and Coarse adjustment lock-in circuit, the result output coarse adjustment locking signal and fine tuning locking signal tracked respectively according to fine tuning and coarse adjustment；Benefit With encoder, coarse adjustment locking signal and fine tuning locking signal are encoded, to export the lock control signal of tool bit streams； Using oscillating circuit, according to lock control signal and initial calibration signal, to export another oscillator signal.

Referring to Fig. 7, it is that the execution of the auto-correction method of the digital phase locked loop of seventh embodiment of the invention is initial The step flow diagram of frequency and oscillation frequency correction.As shown in fig. 7, the digital phase locked loop of the present embodiment automatically corrects Method is suitable for above-mentioned digital phase locked loop, comprises the steps of S701~S725.

Step S701: resetting numerical digit phase-locked loop.

Step S703: utilizing Frequency Phase Lock circuit, receives correction point control signal from outside, and exports corresponding first Begin control signal.

Step S705: correcting circuit is utilized, judges whether original frequency falls into tolerable correction error range, if it is not, holding Row step S707: utilizing correcting circuit, be corrected to original frequency, if so, directly executing step without correction S709。

Step S709: utilizing coarse adjustment lock-in circuit, and initial calibration frequency (when being corrected) or first is tracked/judged in coarse adjustment Whether beginning frequency (when not being corrected) falls into coarse adjustment locking frequency range, if it is not, executing step S711: to initial calibration frequency Rate or original frequency carry out coarse adjustment tracking, if so, using coarse adjustment lock-in circuit, initial calibration frequency or initial that track lock arrives Frequency.

Optionally, the auto-correction method of the digital phase locked loop of the present embodiment also may include the following steps: tracking Whether the initial phase of initial control signal falls into locking phase range, if it is not, the step of repeating this tracking initial phase, If so, locking initial phase, and then execute step S713.

Step S713: utilizing oscillating circuit, according to initial calibration signal (when being corrected) and initial control signal, With outputting oscillation signal.

Step S715: utilizing divider, by oscillator signal divided by default divider value, and exports corresponding by except signal.

Step S717: phase-frequency detector is utilized, detection is removed frequency except signal, with reference frequency by frequency elimination Rate difference.

Step S719: utilizing correcting circuit, according to frequency difference is removed, judges by except whether frequency falls into tolerable correction Error range, if it is not, executing step S721: being removed frequency according to setpoint frequency to correct, and exported with by except correction frequency By remove correction signal, if so, without correction, directly execute step S723.

Step S723: utilizing Frequency Phase Lock circuit, judges by except correction signal is by except correction frequency (carries out school Timing) or locking frequency range whether is fallen into except frequency (when not being corrected), and judge to be removed the quilt of correction signal Except whether phase falls into locking phase range, if not (by except correction frequency or by except frequency), step S725 is executed: to by except school Positive frequency is tracked except frequency, if not (by phase is removed), executes step S725: to being tracked except phase, if (by except correction frequency or by except frequency), executes step S725: to track by except correction frequency or by except frequency is locked Frequently, if (by phase is removed), executes step S725: carrying out locking phase with the phase of being removed tracked, and export respective frequencies and phase The lock control signal of position tracking result is to oscillating circuit.Finally, by oscillating circuit according to by except correction signal and locking Signal is controlled, exports another oscillator signal, and repeat step S715~S725 for another oscillator signal.

Locking frequency range in above-mentioned steps S723 may include coarse adjustment locking frequency range and fine tuning locking frequency model It encloses；Locking phase range may include coarse adjustment locking phase range and fine tuning locking phase range.That is, can will be applied to It (is passed through except frequency and by step S619~S629 of the sixth embodiment except phase correction frequency of being removed for being diverted to step S723 Frequency is removed after correction) and phase is removed, coarse adjustment locking frequency range or fine tuning locking phase range are fallen into comprising locking By except correction frequency, and locking fall into coarse adjustment locking phase range or fine tuning locking phase range by except phase.

In conclusion the beneficial effects of the present invention are the digital servo-controls provided by the invention with zero offset capability Circuit and auto-correction method are influenced by the various factors in processing procedure and environment in oscillating circuit and the frequency of output are caused to be floated When shifting, drift frequency and phase can be automatically corrected, without carrying out by additional board for example when starting digital phase locked loop Specifying calibration can optimize the resolution ratio for improving oscillator, and can effectively save under the limited control digit of oscillating circuit This.

The foregoing is merely illustratives, rather than are restricted person.It is any without departing from spirit and scope of the invention, and to it The equivalent modifications or change of progress, are intended to be limited solely by appended claims range.

Must be explanatorily finally, in preceding description, although by the concept of the technology of the present invention with multiple exemplary implementations Example is specifically illustrated in and illustrates, however it will be understood by those skilled in the art that is defined without departing substantially from by following following claims range The technology of the present invention concept range under conditions of, the various change in form and details can be made to it.

Only the foregoing is merely preferred possible embodiments of the invention, therefore, it does not limit the scope of the patents of the invention, therefore Such as it with the equivalent structure variation carried out by description of the invention and diagramatic content, is similarly included within the scope of the present invention, Chen Ming is given in conjunction.