阅读说明：本技术 一种低功耗行波分频电路 (Low-power-consumption traveling wave frequency division circuit ) 是由 曹怡珺 于 2019-09-29 设计创作，主要内容包括：一种低功耗行波分频电路,包括多个触发器,其中,每个触发器的D端与其输出端<Image he="66" wi="51" file="DDA0002220785820000011.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>连接,每个触发器的复位端<Image he="64" wi="45" file="DDA0002220785820000012.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>通过导线并联并与外部<Image he="49" wi="134" file="DDA0002220785820000013.GIF" imgContent="drawing" imgFormat="GIF" orientation="portrait" inline="no"></Image>分频信号连接；第一个触发器的时钟端与外部时钟源连接；其特征为：还包括多个与门,每个与门与外部分频时钟选择信号中的一位连接,每个与门的第一输入端与每个触发器的输出端Q连接,每个与门的输出端与其后面的触发器的时钟端连接。(A low-power consumption traveling wave frequency division circuit comprises a plurality of triggers, wherein the D end of each trigger is connected with the output end of the trigger, and the reset end of each trigger is connected in parallel with an external frequency division signal through a wire; the clock end of the first trigger is connected with an external clock source; it is characterized in that: the circuit also comprises a plurality of AND gates, each AND gate is connected with one bit in the external frequency division clock selection signal, the first input end of each AND gate is connected with the output end Q of each trigger, and the output end of each AND gate is connected with the clock end of the trigger behind the AND gate.)

1. A low-power consumption traveling wave frequency division circuit comprises a plurality of triggers, wherein the D end of each trigger is connected with the output end of the trigger, and the reset end of each trigger is connected in parallel with an external frequency division signal through a wire; the clock end of the first trigger is connected with an external clock source; it is characterized in that: the second input end of each AND gate is connected with one bit in the external frequency division clock selection signal, the first input end of each AND gate is connected with the output end Q of each trigger, and the output end of each AND gate is connected with the clock end of the trigger behind the AND gate.

2. The low-power consumption traveling wave frequency dividing circuit according to claim 1, characterized in that: the number of the triggers is four, and the number of the AND gates is three.

Technical Field

The invention relates to a circuit structure, in particular to a low-power-consumption traveling wave frequency division circuit.

Background

The frequency division circuit is used in an integrated circuit in a large number to generate clock signals of various frequencies to drive the operation of the integrated circuit. Clock signals of different frequencies are used for different internal modules of the integrated circuit and are distributed according to requirements. Typical clock frequency division circuits mainly include a traveling wave frequency divider, a synchronous integer frequency divider, a fractional frequency divider, and the like. Travelling wave dividers are the most commonly used dividers.

As shown in fig. 1-2, a conventional traveling-wave frequency divider is formed by cascading a plurality of D flip-flops, where a D flip-flop inputs a signal on a D pin when a clock rises, so that Q is equal to D, and the operating principle of the structure is as follows: for Q0, (non-Q0) ═ D, so until the first clock rising edge arrives, (non-Q0) ═ 1, Q0 ═ 0, the input signal of D ═ 1, at the time of the clock rising edge, Q ═ D ═ 1, and this output is maintained, so that (non-Q0) ═ 0 ═ D, and so on at the next clock cycle, Q0 ═ D ═ 0, and then the signal of Q0 is inverted at the rising edge as a new clock cycle, and the frequency division is performed on the premise that the input signal of each D is 1.

However, the conventional traveling wave frequency divider (taking 4D flip-flops as an example) has the following problems: after the frequency divider is started, the whole circuit can always run, and if the circuit selects q (0) as a module clock, the 2 nd to 4 th D flip-flops do idle work and waste power consumption.

As another example, in the prior art, a LOCK detection circuit with programmable LOCK precision and LOCK frequency is disclosed in chinese patent application (application No. CN201110083516.3, publication No. CN102291130A), which divides a reference clock by M, divides an output clock by N, enables a counter with a count coefficient related to M, N in a half period T1 of the divided signal of the reference clock by M, counts the divided signal of the VCO output clock by Cnt for a count time T2, and then compares T1 and T2 by a determination module after a delay of X VCO clocks, determines whether the VCO output clock and the reference clock satisfy a predetermined relationship within a certain error range, and outputs a LOCK status flag LOCK, the LOCK detection circuit disclosed in the present invention provides programmable parameters M, N, Cnt and X, and the adjustment of the LOCK precision and the LOCK frequency of the LOCK detection circuit can be achieved by changing these parameters, however, the invention can not solve the problem of power consumption, each stage needs to work, and the final frequency division multiple can be controlled by CM [ K:0] because the alternative selector is arranged between the Q of the previous stage and the clock signal of the next stage.

Disclosure of Invention

In order to solve the problems in the prior art, the invention discloses a low-power-consumption traveling wave frequency division circuit, which adopts the following technical scheme:

A low-power consumption traveling wave frequency division circuit comprises a plurality of triggers, wherein the D end of each trigger is connected with the output end of the trigger, and the reset end of each trigger is connected in parallel with an external frequency division signal through a wire; the clock end of the first trigger is connected with an external clock source; it is characterized in that: the second input end of each AND gate is connected with an external frequency division clock selection signal after being connected in parallel, the first input end of each AND gate is connected with the output end Q of each trigger, and the output end of each AND gate is connected with the clock end of the trigger behind the AND gate.

Preferably: the number of the triggers is four, and the number of the AND gates is three.

Has the advantages that:

Compared with the existing traveling wave frequency division circuit, the power consumption is saved.

Drawings

Fig. 1 is a schematic diagram of a traveling wave frequency division circuit in the prior art.

Fig. 2 is a waveform diagram of a frequency dividing circuit after the reset of a traveling wave frequency dividing circuit in the prior art is finished.

Fig. 3 is a schematic diagram of the low-power-consumption traveling wave frequency division circuit according to the present invention.

Fig. 4 is a waveform diagram of the frequency dividing circuit after the reset of the low-power-consumption traveling wave frequency dividing circuit is finished.

Wherein the waveform diagram of FIG. 4(a) is the waveform diagram of DIVCLKSEL [2:0] three bits full 0; (b) a waveform diagram when DIVCLKSEL [2] is equal to 0, DIVCLKSEL [1] is equal to 0, and DIVCLKSEL [0] is equal to 1; (c) a waveform diagram when DIVCLKSEL [2] is equal to 0, DIVCLKSEL [1] is equal to 1, and DIVCLKSEL [0] is equal to 1; (d) the waveform diagram is DIVCLKSEL [2] equals 1, DIVCLKSEL [1] equals 1, and DIVCLKSEL [0] equals 1.

Detailed Description

A low-power consumption traveling wave frequency division circuit comprises a plurality of triggers, wherein the D end of each trigger is connected with the output end of the trigger, and the reset end of each trigger is connected in parallel with an external frequency division signal through a wire; the clock end of the first trigger is connected with an external clock source; it is characterized in that: the second input end of each AND gate is connected with one bit in the external frequency division clock selection signal, the first input end of each AND gate is connected with the output end Q of each trigger, and the output end of each AND gate is connected with the clock end of the trigger behind the AND gate. The number of the triggers is four, and the number of the AND gates is three.

The improved operation principle is as follows, please refer to fig. 3-4.

The clock input of a D trigger CLK in the gated travelling wave frequency division circuit is introduced with DIVCLKSEL [2:0] frequency division clock selection signals, if DIVCLKSEL [0] selects q (0), the subsequent clock of the AND gate is gated by DIVCLKSEL, and the D trigger does not have clock input, and does not make useless inversion, thereby achieving the purpose of saving power.

The present invention is not limited to the above embodiments, and any modification, equivalent replacement, or improvement made within the scope of the present invention shall be included in the protection scope of the present invention, such as increasing the number of stages of the divider and correspondingly providing more and gates and external division clock selection signals.