阅读说明：本技术 一种基于数字锁相环的全数字低电平系统 (all-digital low-level system based on digital phase-locked loop ) 是由 付晓亮 殷治国 纪彬 魏俊逸 张天爵 于 2019-09-03 设计创作，主要内容包括：本发明公开了一种基于数字锁相环的全数字低电平系统,该全数字低电平系统整体上为一个闭环回路,用于控制高频信号的幅度相位信息；该闭环回路从加速器腔体两端拆开由三条并联的主体幅相控制分支组成；该三条并联的主体幅相控制分支共用一个输入端ADC和一个输出端DAC；该ADC输入端从加速器腔体取样数据、该DAC将数字信号转换为模拟信号后输出给功率放大器,经过功率放大器馈入到加速器腔体,ADC再从加速器腔体取样,从而形成闭环回路；该闭环回路还连接有一个将整个系统所有信号的相位锁定到外部参考信号源上的数字锁相环,本发明解决了锁定多个信号的相位到同一个信号源的问题,减少了系统接口,降低了系统复杂度,提高了系统可靠性。(The invention discloses an all-digital low-level system based on a digital phase-locked loop, which is a closed loop on the whole and is used for controlling the amplitude phase information of a high-frequency signal; the closed loop circuit is formed by three main body amplitude-phase control branches which are connected in parallel and are disassembled from two ends of the accelerator cavity; the three parallel main body amplitude-phase control branches share an input end ADC and an output end DAC; the ADC input end samples data from the accelerator cavity, the DAC converts a digital signal into an analog signal and outputs the analog signal to the power amplifier, the analog signal is fed into the accelerator cavity through the power amplifier, and the ADC samples the data from the accelerator cavity so as to form a closed loop; the closed loop is also connected with a digital phase-locked loop which locks the phases of all signals of the whole system to an external reference signal source.)

1. An all-digital low-level system based on a digital phase-locked loop,

The method is characterized in that: the all-digital low-level system is a closed loop as a whole and is used for controlling amplitude phase information of a high-frequency signal u0(t) ═ A0(t) cos [ omega 0t + phi 0(t) ] + A1(t) cos [ omega 1t + phi 1(t) ] + A2(t) cos [ omega 2t + phi 2(t) ]; the closed loop circuit is formed by three parallel main body amplitude-phase control branches which are detached from two ends of an accelerator cavity and respectively control amplitude phase information of three frequency components of omega 0, omega 1 and omega 2; each main body amplitude-phase control branch is further divided into two amplitude control branches and two phase control branches which are connected in parallel; the three parallel main body amplitude-phase control branches share an input end ADC and an output end DAC; the ADC input end samples data from the accelerator cavity, the DAC converts a digital signal into an analog signal and outputs the analog signal to the power amplifier, the analog signal is fed into the accelerator cavity through the power amplifier, and the ADC samples the data from the accelerator cavity so as to form a closed loop; the closed loop is also connected with a digital phase-locked loop which locks the phases of all signals of the whole system to an external reference signal source, and the digital phase-locked loop is used for dynamically tracking the phase difference between a 5.89MHz reference signal and a local NCO of the phase-locked loop in real time so that the frequency difference between the two signals is almost the same.

2. The all-digital low-level system based on digital phase-locked loop of claim 1, wherein: after the amplitude control branch of each main body amplitude-phase control branch is led out from the ADC, the signal passes through a multiplier, a tuning NCO, a low-pass filter, an amplitude-phase converter CODEC module, a phase setting comparator Aset, a PID controller, a final-stage NCO and a multipath signal adder from left to right; after being led out from the ADC, a signal firstly passes through two multipliers, wherein the input of each multiplier is divided into two paths, one path is ADC sampling data, and the other path is from a tuning NCO; the tuning NCO is a numerical control oscillator and is used for programming the tuning NCO to generate two paths of orthogonal signals with any frequency, and the tuning NCO of an omega 0 frequency component channel is taken as an example and is expressed as follows:

the signal output by the tuning NCO is multiplied by the ADC signal to obtain I, Q two paths of signals, which are expressed as:

The two paths of signals pass through a low-pass filter to form a low-frequency signal, which can be expressed as:

I. the Q two paths of signals are input into a CODEC module, the CODEC module is used for converting the signals from an I, Q coordinate system into an amplitude-phase coordinate system, and the specific conversion method comprises the following steps:

the CODEC module has two output signals R, Theta after conversion, wherein R corresponds to the amplitude signal of the high-frequency signal, the amplitude signal R and the information of the Aset amplitude set point are subtracted, and the difference value is input into a PID controller; the PID controller performs a closed-loop control based on the difference between the feedback signal and the desired signal, and the closed-loop control is output to the amplitude control variable of the final NCO.

3. The all-digital low-level system based on digital phase-locked loop of claim 1, wherein: the phase control branch of each main body amplitude-phase control branch is led out from an ADC (analog-to-digital converter), and then is divided into I, Q signals through a multiplier and a low-pass filter, I, Q signals are input into a CODIC (complementary digital-to-analog converter) module, two output signals R, Theta are left after the CODIC module is converted, Theta corresponds to phase information of a high-frequency signal, subtraction operation is carried out on the Theta signal and a desired phase value Pset, an error value after comparison is input into a PID (proportion integration differentiation) module, and PID (proportion integration differentiation) is output into a phase control variable of a final-stage NCO.

4. The all-digital low-level system based on digital phase-locked loop of claim 2, wherein: the multi-path signal adder is arranged between the output end of the three-path final-stage NCO and the DAC and used for carrying out unified summation on three paths of data in the multi-path signal adder and inputting the data to the DAC.

5. the all-digital low-level system based on digital phase-locked loop of claim 1, wherein: each block diagram of each branch of the three-way main body amplitude-phase control branch is the same, and the only difference is that the frequencies of tuning NCO of the three-way branches are different: the frequency control word of the first tuning NCO is 6f, the frequency control word of the second tuning NCO is 4f, and the frequency control word of the third tuning NCO is 2 f. Wherein f is the output frequency of the digital phase-locked loop.

6. the all-digital low-level system based on digital phase-locked loop of claim 1, wherein: the digital phase-locked loop comprises an ADC, two multipliers, two low-pass filters, a phase discriminator PD and a loop filter LF from left to right; the ADC is used for sampling a reference signal and converting the reference signal into a digital signal from an analog signal; the two multipliers are used for multiplying the outputs of the ADC and the NCO to form I, Q two-path signals; the two low-pass filters are used for filtering out high-frequency components in I, Q signals output by the two multipliers; the filtered I, Q signal is input to a phase detector PD, and the phase detector PD is used for identifying the phase difference of two paths of input signals; the phase difference is the phase difference of two signals, namely a 5.89MHz reference signal and a phase-locked loop local NCO; the output of the phase discriminator PD passes through a loop filter LF, the output of the LF is subjected to frequency multiplication and then is used as the frequency of the tuning NCO of the three main amplitude-phase control branches, and the dynamic adjustment of the frequency of each tuning NCO is realized.

7. The all-digital low-level system based on digital phase-locked loop of claim 5, wherein: the method for calculating the output frequency f of the digital phase-locked loop comprises the following steps:

assume that the external phase reference signal can be expressed as:

x(t)＝Acos(ωt)

The output of the phase locked loop local NCO is represented as:

The result of the mixing of the two products is:

After passing through the low pass filter, the result can be expressed as:

after passing through the phase discriminator, the output result is:

φ(t)＝A/8sin[2(ω-ω)t-2φ(t)]

When the frequency difference is small, equation (12) can be expressed as:

φ(t)＝A/8[2(ω-ω)t-2φ(t)]

The above equation shows that the output of the phase detector is directly proportional to the phase difference between the phase reference signal and the local oscillator signal.

After the phase error signal passes through the loop filter, the output result is as follows:

Δf＝kgφ(t)+k∫φ(t)

The frequency word of the final input NCO is:

f＝f+Δf

8. The all-digital low-level system based on digital phase-locked loop of claim 7, wherein: after the output frequency f of the digital phase-locked loop is obtained through calculation, the frequency of the tuning NCO corresponding to the three frequency components is obtained through further calculation, and the calculation method is as follows:

when the local NCO is locked to the external phase reference signal, the three frequency component signals satisfying the above formula will automatically lock the phase to the external phase reference signal.

Technical Field

the invention belongs to the technical field of accelerators, and particularly relates to an all-digital low-level system based on a digital phase-locked loop.

Background

In an accelerator system, in order to increase the beam intensity, a beam condenser is generally added to the front end of the accelerator. The beam buncher has the working principle that the beam is compressed in the injection axial direction to form a beam cluster, so that the number of accelerated particles in unit time is increased, and a beam with higher intensity is generated. To achieve this, it is necessary that a certain phase relationship be satisfied between the low-level amplitude-phase control system of the buncher and the low-level control system of the accelerator. Thus, both control systems need to be locked to the same phase reference to achieve phase synchronization. However, in order to obtain better bunching efficiency, better restraining effect can be obtained by driving the buncher with sawtooth waves instead of sine waves. The ideal sawtooth wave signal can be decomposed into superposition of fundamental wave and each subharmonic wave by using a Taylor formula, thereby being more beneficial to technical realization. Taking the synthesis of a sawtooth wave by using fundamental waves, second harmonics and third harmonics as an example, an amplitude-phase control system of the beam combiner needs to lock three signals with different frequencies to a phase reference. This puts more stringent requirements on the control system. In the prior art, three paths of reference signals are generated respectively, and are subjected to IQ demodulation, PID calculation to obtain a fine tuning amount, and the fine tuning amount is output to an amplifier to drive a beam combiner through IQ modulation. The system needs to provide three phase reference signals, and meanwhile, the system needs to respectively provide sampling clocks with the frequency being 4 times that of the sampled signals. This approach greatly increases the complexity of the system and reduces reliability.

Disclosure of Invention

the invention provides a digital phase-locked loop-based all-digital low-level system aiming at the problems in the prior art, and aims to solve the problems that each branch of a beam bunching device amplitude-phase control system needs to provide a phase reference signal and a sampling clock which is 4 times of the frequency of a sampled signal, the complexity of the system is increased, and the reliability is reduced.

in order to solve the technical problem, the invention provides the following technical scheme:

A digital phase-locked loop-based all-digital low-level system is characterized in that:

The all-digital low-level system is a closed loop as a whole and is used for controlling amplitude phase information of a high-frequency signal u0(t) ═ A0(t) cos [ omega 0t + phi 0(t) ] + A1(t) cos [ omega 1t + phi 1(t) ] + A2(t) cos [ omega 2t + phi 2(t) ]; the closed loop circuit is formed by three parallel main body amplitude-phase control branches which are detached from two ends of an accelerator cavity and respectively control amplitude phase information of three frequency components of omega 0, omega 1 and omega 2; each main body amplitude-phase control branch is further divided into two amplitude control branches and two phase control branches which are connected in parallel; the three parallel main body amplitude-phase control branches share an input end ADC and an output end DAC; the ADC input end samples data from the accelerator cavity, the DAC converts a digital signal into an analog signal and outputs the analog signal to the power amplifier, the analog signal is fed into the accelerator cavity through the power amplifier, and the ADC samples the data from the accelerator cavity so as to form a closed loop; the closed loop is also connected with a digital phase-locked loop which locks the phases of all signals of the whole system to an external reference signal source, and the digital phase-locked loop is used for dynamically tracking the phase difference between a 5.89MHz reference signal and a local NCO of the phase-locked loop in real time so that the frequency difference between the two signals is almost the same.

After the amplitude control branch of each main body amplitude-phase control branch is led out from the ADC, the signal passes through a multiplier, a tuning NCO, a low-pass filter, an amplitude-phase converter CODEC module, a phase setting comparator Aset, a PID controller, a final-stage NCO and a multipath signal adder from left to right; after being led out from the ADC, a signal firstly passes through two multipliers, wherein the input of each multiplier is divided into two paths, one path is ADC sampling data, and the other path is from a tuning NCO; the tuning NCO is a numerical control oscillator and is used for programming the tuning NCO to generate two paths of orthogonal signals with any frequency, and the tuning NCO of an omega 0 frequency component channel is taken as an example and is expressed as follows:

The signal output by the tuning NCO is multiplied by the ADC signal to obtain I, Q two paths of signals, which are expressed as:

the two paths of signals pass through a low-pass filter to form a low-frequency signal, which can be expressed as:

I. The Q two paths of signals are input into a CODEC module, the CODEC module is used for converting the signals from an I, Q coordinate system into an amplitude-phase coordinate system, and the specific conversion method comprises the following steps:

the CODEC module has two output signals R, Theta after conversion, wherein R corresponds to the amplitude signal of the high-frequency signal, the amplitude signal R and the information of the Aset amplitude set point are subtracted, and the difference value is input into a PID controller; the PID controller performs a closed-loop control based on the difference between the feedback signal and the desired signal, and the closed-loop control is output to the amplitude control variable of the final NCO.

the phase control branch of each main body amplitude-phase control branch is led out from an ADC (analog-to-digital converter), and then is divided into I, Q signals through a multiplier and a low-pass filter, I, Q signals are input into a CODIC (complementary digital-to-analog converter) module, two output signals R, Theta are left after the CODIC module is converted, Theta corresponds to phase information of a high-frequency signal, subtraction operation is carried out on the Theta signal and a desired phase value Pset, an error value after comparison is input into a PID (proportion integration differentiation) module, and PID (proportion integration differentiation) is output into a phase control variable of a final-stage NCO.

The multi-path signal adder is arranged between the output end of the three-path final-stage NCO and the DAC and used for carrying out unified summation on three paths of data in the multi-path signal adder and inputting the data to the DAC.

Each block diagram of each branch of the three-way main body amplitude-phase control branch is the same, and the only difference is that the frequencies of tuning NCO of the three-way branches are different: the frequency control word of the first tuning NCO is 6f, the frequency control word of the second tuning NCO is 4f, and the frequency control word of the third tuning NCO is 2 f. Wherein f is the output frequency of the digital phase-locked loop.

the digital phase-locked loop comprises an ADC, two multipliers, two low-pass filters, a phase discriminator PD and a loop filter LF from left to right; the ADC is used for sampling a reference signal and converting the reference signal into a digital signal from an analog signal; the two multipliers are used for multiplying the outputs of the ADC and the NCO to form I, Q two-path signals; the two low-pass filters are used for filtering out high-frequency components in I, Q signals output by the two multipliers; the filtered I, Q signal is input to a phase detector PD, and the phase detector PD is used for identifying the phase difference of two paths of input signals; the phase difference is the phase difference of two signals, namely a 5.89MHz reference signal and a phase-locked loop local NCO; the output of the phase discriminator PD passes through a loop filter LF, the output of the LF is subjected to frequency multiplication and then is used as the frequency of the tuning NCO of the three main amplitude-phase control branches, and the dynamic adjustment of the frequency of each tuning NCO is realized.

The method for calculating the output frequency f of the digital phase-locked loop comprises the following steps:

Assume that the external phase reference signal can be expressed as:

x(t)＝Acos(ωt)

the output of the phase locked loop local NCO is represented as:

The result of the mixing of the two products is:

after passing through the low pass filter, the result can be expressed as:

after passing through the phase discriminator, the output result is:

φ(t)＝A/8sin[2(ω-ω)t-2φ(t)]

When the frequency difference is small, equation (12) can be expressed as:

φ(t)＝A/8[2(ω-ω)t-2φ(t)]

The above equation shows that the output of the phase detector is directly proportional to the phase difference between the phase reference signal and the local oscillator signal.

after the phase error signal passes through the loop filter, the output result is as follows:

Δf＝kgφe(t)+k∫φ(t)

The frequency word of the final input NCO is:

f＝f+Δf

after the output frequency f of the digital phase-locked loop is obtained through calculation, the frequency of the tuning NCO corresponding to the three frequency components is obtained through further calculation, and the calculation method is as follows:

when the local NCO is locked to the external phase reference signal, the three frequency component signals satisfying the above formula will automatically lock the phase to the external phase reference signal.

advantageous effects of the invention

1. The invention solves the problem of locking the phases of a plurality of signals to the same signal source, reduces system interfaces, reduces system complexity and improves system reliability by adopting the technologies of digital phase-locked loops, single-channel ADC and DAC modulation and demodulation of multi-channel signals and the like.

2. The invention solves the problem that the sampling clock of the traditional quadrature IQ sampling system changes along with the frequency change of the sampled signal. According to the technical scheme, the sampling clock is not influenced by the frequency of the sampled signal, and the flexibility and the application range of the system are greatly improved.

3. the invention provides a novel low-level system construction method, and particularly relates to a system which does not consider the future clock tree expansion requirement in the initial design stage.

4. Compared with the traditional system, the invention greatly saves hardware resources, improves the integration level and improves the reliability of the system.

Drawings

FIG. 1 is a block diagram of the system of the present invention.

Detailed Description

the invention is further explained below with reference to the drawings:

design principle of the invention

1. least system interface design principle: the method for reducing the system interface aims at the prior art that three paths of sampling clocks with different frequencies are needed for processing three signals with different frequencies in the prior method, and the frequency of each sampling clock is four times that of a sampled signal; if the processing is carried out according to the traditional method, the number of the needed interfaces is at least two more sampling clock signals than that of the traditional mode; if phase locking to the outside is needed, at least two phase reference signal inputs are additionally needed, but the invention only needs one external phase reference signal input, and two sampling clocks and two phase reference signals are saved.

2. modular design principle. The modularization has the advantages that the method for accessing the system is more flexible, the requirement on the system and the dependence on specific signals are weak, and only one phase reference and one clock are needed. The system is a whole and has little dependence on external signals, so the system is simpler and more reliable, and because the fault rate is very high in the aspect of connector assembly, and the fault rate is reduced because of few interfaces; the modularity also has the advantage that the system design is less critical with respect to the clock and sampled signal, whereas the conventional approach has to be four times more critical, which is not achievable for most devices, so the present invention can be used in less powerful chips for more critical applications.

3. the design principle of future expansion requirements is reserved. The invention can work only by one sampling signal and one external reference without the limit of actually having more branches, and for the condition that how many branches and sampling clocks are needed for actual use in the future are not considered or cannot be expected in the initial design stage, the design of the system reserving the future expansion requirement can meet the requirement in the initial design stage.

4. And (3) designing the fault tolerance of the system. If the clock is mistaken in the system design and is not completely quadrupled, the system has certain fault tolerance because the clock of the invention does not depend on the quadruple sampling relation.

Based on the principle, the invention designs an all-digital low-level system based on a digital phase-locked loop.

an all-digital low-level system based on a digital phase-locked loop is shown in figure 1,

the method is characterized in that: the all-digital low-level system is a closed loop as a whole and is used for controlling amplitude phase information of a high-frequency signal u0(t) ═ A0(t) cos [ omega 0t + phi 0(t) ] + A1(t) cos [ omega 1t + phi 1(t) ] + A2(t) cos [ omega 2t + phi 2(t) ]; the closed loop circuit is formed by three parallel main body amplitude-phase control branches which are detached from two ends of an accelerator cavity and respectively control amplitude phase information of three frequency components of omega 0, omega 1 and omega 2; each main body amplitude-phase control branch is further divided into two amplitude control branches and two phase control branches which are connected in parallel; the three parallel main body amplitude-phase control branches share an input end ADC and an output end DAC; the ADC input end samples data from the accelerator cavity, the DAC converts a digital signal into an analog signal and outputs the analog signal to the power amplifier, the analog signal is fed into the accelerator cavity through the power amplifier, and the ADC samples the data from the accelerator cavity so as to form a closed loop; the closed loop is also connected with a digital phase-locked loop which locks the phases of all signals of the whole system to an external reference signal source, and the digital phase-locked loop is used for dynamically tracking the phase difference between a 5.89MHz reference signal and a local NCO of the phase-locked loop in real time so that the frequency difference between the two signals is almost the same.

after the amplitude control branch of each main body amplitude-phase control branch is led out from the ADC, the signal passes through a multiplier, a tuning NCO, a low-pass filter, an amplitude-phase converter CODEC module, a phase setting comparator Aset, a PID controller, a final-stage NCO and a multipath signal adder from left to right; after being led out from the ADC, a signal firstly passes through two multipliers, wherein the input of each multiplier is divided into two paths, one path is ADC sampling data, and the other path is from a tuning NCO; the tuning NCO is a numerical control oscillator and is used for programming the tuning NCO to generate two paths of orthogonal signals with any frequency, and the tuning NCO of an omega 0 frequency component channel is taken as an example and is expressed as follows:

The signal output by the tuning NCO is multiplied by the ADC signal to obtain I, Q two paths of signals, which are expressed as:

The two paths of signals pass through a low-pass filter to form a low-frequency signal, which can be expressed as:

I. the Q two paths of signals are input into a CODEC module, the CODEC module is used for converting the signals from an I, Q coordinate system into an amplitude-phase coordinate system, and the specific conversion method comprises the following steps:

the CODEC module has two output signals R, Theta after conversion, wherein R corresponds to the amplitude signal of the high-frequency signal, the amplitude signal R and the information of the Aset amplitude set point are subtracted, and the difference value is input into a PID controller; the PID controller performs a closed-loop control based on the difference between the feedback signal and the desired signal, and the closed-loop control is output to the amplitude control variable of the final NCO.

the phase control branch of each main body amplitude-phase control branch is led out from an ADC (analog-to-digital converter), and then is divided into I, Q signals through a multiplier and a low-pass filter, I, Q signals are input into a CODIC (complementary digital-to-analog converter) module, two output signals R, Theta are left after the CODIC module is converted, Theta corresponds to phase information of a high-frequency signal, subtraction operation is carried out on the Theta signal and a desired phase value Pset, an error value after comparison is input into a PID (proportion integration differentiation) module, and PID (proportion integration differentiation) is output into a phase control variable of a final-stage NCO.

The multi-path signal adder is arranged between the output end of the three-path final-stage NCO and the DAC and used for carrying out unified summation on three paths of data in the multi-path signal adder and inputting the data to the DAC.

Each block diagram of each branch of the three-way main body amplitude-phase control branch is the same, and the only difference is that the frequencies of tuning NCO of the three-way branches are different: the frequency control word of the first tuning NCO is 6f, the frequency control word of the second tuning NCO is 4f, and the frequency control word of the third tuning NCO is 2 f. Wherein f is the output frequency of the digital phase-locked loop.

the digital phase-locked loop comprises an ADC, two multipliers, two low-pass filters, a phase discriminator PD and a loop filter LF from left to right; the ADC is used for sampling a reference signal and converting the reference signal into a digital signal from an analog signal; the two multipliers are used for multiplying the outputs of the ADC and the NCO to form I, Q two-path signals; the two low-pass filters are used for filtering out high-frequency components in I, Q signals output by the two multipliers; the filtered I, Q signal is input to a phase detector PD, and the phase detector PD is used for identifying the phase difference of two paths of input signals; the phase difference is the phase difference of two signals, namely a 5.89MHz reference signal and a phase-locked loop local NCO; the output of the phase discriminator PD passes through a loop filter LF, the output of the LF is subjected to frequency multiplication and then is used as the frequency of the tuning NCO of the three main amplitude-phase control branches, and the dynamic adjustment of the frequency of each tuning NCO is realized.

the method for calculating the output frequency f of the digital phase-locked loop comprises the following steps:

Assume that the external phase reference signal can be expressed as:

x(t)＝Acos(ωt)

The output of the phase locked loop local NCO is represented as:

the result of the mixing of the two products is:

after passing through the low pass filter, the result can be expressed as:

after passing through the phase discriminator, the output result is:

φ(t)＝A/8sin[2(ω-ω)t-2φ(t)]

when the frequency difference is small, equation (12) can be expressed as:

φ(t)＝A/8[2(ω-ω)t-2φ(t)]

the above equation shows that the output of the phase detector is directly proportional to the phase difference between the phase reference signal and the local oscillator signal.

After the phase error signal passes through the loop filter, the output result is as follows:

Δf＝kgφ(t)+k∫φ(t)

The frequency word of the final input NCO is:

f＝f+Δf

After the output frequency f of the digital phase-locked loop is obtained through calculation, the frequency of the tuning NCO corresponding to the three frequency components is obtained through further calculation, and the calculation method is as follows:

When the local NCO is locked to the external phase reference signal, the three frequency component signals satisfying the above formula will automatically lock the phase to the external phase reference signal.