阅读说明：本技术 一种镀膜载体和利用其增大异质结太阳能电池tco镀膜面积的方法 (Coated carrier and method for increasing TCO (transparent conductive oxide) coated area of heterojunction solar cell by using same ) 是由 黄金 王继磊 杨立友 白焱辉 鲍少娟 杨骥 李莎 贾慧君 郭磊 孔青青 于 2021-05-28 设计创作，主要内容包括：本发明公开了一种镀膜载体,包括载体本体和盛放硅片的多个放置部,放置部沿载板本体纵向和横向均匀分布；放置部包括第一框体和第二框体,第一框体设于第二框体外侧；第二框体内侧壁上相对设置多个支撑点；并公开增大异质结太阳能电池TCO镀膜面积的方法：(1)将晶体硅片进行制绒、清洗；(2)在晶体硅片的正面制备双本征非晶硅层,然后制备双掺杂非晶硅层；(3)将制备后的双掺杂非晶硅层的硅片放置于镀膜载体的放置部上,然后分别在双掺杂非晶硅层上制备得到导电薄膜层和掩膜区域；(4)在导电薄膜层上通过丝网印刷的方式形成金属电极。采用本发明中的镀膜载体,应用到后续的镀膜方法中能够增大TCO镀膜面积。(The invention discloses a film coating carrier, which comprises a carrier body and a plurality of placing parts for placing silicon wafers, wherein the placing parts are uniformly distributed along the longitudinal direction and the transverse direction of the carrier body; the placing part comprises a first frame body and a second frame body, and the first frame body is arranged outside the second frame body; a plurality of supporting points are oppositely arranged on the inner side wall of the second frame body; and discloses a method for increasing the TCO plating area of the heterojunction solar cell, which comprises the following steps: (1) texturing and cleaning a crystal silicon wafer; (2) preparing a double intrinsic amorphous silicon layer on the front side of the crystal silicon wafer, and then preparing a double doped amorphous silicon layer; (3) placing the prepared silicon wafer of the double-doped amorphous silicon layer on a placing part of a film coating carrier, and then respectively preparing a conductive thin film layer and a mask region on the double-doped amorphous silicon layer; (4) and forming a metal electrode on the conductive film layer by a screen printing mode. The coating carrier disclosed by the invention is applied to a subsequent coating method, and the TCO coating area can be increased.)

1. The film coating carrier is characterized by comprising a carrier body and a plurality of placing parts for placing silicon wafers, wherein the placing parts are uniformly distributed along the longitudinal direction and the transverse direction of the carrier body;

the placing part comprises a first frame body and a second frame body, and the first frame body is arranged on the outer side of the second frame body;

and a plurality of supporting points are oppositely arranged on the inner side wall of the second frame body.

2. The plating carrier according to claim 1, wherein when a supporting point is arranged at 4 corners or a supporting point is arranged at opposite corners of the inner side of the second frame body, the distance between two opposite inner side walls of the second frame body is Z, the side length of the silicon wafer is A, and Z is less than or equal to A-0.2 mm.

3. The plating carrier of claim 2, wherein when the second frame has support points on its inner side walls, the distance between the support points is Z1, and the distance between the two opposite inner side walls of the second frame is Z2; z1 ═ Z, Z2 > Z.

4. The coated carrier according to claim 3, wherein the supporting points are triangular, semicircular or square.

5. The plating carrier as claimed in claim 4, wherein the plating carrier is made of one of stainless steel, aircraft aluminum and titanium alloy.

6. A method for increasing the TCO coating area of a heterojunction solar cell using the coating carrier according to any one of claims 1 to 5, comprising the following steps:

(1) texturing and cleaning a crystal silicon wafer;

(2) preparing a double intrinsic amorphous silicon layer on the front side and the back side of the crystal silicon wafer obtained in the step (1) by utilizing plasma chemical vapor deposition;

(3) preparing a double-sided doped amorphous silicon layer on the double-sided intrinsic amorphous silicon layer;

(4) placing the silicon wafer prepared in the step (3) on a placing part of a film coating carrier, and then preparing a conductive thin film layer and/or a mask area on the double-sided doped amorphous silicon layer;

(5) and forming a metal electrode on the conductive film layer and/or the mask area by means of screen printing.

7. The method for increasing the TCO plating area of the heterojunction solar cell according to claim 6, wherein in the step (1), the textured structure obtained by texturing is a light receiving surface of a pyramid structure.

8. The method for increasing the TCO coating area of the heterojunction solar cell according to claim 6, wherein in the step (4), the method for preparing the conductive thin film layer and/or the mask area is a magnetron sputtering method or a reactive plasma deposition method;

the conductive thin film layer is formed on two surfaces of the doped amorphous silicon layer;

the mask region is formed on one or both sides of the doped amorphous silicon layer.

9. The method for increasing the TCO plating area of the heterojunction solar cell of claim 8, wherein the width B of the mask region is (A-Z)/2 mm;

alternatively, the mask area is divided into two regions having widths of B1 ═ a-Z1)/2mm and B2 ═ a-Z2)/2mm, respectively.

10. The method for increasing the TCO plating area of the heterojunction solar cell according to claim 8, wherein one surface of the doped amorphous silicon layer is doped with P to form N-type doped amorphous silicon, and the other surface is doped with B to form P-type doped amorphous silicon.

Technical Field

The invention relates to the technical field of solar energy, in particular to a coating carrier and a method for increasing the TCO coating area of a heterojunction solar cell by using the coating carrier.

Background

At present, with the development of solar cell technology, the development of high-efficiency cells is more and more emphasized. Among them, a silicon-based heterojunction solar cell (HJT cell) passivated with an amorphous silicon intrinsic layer (a-Si: h (i)) is one of the major research directions. As is known, the silicon-based heterojunction solar cell not only has high conversion efficiency and high open-circuit voltage, but also has the advantages of low temperature coefficient, no Light Induced Degradation (LID), no induced degradation (PID), low preparation process temperature, short process flow and the like. In addition, the silicon-based heterojunction battery ensures high conversion efficiency, and the thickness of the silicon wafer can be reduced to 100 mu m, so that the consumption of silicon materials is effectively reduced, and the silicon-based heterojunction battery can be used for preparing a bendable battery component.

However, the conductivity of amorphous silicon In the conventional HJT cell is not good, and it is a common method to cover the surface with a transparent conductive thin film, and many types of transparent conductive thin films include In₂O₃、SnO₂、ZnO、 In₂O₃:Sn(ITO)、In₂O₃:Mo(IMO)、In₂O₃:W(IWO)、SnO₂:Sb(ATO)、SnO₂:F(FTO)、 ZnO:Al(ZnO)、ZnO·SnO₂、ZnO·In₂O₃、CdSb₂O₆、MgIn₂O₄、In₄Sn₃O1₂、Zn₂In₂O₅、 CdIn₂O₄、Cd₂SnO₄、Zn₂SnO₄、GaInO₃Etc.; due to the double-sided characteristic of the HJT battery, the front and back surfaces of the HJT battery are provided with the amorphous silicon layers, and the mask region of the conductive thin film layer formed on the surface of the amorphous silicon layer is too large, and the mask region is a part of the surface of the amorphous silicon layer without being covered with the conductive layer.

At present, the surface of a formed conductive thin film layer is a single-sided or double-sided mask area, a groove is formed by processing the periphery of a carrier supporting silicon wafer for depositing a thin film, the effect of placing a silicon wafer substrate and forming the mask area is achieved, the transverse distance between the mask area and the edge of the silicon wafer is hardly smaller than 0.8mm, the three factors mainly depend on, firstly, the processing precision is hard to carry the edge of the supported groove to be too narrow; secondly, the precision of automatic mechanical piece placing is not enough and vibration is caused in the transmission process, the mask is easy to deviate from the central position to cause mask deviation after the supported groove carrying edge is too small, namely, the area of the silicon chip which is not covered with the conductive layer can not form symmetry, thirdly, the film is easy to cause winding plating after the supported groove carrying edge is too small, and the front surface and the back surface form short circuit.

Therefore, the problem to be solved by the skilled person is how to provide a method for increasing the TCO film plating area of a heterojunction solar cell, which can improve the performance of a conductive layer to further improve the mass production efficiency of the HJT cell and accelerate the large-area industrialization process.

Disclosure of Invention

In view of this, the invention provides a method for increasing the TCO plating area of a heterojunction solar cell, which can improve the performance of a conductive layer to further improve the mass production efficiency of the HJT cell and accelerate the large-area industrialization process.

In order to achieve the purpose, the invention adopts the following technical scheme: a film coating carrier comprises a carrier body and a plurality of placing parts for placing silicon wafers, wherein the placing parts are uniformly distributed along the longitudinal direction and the transverse direction of the carrier body;

the placing part comprises a first frame body and a second frame body, and the first frame body is arranged on the outer side of the second frame body;

and a plurality of supporting points are oppositely arranged on the inner side wall of the second frame body.

The invention has the beneficial effects that: the film coating carrier can ensure that the width of the mask is small enough and is in the range of controllable automatic film placing precision; the area of the film covering the conductive layer is ensured to be increased.

Preferably, when a supporting point is arranged at 4 corners or diagonally arranged at the inner side of the second frame body, the distance between two opposite inner side walls of the second frame body is Z, the side length of the silicon wafer is A, and Z is not more than A-0.2 mm.

Adopt above-mentioned technical scheme's beneficial effect: if the value exceeds the above-defined range, the leakage of the battery device is easily caused. When the supporting point is arranged at the 4 corners or the diagonal corners inside the second frame body, Z can be further increased without influencing the support.

Preferably, when the inner side walls of the second frame body are provided with supporting points, the distance between the oppositely arranged supporting points is Z1, and the distance between the two opposite inner side walls of the second frame body is Z2; z1 ═ Z, Z2 > Z.

Preferably, the support points are triangular, semi-circular or square.

Preferably, the material of the coating carrier is one of stainless steel, aviation aluminum and titanium alloy.

Preferably, the coating carrier is suitable for transparent conductive film equipment, and can also be used for magnetron sputtering equipment and reactive plasma deposition equipment.

The invention also provides a method for increasing the TCO plating area of the heterojunction solar cell, which comprises the following steps:

(1) texturing and cleaning a crystal silicon wafer;

(2) preparing a double intrinsic amorphous silicon layer on the front side and the back side of the crystal silicon wafer obtained in the step (1) by utilizing plasma chemical vapor deposition;

(3) preparing a doped amorphous silicon layer on the double-sided intrinsic amorphous silicon layer, wherein the double-sided doped amorphous silicon layer has different doping types;

(4) placing the silicon wafer prepared in the step (3) on a placing part of a film coating carrier, and then preparing a double-sided conductive thin film layer and/or a mask area on the doped amorphous silicon layer;

(5) and forming a metal electrode on the conductive film layer and/or the mask area by means of screen printing.

The invention has the beneficial effects that: the method can greatly increase the film forming area of the conductive layer, thereby improving the conversion efficiency of the solar cell.

Preferably, in the step (1), the textured structure obtained by texturing is a light receiving surface with a pyramid structure; the crystal silicon wafer is square or quasi-square.

Preferably, in the step (4), the method for preparing the conductive thin film layer and/or the mask region is a magnetron sputtering method or a reactive plasma deposition method;

the conductive thin film layer is formed on two surfaces of the doped amorphous silicon layer;

the mask region is formed on one or both sides of the doped amorphous silicon layer.

Preferably, in step (4), the width B of the mask region is (a-Z)/2 mm;

alternatively, the mask area is divided into two regions having widths of B1 ═ a-Z1)/2mm and B2 ═ a-Z2)/2mm, respectively.

Adopt above-mentioned technical scheme's beneficial effect: the placing section is provided in the above two forms in order to increase the width Z of the lower opening inside so as to be offset outward, thereby increasing the plating area.

The coating area of the conductive film on the lower surface can be increased by adopting a mask area; the two mask areas can be adopted to maximally increase the plating area of the lower surface conductive film; the short-circuit current can be greatly improved.

More preferably, B1 > B2 and B2 is 0.3mm or more.

Adopt above-mentioned technical scheme's beneficial effect: considering from the electric leakage standard angle of finished battery during design, it is recommended that if the electric leakage current is increased below 0.3mm, the electric leakage standard is exceeded, and meanwhile, the winding plating risk is easily generated, so that the edge of the battery piece is also plated with the transparent conductive film layer, and the front surface and the back surface are conducted, and in addition, the angle of the battery finished product performance is optimal.

Preferably, in the step (3), one surface of the doped amorphous silicon layer is doped with P to form N-type doped amorphous silicon, and the other surface is doped with B to form P-type doped amorphous silicon.

According to the technical scheme, compared with the prior art, the invention discloses the coating carrier and the method for increasing the TCO coating area of the heterojunction solar cell by using the coating carrier.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a placing part of a coated carrier structure provided by the invention;

FIG. 2 is a schematic structural diagram of a conventional coated carrier in comparative example 1 according to the present invention;

FIG. 3 is a schematic diagram illustrating a mask width structure according to embodiment 1 of the present invention;

FIG. 4 is a schematic diagram illustrating a structure of two mask widths in embodiment 2 of the present invention;

wherein, 1-carrier body, 2-placing part, 21-second frame, 22-first frame, 23-supporting point.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

The coating carrier comprises a carrier body 1 and a plurality of placing parts 2 for containing silicon wafers, wherein the placing parts 2 are uniformly distributed along the longitudinal direction and the transverse direction of the carrier body;

the placing section 2 includes a first frame 22 and a second frame 21, the first frame 22 being provided outside the second frame 21;

a plurality of support points 23 are oppositely arranged on the inner side wall of the second frame body 21.

In one embodiment, the supporting point 23 is arranged at the 4-corner or the diagonal of the inner side of the second frame body 21, the distance between two opposite inner side walls of the second frame body 21 is Z, the side length of the silicon wafer is A, and Z is less than or equal to A-0.2 mm. If the value exceeds the above-defined range, the leakage of the battery device is easily caused.

In one embodiment, when the supporting points 23 are disposed on both inner side walls of the second frame body 21, the distance between the oppositely disposed supporting points 23 is Z1, and the distance between two opposite inner side walls of the second frame body 21 is Z2; z1 ═ Z, Z2 > Z; the support points 23 are triangular, semi-circular or square.

In one embodiment, the material of the coating carrier is selected from one of stainless steel, aviation aluminum and titanium alloy.

In one embodiment, the coated carrier is suitable for transparent conductive film equipment, and can also be used for magnetron sputtering equipment and reactive plasma deposition equipment.

The method for increasing the TCO coating area of the heterojunction solar cell by using the coating carrier comprises the following steps:

(1) carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;

(2) preparing a double intrinsic amorphous silicon layer on the front side and the back side of the crystal silicon wafer obtained in the step (1) by utilizing plasma chemical vapor deposition;

(3) preparing a doped amorphous silicon layer on the double-sided intrinsic amorphous silicon layer; doping P on one surface of the doped amorphous silicon layer to form N-type doped amorphous silicon, and doping B on the other surface of the doped amorphous silicon layer to form P-type doped amorphous silicon;

(4) placing the silicon wafer prepared in the step (3) on a placing part 2 of a coating carrier, and then preparing a double-sided conductive thin film layer and a mask area on the doped amorphous silicon layer; wherein the mask width of the coating carrier is 0.6mm, and the mask width at the edge chamfer is still 0.8 mm;

(5) and (4) forming a metal electrode by screen printing silver paste on the conductive thin film layer and the mask area in the step (4) and curing at 200 ℃.

The electrical performance of the cell was tested and the average efficiency of mass production of the cell was 23.9%.

Example 2

The method for increasing the TCO coating area of the heterojunction solar cell by using the coating carrier comprises the following steps:

(1) carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;

(2) preparing a double intrinsic amorphous silicon layer on the front side and the back side of the crystal silicon wafer obtained in the step (1) by utilizing plasma chemical vapor deposition;

(3) preparing a doped amorphous silicon layer on the double-sided intrinsic amorphous silicon layer; doping P on one surface of the doped amorphous silicon layer to form N-type doped amorphous silicon, and doping B on the other surface of the doped amorphous silicon layer to form P-type doped amorphous silicon;

(4) placing the silicon wafer prepared in the step (3) on a placing part 2 of a coating carrier, and then preparing a double-sided conductive thin film layer and a mask area on the doped amorphous silicon layer; wherein the mask width of the coating carrier is 0.5mm, and the mask width at the support point 23 is still 0.8 mm;

(5) and (4) forming a metal electrode by screen printing silver paste on the conductive thin film layer and the mask area in the step (4) and curing at 200 ℃.

The electrical performance of the cells was tested and the average efficiency of mass production of the cells was 24%.

Comparative example 1

(1) Carrying out texturing treatment on an N-type monocrystalline silicon wafer with the thickness of 180 mu m to form a pyramid textured surface, removing impurity ions and cleaning the surface;

(2) preparing a double intrinsic amorphous silicon layer on the front side and the back side of the crystal silicon wafer obtained in the step (1) by utilizing plasma chemical vapor deposition;

(3) preparing a doped amorphous silicon layer on the double-sided intrinsic amorphous silicon layer; doping P on one surface of the doped amorphous silicon layer to form N-type doped amorphous silicon, and doping B on the other surface of the doped amorphous silicon layer to form P-type doped amorphous silicon;

(4) placing the silicon wafer prepared in the step (3) on a placing part 2 of a coating carrier, and then preparing a double-sided conductive thin film layer and a mask area on the doped amorphous silicon layer; wherein the mask width of the conventional coating carrier is 0.8 mm;

(5) and (4) forming a metal electrode by screen printing silver paste on the conductive thin film layer and the mask area in the step (4) and curing at 200 ℃.

The electrical performance of the cell was tested and the average efficiency of mass production of the cell was 23.7%.

In example 2, Z in example 1 is enlarged and divided into Z1 and Z2, wherein Z1 is Z, and Z2 is more than Z; z in example 1 is larger than Z in comparative example 1. The black areas in fig. 2 and 3 are the silicon wafers placed.

The electrical property of the HJT battery prepared by the coating carrier and the method of the invention improves the short-circuit current by 60-120mA, and compared with the comparative example 1, the efficiency can be improved by about 0.2-0.3%.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.