阅读说明：本技术 Jfet器件 (JFET device ) 是由 段文婷 于 2021-07-02 设计创作，主要内容包括：本发明公开了一种JFET器件,包括：深阱区,在深阱区的选定区域的表面形成有栅极区、源区和漏区。在漂移区的顶部形成有漂移区场氧。在漂移区场氧上形成有多晶硅绕阻,多晶硅绕阻由多圈首尾相连的多晶硅线连接而成,多晶硅绕阻包括第一连接端和第二连接端。第一连接端位于最靠近漂移区场氧的第一侧的多晶硅线上且接0V电位,第二连接端位于最靠近漂移区场氧的第二侧的多晶硅线上且接漏极电位。漂移区场氧的第二侧不设置漏端多晶硅场板,使多晶硅绕阻的圈数最大化。本发明能增加漂移区场氧上的多晶硅绕阻的圈数,从而提高器件的击穿电压。(The invention discloses a JFET device, comprising: and the deep well region is provided with a gate region, a source region and a drain region on the surface of the selected region of the deep well region. A drift region field oxide is formed on top of the drift region. And a polysilicon winding is formed on the drift region field oxide and is formed by connecting a plurality of circles of polysilicon wires which are connected end to end, and the polysilicon winding comprises a first connecting end and a second connecting end. The first connecting end is positioned on the polycrystalline silicon wire closest to the first side of the drift region field oxygen and connected with 0V potential, and the second connecting end is positioned on the polycrystalline silicon wire closest to the second side of the drift region field oxygen and connected with drain potential. And a drain-end polysilicon field plate is not arranged on the second side of the drift region field oxygen, so that the number of turns of the polysilicon winding is maximized. The invention can increase the number of turns of the polysilicon winding on the field oxide of the drift region, thereby improving the breakdown voltage of the device.)

1. A JFET device, comprising:

forming a first-conductivity-type-doped deep well region on a second-conductivity-type-doped semiconductor substrate;

a gate region consisting of a second conductive type doping region, a source region consisting of a first conductive type heavily doped region and a drain region consisting of a first conductive type heavily doped region are formed on the surface of the selected region of the deep well region;

the source region is positioned on the first side of the gate region, and a distance is reserved between the second side of the source region and the first side of the gate region;

the drain region is located on the first side of the gate region and a distance is reserved between the first side of the drain region and the second side of the gate region;

the drift region is positioned between the second side of the gate region and the first side of the drain region;

forming a drift region field oxide on the top of the drift region;

a first side of the drift region field oxide and a second side of the gate region have a spacing;

a first side of the drain region and a second side of the drift region field oxide are self-aligned;

a polysilicon winding is formed on the drift region field oxide and is formed by connecting multiple circles of polysilicon wires in end-to-end connection, and the polysilicon winding comprises a first connecting end and a second connecting end;

the first connecting end is positioned on the polycrystalline silicon wire closest to the first side of the drift region field oxygen and is connected with 0V potential, the second connecting end is positioned on the polycrystalline silicon wire closest to the second side of the drift region field oxygen and is connected with drain potential, and the potential of the polycrystalline silicon wire of each circle is sequentially changed from the 0V potential to the drain potential in the direction from the first side of the drift region field oxygen to the second side of the drift region field oxygen;

and a drain-end polysilicon field plate is not arranged on the second side of the drift region field oxygen, so that the second connecting end is maximally close to the second side of the drift region field oxygen, and the number of turns of the polysilicon winding is maximized.

2. The JFET device of claim 1, wherein: on a top view plane, the drift region field oxide is of a surrounding structure, the first side and the second side of the drift region field oxide are inner sides and outer sides, the gate region and the source region are both positioned on the inner sides of the drift region field oxide, and the drain region is positioned on the outer sides of the drift region field oxide;

each polycrystalline silicon wire of the polycrystalline silicon winding is also in a surrounding structure.

3. The JFET device of claim 1, wherein: on a plane of view, the drift region field oxygen is in a strip structure, and each polycrystalline silicon wire of the polycrystalline silicon winding is in a strip structure connected end to end.

4. The JFET device of claim 1, wherein: the gate region is comprised of a second conductivity type well region.

5. The JFET device of claim 1, wherein: the drift region is directly comprised of the deep well region between the second side of the gate region to the first side of the drain region.

6. The JFET device of claim 1, wherein: the channel region is composed of the deep well region located between the bottom of the gate region and the semiconductor substrate.

7. The JFET device of claim 5, wherein: a top layer of a second conductivity type is also formed in the drift region at the bottom of the drift region field oxide.

8. The JFET device of claim 7, wherein: and a second conductive type top layer is also formed at the bottom of the gate region, and the gate region is contacted with the bottom second conductive type top layer.

9. The JFET device of claim 1, wherein: and a second gate structure formed by overlapping a gate dielectric layer and a polysilicon gate is formed on the surface of the gate region close to the second side, and the second side of the second gate structure also extends to the top surface of the field oxide of the drift region.

10. The JFET device of claim 1, wherein: the second source region composed of the first conductive type heavily doped region is formed on the surface of the gate region and is self-aligned with the first side of the second gate structure.

11. The JFET device of claim 10, wherein: and a gate contact region consisting of a second conductive type heavily doped region is also formed on the surface of the gate region.

12. The JFET device of claim 1, wherein: and a second field oxide is arranged between the source region and the gate region in a spacing mode.

13. The JFET device of claim 1, wherein: the top of the source region is connected to a source electrode formed by patterning of the front metal layer through a contact hole;

the top of the gate region is connected to a gate formed by patterning the front-side metal layer through a contact hole;

the top of the drain region is connected to a drain electrode formed by patterning the front metal layer through a contact hole.

14. The JFET device of claim 1, wherein: the number of turns of the polysilicon winding is more than 1.

15. The JFET device of claim 1, wherein: the JFET device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or the JFET device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

Technical Field

The present invention relates to semiconductor integrated circuits, and more particularly, to Junction Field Effect Transistor (JFET) devices.

Background

The high-voltage LDMOS has the characteristics of high voltage and high current of discrete devices, draws the advantage of high-density intelligent logic control of a low-voltage integrated circuit, realizes the function which can be completed by a plurality of chips originally by a single chip, greatly reduces the area, reduces the cost, improves the energy efficiency, and accords with the development direction of miniaturization, intellectualization and low energy consumption of modern power electronic devices. The high-voltage JFET device carried on the platform is used as an important device of a driving circuit, and the breakdown voltage of the high-voltage JFET device is a key parameter for measuring the characteristics of the high-voltage JFET.

According to customization requirements, a polysilicon winding is added above a drift region of the high-voltage JFET device, so that the breakdown voltage of the device can be increased. As shown in fig. 1, a cross-sectional view of a prior art JFET device; taking an N-type JFET device as an example, a conventional JFET device includes:

an N-type doped deep well region 202 is formed on a P-type doped semiconductor substrate 201.

A gate region 204 composed of a P-type doped region, a source region 208c composed of an N-type heavily doped region, and a drain region 208b composed of an N-type heavily doped region are formed on the surface of the selected region of the deep well region 202.

The gate region 204 is comprised of a P-type well region. The source region 208c and the gate region 204 are separated by a second field oxide 203 a.

The drain region 208b is located on a first side of the gate region 204 and a spacing is provided between the first side of the drain region 208b and a second side of the gate region 204.

The drift region is comprised of the deep well region 202 between the second side of the gate region 204 to the first side of the drain region 208 b.

The channel region is composed of the deep well region 202 between the bottom of the gate region 204 to the semiconductor substrate 201.

A drift region field oxide 203 is formed on top of the drift region.

The first side of the drift region field oxide 203 and the second side of the gate region 204 have a spacing.

A first side of the drain region 208b and a second side of the drift region field oxide 203 are self-aligned.

A P-type top layer (PTOP)205 is also formed in the drift region at the bottom of the drift region field oxide 203. A P-type top layer 205 is also formed at the bottom of the gate region 204 and the gate region 204 is in contact with the bottom P-type top layer 205.

A polysilicon winding 207b is formed on the drift region field oxide 203, the polysilicon winding 207b is formed by connecting multiple circles of polysilicon wires end to end, and the polysilicon winding 207b includes a first connection end and a second connection end.

The first connection end is located on the polysilicon line closest to the first side of the drift region field oxide 203 and connected with a 0V potential, the second connection end is located on the polysilicon line closest to the second side of the drift region field oxide 203 and connected with a drain potential, and the potentials of the polysilicon lines of all circles are sequentially changed from the 0V potential to the drain potential in the direction from the first side of the drift region field oxide 203 to the second side of the drift region field oxide 203.

A second gate structure formed by stacking a gate dielectric layer 206 and a polysilicon gate 207 is formed on the surface of the gate region 204 near the second side, and the second side of the second gate structure further extends to the top surface of the drift region field oxide 203.

A second source region 208a composed of a heavily N-doped region is formed at the surface of the gate region 204 and is self-aligned to the first side of the second gate structure. The second gate structure is used as a gate structure of the LDMOS. The second source region 208a serves as a source region of the LDMOS.

A gate contact region 209 consisting of a P-type heavily doped region is also formed on the surface of the gate region 204.

The top of the source region 208c is connected to a source electrode, which is denoted by S in fig. 1, patterned by a front metal layer 211 through a contact hole 210.

The top of the gate region 204 is connected to a gate, indicated by G in fig. 1, patterned from the front-side metal layer 211 through a contact hole 210.

The top of the drain region 208b is connected to a drain electrode, which is denoted by D in fig. 1, patterned by the front metal layer 211 through a contact hole 210.

A drain-side polysilicon field plate 207a is also provided on the drift region field oxide 203, and the drain-side polysilicon field plate 207a is connected to the drain through a contact hole 210. The drain side polysilicon field plate 207a is closer to the drain region 208b, and the polysilicon winding 207b is located between the polysilicon gate 207 and the drain side polysilicon field plate 207 a. The drain-side polysilicon field plate 207a is not connected to the polysilicon winding 207b, and the top surface structures of the two are different, so that the winding of the polysilicon winding 207b cannot be performed at the place where the drain-side polysilicon field plate 207a is disposed.

Disclosure of Invention

The invention aims to solve the technical problem of providing a JFET device, which can increase the number of turns of a polysilicon winding on field oxide of a drift region, thereby improving the breakdown voltage of the device.

To solve the above technical problem, the JFET device provided by the present invention comprises:

a deep well region doped with a first conductivity type is formed on a semiconductor substrate doped with a second conductivity type.

And a gate region consisting of a second conductive type doped region, a source region consisting of a first conductive type heavily doped region and a drain region consisting of a first conductive type heavily doped region are formed on the surface of the selected region of the deep well region.

The source region is located on the first side of the gate region and a gap is provided between the second side of the source region and the first side of the gate region.

The drain region is located on the first side of the gate region and a gap is formed between the first side of the drain region and the second side of the gate region.

The drift region is located between the second side of the gate region to the first side of the drain region.

And a drift region field oxide is formed on the top of the drift region.

The first side of the drift region field oxide and the second side of the gate region have a spacing.

The first side of the drain region and the second side of the drift region field oxide are self-aligned.

And a polysilicon winding is formed on the drift region field oxide and is formed by connecting multiple circles of polysilicon wires in end-to-end connection, and the polysilicon winding comprises a first connecting end and a second connecting end.

The first connecting end is located on the polycrystalline silicon wire closest to the first side of the drift region field oxygen and connected with a 0V potential, the second connecting end is located on the polycrystalline silicon wire closest to the second side of the drift region field oxygen and connected with a drain potential, and the potential of the polycrystalline silicon wire of each circle changes from the 0V potential to the drain potential in the direction from the first side of the drift region field oxygen to the second side of the drift region field oxygen.

And a drain-end polysilicon field plate is not arranged on the second side of the drift region field oxygen, so that the second connecting end is maximally close to the second side of the drift region field oxygen, and the number of turns of the polysilicon winding is maximized.

In a further improvement, in a top view, the drift region field oxide is in a surrounding structure, a first side of the drift region field oxide is an inner side, and a second side of the drift region field oxide is an outer side, the gate region and the source region are both located on the inner side of the drift region field oxide, and the drain region is located on the outer side of the drift region field oxide.

Each polycrystalline silicon wire of the polycrystalline silicon winding is also in a surrounding structure.

In a further improvement, in a plane of view, the drift region field oxide is in a strip structure, and each polycrystalline silicon wire of the polycrystalline silicon winding is in a strip structure connected end to end.

In a further refinement, the gate region is comprised of a second conductivity type well region.

In a further refinement, the drift region is directly comprised of the deep well region between the second side of the gate region to the first side of the drain region.

In a further improvement, the channel region is composed of the deep well region located between the bottom of the gate region and the semiconductor substrate.

In a further improvement, a top layer of a second conductivity type is also formed in the drift region at the bottom of the drift region field oxide.

In a further improvement, a top layer of the second conductivity type is also formed at the bottom of the gate region and the gate region is in contact with the bottom top layer of the second conductivity type.

In a further improvement, a second gate structure formed by overlapping a gate dielectric layer and a polysilicon gate is formed on the surface of the gate region close to the second side, and the second side of the second gate structure also extends to the top surface of the drift region field oxide.

In a further improvement, a second source region composed of a heavily doped region of the first conductivity type is formed on the surface of the gate region and is self-aligned to the first side of the second gate structure.

In a further improvement, a gate contact region composed of a second conductive type heavily doped region is formed on the surface of the gate region.

In a further improvement, a second field oxide is spaced between the source region and the gate region.

In a further improvement, the top of the source region is connected to a source electrode formed by patterning a front metal layer through a contact hole.

The top of the gate region is connected to a gate formed by patterning the front side metal layer through a contact hole.

The top of the drain region is connected to a drain electrode formed by patterning the front metal layer through a contact hole.

In a further improvement, the number of turns of the polysilicon winding is more than 1.

The JFET device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type; or the JFET device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

The structure of the top of the drift region field oxide is arranged, and the eliminated drain-end polysilicon field plate can empty a forming space of the drain-end polysilicon field plate to form polysilicon winding, so that the number of the polysilicon winding turns can be increased, the more the number of the polysilicon winding turns are arranged on the same drift region field oxide size along the direction from a source region to a drain region, namely the X-axis direction, the X-axis area of a surface electric field curve of a device is increased when breakdown voltage occurs, and the breakdown voltage can be increased.

Drawings

The invention is described in further detail below with reference to the following figures and detailed description:

figure 1 is a cross-sectional view of a prior art JFET device;

figure 2 is a cross-sectional view of a JFET device according to an embodiment of the invention;

fig. 3 is a plot of the electric field strength distribution across the surface of the drift region of a prior art JFET device and a JFET device according to an embodiment of the invention;

fig. 4A-4D are schematic device structures at various steps in the fabrication of a JFET device according to embodiments of the invention.

Detailed Description

Fig. 2 is a cross-sectional view of a JFET device according to an embodiment of the invention; the JFET device comprises:

a first-conductivity-type-doped deep well region 102 is formed on the second-conductivity-type-doped semiconductor substrate 101.

A gate region 104 composed of a second conductive type doped region, a source region 108c composed of a first conductive type heavily doped region, and a drain region 108b composed of a first conductive type heavily doped region are formed on the surface of the selected region of the deep well region 102.

In the embodiment of the present invention, the gate region 104 is composed of a second conductive well region.

The source region 108c is located at a first side of the gate region 104 with a spacing between a second side of the source region 108c and the first side of the gate region 104. Preferably, a second field oxide 103a is spaced between the source region 108c and the gate region 104.

The drain region 108b is located on a first side of the gate region 104 with a spacing between the first side of the drain region 108b and a second side of the gate region 104.

The drift region is located between the second side of the gate region 104 to the first side of the drain region 108 b. The drift region is directly comprised of the deep well region 102 between the second side of the gate region 104 to the first side of the drain region 108 b.

The channel region is composed of the deep well region 102 between the bottom of the gate region 104 and the semiconductor substrate 101.

A drift region field oxide 103 is formed on top of the drift region.

A first side of the drift region field oxide 103 and a second side of the gate region 104 have a spacing.

A first side of the drain region 108b and a second side of the drift region field oxide 103 are self-aligned.

In the embodiment of the present invention, a second conductive type top layer 105 is further formed in the drift region at the bottom of the drift region field oxide 103. A top layer 105 of the second conductivity type is also formed at the bottom of the gate region 104 and the gate region 104 is in contact with the bottom top layer 105 of the second conductivity type.

A polysilicon winding 107b is formed on the drift region field oxide 103, the polysilicon winding 107b is formed by connecting multiple circles of polysilicon wires end to end, and the polysilicon winding 107b comprises a first connecting end and a second connecting end. In the embodiment of the present invention, the number of turns of the polysilicon winding 107b is greater than 1.

The first connection end is located on the polysilicon line closest to the first side of the drift region field oxide 103 and connected with a 0V potential, the second connection end is located on the polysilicon line closest to the second side of the drift region field oxide 103 and connected with a drain potential, and the potentials of the polysilicon lines of all circles are sequentially changed from the 0V potential to the drain potential in the direction from the first side of the drift region field oxide 103 to the second side of the drift region field oxide 103.

A drain-end polysilicon field plate is not arranged on the second side of the drift region field oxide 103, so that the second connection end is maximally close to the second side of the drift region field oxide 103, and the number of turns of the polysilicon winding 107b is maximized.

In the embodiment of the present invention, in a top view, the drift region field oxide 103 is in a surrounding structure, a first side of the drift region field oxide 103 is an inner side, and a second side of the drift region field oxide 103 is an outer side, the gate region 104 and the source region 108c are both located inside the drift region field oxide 103, and the drain region 108b is located outside the drift region field oxide 103. Each polysilicon line of the polysilicon winding 107b also has a surrounding structure. In other embodiments can also be: in a top view, the drift region field oxide 103 is in a strip structure, and each polysilicon wire of the polysilicon winding 107b is in a strip structure connected end to end, so that the polysilicon wires in the strip structure are connected end to form the polysilicon winding 107b in a Z shape.

A second gate structure formed by overlapping a gate dielectric layer 106 and a polysilicon gate 107 is formed on the surface of the gate region 104 near the second side, and the second side of the second gate structure further extends to the top surface of the drift region field oxide 103.

A second source region 108a, consisting of a heavily doped region of the first conductivity type, is formed at the surface of the gate region 104 and is self-aligned to the first side of the second gate structure. The second gate structure is used as a gate structure of the LDMOS. The second source region 108a serves as a source region of the LDMOS.

A gate contact region 109, which is a heavily doped region of the second conductivity type, is also formed on the surface of the gate region 104.

The top of the source region 108c is connected to a source electrode, which is denoted by S in fig. 2, patterned by a front metal layer 111 through a contact hole 110.

The top of the gate region 104 is connected to a gate, indicated by G in fig. 2, patterned from the front-side metal layer 111 through a contact hole 110.

The top of the drain region 108b is connected to a drain electrode, which is denoted by D in fig. 2, formed by patterning the front metal layer 111 through a contact hole 110.

In the embodiment of the invention, the JFET device is an N-type device, the first conduction type is an N type, and the second conduction type is a P type. In other embodiments can also be: the JFET device is a P-type device, the first conduction type is a P type, and the second conduction type is an N type.

In the embodiment of the invention, the structure at the top of the drift region field oxide 103 is arranged, and the eliminated drain-end polysilicon field plate can empty the forming space of the drain-end polysilicon field plate to form the polysilicon winding 107b, so that the number of turns of the polysilicon winding 107b can be increased, and the more the number of turns of the polysilicon winding 107b arranged on the same size of the drift region field oxide 103 along the direction from the source region 108c to the drain region 108b, namely the X-axis direction, the larger the X-axis area of the surface electric field curve of the device is increased when the breakdown voltage occurs, so that the breakdown voltage can be increased.

As shown in fig. 3, is a plot of the electric field intensity distribution at the surface of the drift region of a prior art JFET device and a JFET device according to an embodiment of the present invention; in fig. 3, the abscissa is the X-axis, the ordinate is the electric field strength of the drift region surface along the X-axis direction, the curve 301 is the curve of the conventional JFET device, and the curve 302 is the curve of the JFET device according to the embodiment of the present invention, and it can be seen that the curve 302 covers more X-axis dimensions, so that the breakdown voltage can be increased.

As shown in fig. 4A to 4D, the schematic device structure in each step of manufacturing the JFET device according to the embodiment of the present invention, taking an N-type JFET as an example, includes the steps of:

as shown in fig. 4A, the deep well region 102 is formed on the semiconductor substrate 101, and the deep well region 102 is formed by N-type ion implantation and thermal drive.

As shown in fig. 4B, active area lithography is used to open the field oxide region, etch the field oxide region, and grow field oxide, including the drift region field oxide 103 and the second field oxide 103 a.

As shown in fig. 4C, the well implantation region is opened by photolithography, a P-well implantation is performed to form the gate region 104, and a P-type implantation is performed to form a second conductivity type top layer, i.e., a P-type top layer (PTOP) 105.

As shown in fig. 4D, a gate dielectric layer 106, such as a gate oxide layer, is grown, polysilicon is deposited and is etched by photolithography to simultaneously form a polysilicon gate 107 and the polysilicon winding 107 b.

As shown in fig. 2, conventional source-drain ion implantation is selectively performed to form heavily N-doped regions 108a, 108b, and 108c and heavily P-doped region 109.

Depositing an interlayer film, etching to form an opening of the contact hole 110, and filling metal to form the contact hole 110; and depositing and patterning a front metal layer 111 to finish the manufacture of the device.

The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.