阅读说明：本技术 减少读干扰影响的方法、装置、设备及存储介质 (Method, device, equipment and storage medium for reducing read interference influence ) 是由 刘璨 霍文捷 万婷 刘攀 孙承华 于 2020-05-08 设计创作，主要内容包括：本申请公开了一种减少读干扰影响的方法、装置、设备及存储介质,属于计算机技术领域。所述方法包括：在目标块进行擦除判定后,达到所述目标块的擦除判定周期时,获取所述目标块的总擦除次数和在上一次擦除处理后的读次数；基于所述目标块的总擦除次数和所述在上一次擦除处理后的读次数,确定更新的擦除判定周期；将所述目标块的擦除判定周期,调整为所述更新的擦除判定周期。采用本申请可对SSD中各个块进行擦除判定的擦除判定周期进行动态调整,能够将存在Read Disturb的存储单元的个数控制在一定范围内,从而降低块中出现数据错误的可能性。(The application discloses a method, a device, equipment and a storage medium for reducing read interference influence, and belongs to the technical field of computers. The method comprises the following steps: after the target block is subjected to erasure judgment, when the erasure judgment period of the target block is reached, acquiring the total erasure times of the target block and the reading times after the last erasure processing; determining an updated erase decision period based on the total erase count of the target block and the read count after the last erase process; and adjusting the erasure decision period of the target block to the updated erasure decision period. By adopting the method and the device, the erasing judgment period for erasing judgment of each block in the SSD can be dynamically adjusted, and the number of the storage units with Read Disturb can be controlled within a certain range, so that the possibility of data errors in the blocks is reduced.)

1. A method of reducing read disturb effects, the method comprising:

after the target block is subjected to erasure judgment, when the erasure judgment period of the target block is reached, acquiring the total erasure times of the target block and the reading times after the last erasure processing;

determining an updated erase decision period based on the total erase count of the target block and the read count after the last erase process;

and adjusting the erasure decision period of the target block to the updated erasure decision period.

2. The method of claim 1, wherein the reaching of the erase decision period for the target block further comprises:

acquiring the position information of the target block and the error bit flipping number after the last erasing processing;

determining an updated erase decision period based on the total number of erases of the target block and the number of reads after the last erase process, including:

and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, and the location information.

3. The method of claim 2, wherein determining an updated erasure decision period based on the total number of erasures of the target block, the number of reads after the last erasure process, the number of error bit flips after the last erasure process, and the location information comprises:

and determining an updated erasure judgment cycle based on the total erasure number of the target block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained cycle calculation model.

4. The method of claim 3, wherein before determining the updated erasure decision period based on the total number of erasures for the target block, the number of reads after the last erasure process, the number of erroneous bit flips after the last erasure process, the location information, and the trained period calculation model, the method further comprises:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period;

and training the initial periodic calculation model based on the multiple groups of training data to obtain a trained periodic calculation model.

5. The method of claim 4, wherein obtaining a plurality of sets of training data, each set of training data including total number of sample erasures, number of sample reads, number of sample error bit flips, sample location information, and a reference erasure decision period comprises:

determining a plurality of sample blocks;

acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information;

for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and after acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information, and reaching an undetermined erasure judgment period allocated for the sample block, acquiring the use state information of the sample block;

determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block;

and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data.

6. The method according to claim 5, wherein the usage status information is an error bit flipping number after a last erasure process, and the sample obtaining condition is that the error bit flipping number is within a preset error bit flipping number range.

7. An apparatus for reducing read disturb effects, the apparatus comprising:

the first acquisition module is configured to acquire the total erasing times of a target block and the reading times after the last erasing processing when the erasing judgment period of the target block is reached after the erasing judgment of the target block is performed;

a determination module configured to determine an updated erase decision period based on the total number of times of erasing the target block and the number of times of reading after the last erasing process;

an adjustment module configured to adjust an erase decision period of the target block to the updated erase decision period.

8. The apparatus of claim 7, further comprising a second obtaining means configured to:

acquiring the position information of the target block and the error bit flipping number after the last erasing processing;

the determination module configured to: and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, and the location information.

9. The apparatus of claim 8, wherein the determination module is configured to:

and determining an updated erasure judgment cycle based on the total erasure number of the target block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained cycle calculation model.

10. The apparatus of claim 9, further comprising a training module configured to:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period;

and training the initial periodic calculation model based on the multiple groups of training data to obtain a trained periodic calculation model.

11. The apparatus of claim 10, wherein the training module is configured to:

determining a plurality of sample blocks;

acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information;

for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and after acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information, and reaching an undetermined erasure judgment period allocated for the sample block, acquiring the use state information of the sample block;

determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block;

and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data.

12. The apparatus of claim 11, wherein the usage status information is an error bit flipping number after a last erasure process, and the sample obtaining condition is that the error bit flipping number is within a preset error bit flipping number range.

13. A computer device comprising a processor and a memory, the memory having stored therein at least one instruction that is loaded and executed by the processor to perform operations performed by the method of reducing read disturb effects of any of claims 1 to 6.

Technical Field

The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a storage medium for reducing read disturb effect.

Background

SSD (Solid State Disk) is widely used in various fields as a new storage medium. The SSD is generally configured by a plurality of NANDs (flash memory devices), and each NAND is divided into a plurality of blocks (blocks), and each Block is divided into a plurality of pages (pages). When one Page in Block needs to be read, other unread pages are also applied with voltage. The applied voltage may cause the memory cells in the Page that are unread to pull in charge. As the number of reads of Block increases, the amount of charge absorbed in the memory cell also increases slowly, which causes a change in the data state in the memory cell, and errors may occur in reading data, which are collectively referred to as Read Disturb.

The method for solving the Read Disturb comprises the steps of recording the reading times of a Block, setting a reading time threshold, obtaining the reading times of the Block according to a preset detection period in the use process of an SSD, erasing the Block when the obtained reading times of the Block reach the reading time threshold, namely moving data stored in the Block to other blocks, and then clearing charges of a storage unit in the Block, so that the problem of the Read Disturb is solved. In addition, the detection period can be adjusted by obtaining parameters of the SSD, such as the temperature of the SSD and the average number of reads of all blocks in the SSD.

In the process of implementing the present application, the inventor finds that the prior art has at least the following problems:

due to the fact that the SSD comprises the plurality of blocks, in the using process of the SSD, the difference of the using conditions of each Block is large, the reading times of all the blocks in the SSD are obtained according to a uniform detection period, and the blocks are erased when the reading times of some blocks exceed a set reading time threshold value, and at this time, a large number of storage units possibly have the problem of Read Disturb.

Disclosure of Invention

The embodiment of the application provides a method, a device, equipment and a storage medium for reducing Read interference influence, which can control the number of storage units with Read Disturb in a certain range, thereby reducing the possibility of data errors in blocks. The technical scheme is as follows:

in one aspect, a method for reducing read disturb effects is provided, the method comprising:

after the target block is subjected to erasure judgment, when the erasure judgment period of the target block is reached, acquiring the total erasure times of the target block and the reading times after the last erasure processing;

determining an updated erase decision period based on the total erase count of the target block and the read count after the last erase process;

and adjusting the erasure decision period of the target block to the updated erasure decision period.

Optionally, when the erase decision period of the target block is reached, the method further includes:

acquiring the position information of the target block and the error bit flipping number after the last erasing processing;

determining an updated erase decision period based on the total number of erases of the target block and the number of reads after the last erase process, including:

and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, and the location information.

Optionally, the determining an updated erasure decision period based on the total erasure count of the target block, the read count after the last erasure processing, the error bit flipping count after the last erasure processing, and the location information includes:

and determining an updated erasure judgment cycle based on the total erasure number of the target block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained cycle calculation model.

Optionally, before determining an updated erasure decision period based on the total erasure count of the target block, the read count after the last erasure processing, the error bit flipping count after the last erasure processing, the location information, and the trained period calculation model, the method further includes:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period;

and training the initial periodic calculation model based on the multiple groups of training data to obtain a trained periodic calculation model.

Optionally, the obtaining multiple sets of training data, where each set of training data includes total sample erasure count, sample reading count, sample error bit flipping count, sample position information, and reference erasure determination period, includes:

determining a plurality of sample blocks;

acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information;

for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and after acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information, and reaching an undetermined erasure judgment period allocated for the sample block, acquiring the use state information of the sample block;

determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block;

and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data.

Optionally, the use state information is an error bit flipping number after the last erasure processing, and the sample obtaining condition is that the error bit flipping number is within a preset error bit flipping number range.

In another aspect, an apparatus for reducing read disturb effects is provided, the apparatus comprising:

the first acquisition module is configured to acquire the total erasing times of a target block and the reading times after the last erasing processing when the erasing judgment period of the target block is reached after the erasing judgment of the target block is performed;

a determination module configured to determine an updated erase decision period based on the total number of times of erasing the target block and the number of times of reading after the last erasing process;

an adjustment module configured to adjust an erase decision period of the target block to the updated erase decision period.

Optionally, the apparatus further includes a second obtaining device configured to:

acquiring the position information of the target block and the error bit flipping number after the last erasing processing;

the determination module configured to: and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, and the location information.

Optionally, the determining module is configured to:

and determining an updated erasure judgment cycle based on the total erasure number of the target block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained cycle calculation model.

Optionally, the apparatus further comprises a training module configured to:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period;

and training the initial periodic calculation model based on the multiple groups of training data to obtain a trained periodic calculation model.

Optionally, the training module is configured to:

determining a plurality of sample blocks;

acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information;

for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and after acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information, and reaching an undetermined erasure judgment period allocated for the sample block, acquiring the use state information of the sample block;

determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block;

and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data.

Optionally, the use state information is an error bit flipping number after the last erasure processing, and the sample obtaining condition is that the error bit flipping number is within a preset error bit flipping number range.

In yet another aspect, a computer device is provided and includes a processor and a memory, where at least one instruction is stored in the memory, and the at least one instruction is loaded and executed by the processor to implement the operations performed by the method for reducing the read disturb effect as described above.

In yet another aspect, a computer-readable storage medium having at least one instruction stored therein is provided, which is loaded and executed by a processor to perform the operations performed by the method for reducing read disturb effects as described above.

The technical scheme provided by the embodiment of the application has the following beneficial effects:

by acquiring the total erasing times of the target block and the reading times after the last erasing process, the erasing judgment period of the target block for the next erasing judgment is determined.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a flow chart of a method for reducing read disturb effects provided by an embodiment of the present application;

FIG. 2 is a flow chart of a method for reducing read disturb effects according to an embodiment of the present application;

FIG. 3 is a schematic structural diagram of an apparatus for reducing the effect of read disturb according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a computer device provided in an embodiment of the present application.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The embodiment of the application can be realized by a terminal, and the terminal can be a mobile phone, a notebook, a desktop and other various devices which take SSD as a storage medium.

SSDs are widely used in various fields as a new storage medium. The SSD is generally configured by a plurality of NANDs, each NAND is divided into a plurality of blocks, and each Block is divided into a plurality of pages. When one Page in Block needs to be read, other unread pages are also applied with voltage. The applied voltage may cause the memory cells in the Page that are unread to pull in charge. With the increase of the number of reading times of Block, the amount of charges absorbed in the memory cell will also increase slowly, which causes the Read threshold voltage corresponding to the memory cell to shift, and thus causes Read Disturb to appear.

The method for solving the Read Disturb at present comprises the steps of recording the reading times of each Block in the process of using an SSD, storing the reading times in a fixed storage position of the SSD, then obtaining the reading times of the Block according to a fixed detection period, and erasing the Block when the obtained reading times of the Block reach a preset reading time threshold value, namely moving data stored in the Block to other blocks, and then clearing charges of storage units in the Block, so that the problem of the Read Disturb is solved.

However, since the SSD includes a plurality of blocks, and in the use of the SSD, the use condition of each Block is different, so that the Read times of the blocks are obtained according to a fixed detection period, which may cause that some Read times of the blocks far exceed a set Read time threshold, the blocks are erased, and at this time, a large number of storage units may have a Read Disturb problem, or some Read times of the blocks are not many, but the performance of the SSD is affected due to obtaining the Read times of the blocks for multiple times. The method for reducing the read disturb effect provided by the embodiment of the application may determine an appropriate erasure decision period according to the current attribute information of each Block, and then obtain the read times of each Block according to the erasure decision period after determination, where the attribute information includes the current erasure times, read times, error bit flipping numbers, location information, and the like of the Block. Therefore, the erasure decision period corresponding to each Block can be dynamically adjusted according to the current attribute information of each Block. For example, when the number of reads to acquire a block does not reach the preset number of reads threshold, but is very close to the preset number of reads, the time length for acquiring the next number of reads of the block may be shortened, or the time length for acquiring the next number of reads of the block may be lengthened if the number of reads to acquire a block is much smaller than the preset number of reads threshold. In addition, the method for reducing the influence of the read disturbance provided by the embodiment of the application can be applied to various types of NAND flash memories, such as SLC, MLC, TLC, QLC and the like.

PEC (Program/Erase Cycle, number of erasures): the number of Block erasures in SSD.

ECC (Error Correcting Code): a technique capable of detecting a read error occurring in an SSD and correcting the detected error.

ErrorCount (error bit flip count): the ECC detects the number of the storage units with data errors in the storage units in the Block in the SSD.

ReadCount: and clearing the read times of the Block in the SSD, wherein the corresponding ReadCount value is cleared after the Block is erased.

Fig. 1 is a flowchart of a method for reducing the effect of read disturb according to an embodiment of the present disclosure. Referring to fig. 1, the embodiment includes:

step 101, after the target block is subjected to the erasure judgment, when the erasure judgment period of the target block is reached, acquiring the total erasure number of the target block and the reading number after the last erasure processing.

In implementation, an erasure decision period may be set in the terminal, and when the set erasure decision period is reached after the SSD in the terminal starts working, an erasure decision may be performed once, that is, the read number and the error bit flipping number of each Block in the SSD are obtained, and the read number and the error bit flipping number of each Block are determined whether or not are greater than the set read number threshold and the error bit flipping number threshold. When the reading times of the target block exceed a preset reading time threshold or the error bit turnover number exceeds an error bit turnover number threshold, the target block can be erased; when neither the read count nor the error bit flip count of the target block exceeds the corresponding threshold, the erase process is not performed. After the target block is subjected to the erasure judgment, the total erasure processing times of the target block and the reading times of the target block after the last erasure processing can be obtained, so as to calculate the erasure judgment period of the target block for performing the erasure judgment next time. When the SSD operates for the first time, the erase decision period corresponding to each block may be an initial erase decision period set by a technician.

Step 102, determining an updated erase decision period based on the total erase count of the target block and the read count after the last erase process.

In implementation, after the total erase count of the target block and the read count after the last erase processing are obtained, the total erase count of the target block and the read count after the last erase processing may be input to the trained cycle calculation model, so as to obtain an erase determination cycle for performing the next erase determination on the target block.

In another possible scheme, the position information of the target block and the number of error bit flips after the last erase process may also be obtained, and the updated erase decision period may be determined based on the total erase count of the target block, the number of reads after the last erase process, the number of error bit flips after the last erase process, and the position information. The corresponding processing is as follows: and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained period calculation model.

After obtaining the total erase count of the target block, the read count after the last erase process, the position information of the target block, and the error bit flipping count after the last erase process, the total erase count of the target block, the read count after the last erase process, the error bit flipping count after the last erase process, and the position information may be input to a trained period calculation model, so as to obtain an erase determination period for performing the next erase determination on the target block.

Taking the obtained data as the total erasing times of the target block, the reading times after the last erasing process, the position information of the target block and the error bit flipping number after the last erasing process as an example, the corresponding periodic calculation model training process can be as follows:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period; and training the initial periodic calculation model based on a plurality of groups of training data to obtain a trained periodic calculation model.

In implementation, a large number of blocks at different positions can be obtained according to experiments, and the reference erasure determination period corresponding to the blocks at different total erasure processing times, different reading times, and different error bit flipping times is a time length suitable for performing next erasure determination on each block. And acquiring the total sample erasing processing times, the sample reading times, the sample error bit flipping times and the corresponding reference erasing judgment period. I.e. obtaining a large number of x₁、x₂、x₃、x₄And corresponding y, wherein x₁As the total number of times of erasing process, x₂For the number of reads, x₃Number of erroneous bit flips, x₄For positional information, y is the corresponding reference erase decision period, then based on a number x₁、x₂、x₃、x₄And y, training the initial periodic calculation model to obtain a trained periodic calculation model, namely x₁、x₂、x₃、x₄And y is the corresponding relation ax₁+bx₂+cx₃+dx₄＝y。

In the training process, the total sample erasing processing times, the sample reading times and the sample error bit flipping numbers can be input into an initial period calculation model to obtain an initial erasing judgment period, and then parameters in the initial period calculation model are adjusted according to a difference value square between a reference erasing judgment period corresponding to the total sample erasing processing times, the sample reading times and the sample error bit flipping numbers and the initial erasing judgment period as a first loss function, namely values of a, b, c and d in the formula are adjusted to enable the value of the first loss function to approach to 0. In this case, the adjustment of a, b, c, and d in the formula may be performed by using a gradient descent method, a solution formula of a variation of the gradient descent method, or the like, so that the value of the first loss function approaches 0.

Wherein the first loss function is as follows:

y_ifor the corresponding reference erase decision period,the output erase decision period is formulated.

In addition, in order to avoid overfitting of the period calculation model, the parameters in the initial period calculation model can be adjusted by taking the difference square sum absolute value of the initial erasure decision period and the reference erasure decision period output by the initial period calculation model as a second loss function, so as to obtain the trained period calculation model.

The second loss function is as follows:

y_ifor the corresponding reference erase decision period,the output erase decision period is formulated.

It should be noted that, when the total erasure count of the target block and the read count after the last erasure processing are input into the period calculation model to obtain the erasure decision period, the sample data required for training of the corresponding period calculation model are the total erasure count of the sample, the sample read count and the corresponding reference erasure decision period, and the training process is the same as the above-mentioned training process, and is not described here again.

Optionally, the process of obtaining the total number of times of erasing the sample, the number of times of reading the sample, the number of times of bit flipping with sample error, the sample position information, and the reference erasure determination period is as follows: determining a plurality of sample blocks; acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information; for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and acquiring the use state information of the sample block when the undetermined erasure judgment period distributed for the sample block is reached after the total erasure number of the sample block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information are acquired; determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block; and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data. The use state information is the number of error bit flipping times after the last erasing process, and the sample obtaining condition is that the number of error bit flipping times is within a preset range of the number of error bit flipping times.

In implementation, a technician may obtain, through experiments, the total number of times of erasing processing of a sample, the number of times of bit flipping of an error bit of the sample, the number of times of reading the sample, the position information of the sample, and the corresponding reference erasure determination period. First, a plurality of sample blocks are determined, a sample block may be a block at any position in the SSD, and when the sample block reaches the erasure decision period, the total erasure processing number, the error bit flipping number, the read number, and the position information of the sample block may be acquired. The technical staff can randomly set different undetermined erasure judging periods for the sample block and simulate the normal use process, when the time length passes through the undetermined erasure judging period, the number of error bit flipping numbers of the sample block after the undetermined erasure judging period is obtained, if the number of error bit flipping numbers after the undetermined erasure judging period meets preset sample obtaining conditions, the sample block is an effective sample block, then the undetermined erasure judging period is determined as a reference erasure judging period, and the total erasure processing times, the number of error bit flipping numbers, the reading times and the position information corresponding to the reference erasure judging period are used as the total erasure processing times, the number of sample error bit flipping numbers, the sample reading times and the sample position information.

The error bit flipping number is the number of memory cells where a read error occurs when data is read, and since the ECC has an error correction capability, when the error bit flipping number of a block is within a certain range, a read error occurring when reading the block can be corrected by the ECC error correction capability, and when the error bit flipping number exceeds a certain range, all read errors cannot be corrected by only the error correction capability of the ECC, and there may be a large number of read errors. It is possible to determine whether or not it is appropriate to set the erasure decision period for the block according to the number of erroneous bit flips. That is, the sample obtaining condition may be set such that the number of erroneous bit flips is 0 or close to 0 after a block is erased in a preset range of the number of erroneous bit flips, and the time duration of the time duration is an erasure determination period, and it is determined that the erasure determination period set for the block may be short; when the elapsed time length of a block after the block is subjected to the erasure processing is an erasure determination period and the number of erroneous bit flips obtained for the block is a large value, it can be determined that the erasure determination period set for the block may be long. Therefore, a technician can set a range of the number of erroneous bit flips according to the ECC error correction capability, and when a block is erased and the duration of the block is the erase determination period, it can be determined that the erase determination period set for the block is proper, and if the erase determination period is longer, the number of erroneous bit flips in the block may increase, so that more data of the memory cells are erroneous, and the ECC cannot be corrected.

Step 103, the erase decision period of the target block is adjusted to the updated erase decision period.

In an implementation, when the cycle calculation model outputs an updated erasure decision cycle for a block, the updated erasure decision cycle may be set as an erasure decision cycle for the current block to make the next erasure decision. As shown in fig. 2, when the erase determination period after the update is long, the read number of the target block and the number of error bit flips can be obtained, if the read number of the target block exceeds the set read number threshold or the number of error bit flips exceeds the set number of error bit flips, the target block can be erased, then the total erase processing number, the read number, the number of error bit flips, and the position information of the target block after the erase processing are input into the period calculation model, the erase determination period after the update is obtained, and then the target block performs erase determination according to the erase determination period after the update; and if the reading times and the error bit flipping numbers of the target block are smaller than the corresponding reading times threshold and the corresponding error bit flipping numbers, inputting the current total erasing processing times, the reading times, the error bit flipping numbers and the position information of the target block into a period calculation model to obtain an erasing judgment period after being updated again, and then performing erasing judgment on the target block according to the erasing judgment period after being updated again.

The method and the device for determining the erasure judgment period of the target block for the next erasure judgment are determined by obtaining the total erasure times of the target block and the Read times after the last erasure processing, and therefore the erasure judgment period for the erasure judgment of each block in the SSD can be dynamically adjusted, the number of the storage units with Read Disturb can be controlled within a certain range, and the possibility of data errors in the blocks is reduced.

All the above optional technical solutions may be combined arbitrarily to form the optional embodiments of the present disclosure, and are not described herein again.

Fig. 3 is a diagram of an apparatus for reducing the influence of read disturb according to an embodiment of the present application, where the apparatus may be a terminal in the foregoing embodiment, and as shown in fig. 3, the apparatus includes:

a first obtaining module 310, configured to obtain a total erasing number of a target block and a reading number after a last erasing process when an erasing determination period of the target block is reached after an erasing determination is performed on the target block;

a determining module 320 configured to determine an updated erase decision period based on the total number of times of erasing the target block and the number of times of reading after the last erasing process;

an adjusting module 330 configured to adjust the erase decision period of the target block to the updated erase decision period.

Optionally, the apparatus further includes a second obtaining device configured to:

acquiring the position information of the target block and the error bit flipping number after the last erasing processing;

the determination module configured to: and determining an updated erasure decision period based on the total erasure number of the target block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing, and the location information.

Optionally, the determining module 330 is configured to:

and determining an updated erasure judgment cycle based on the total erasure number of the target block, the reading number after the last erasure processing, the error bit flipping number after the last erasure processing, the position information and the trained cycle calculation model.

Optionally, the apparatus further comprises a training module configured to:

acquiring a plurality of groups of training data, wherein each group of training data comprises total sample erasing times, sample reading times, sample error bit overturning numbers, sample position information and a reference erasing judgment period;

and training the initial periodic calculation model based on the multiple groups of training data to obtain a trained periodic calculation model.

Optionally, the training module is configured to:

determining a plurality of sample blocks;

acquiring the total erasing times of each sample block when the corresponding erasing judgment period is reached, the reading times after the last erasing treatment, the error bit flipping number after the last erasing treatment and position information;

for each sample block, when the sample block reaches a corresponding erasure judgment period, acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and position information, and after acquiring the total erasure number of the sample block, the read number after the last erasure processing, the error bit flipping number after the last erasure processing and the position information, and reaching an undetermined erasure judgment period allocated for the sample block, acquiring the use state information of the sample block;

determining a sample block of which the corresponding use state information meets a preset sample acquisition condition as an effective sample block;

and respectively determining the total erasing times, the reading times after the last erasing process, the error bit flipping times after the last erasing process, the position information and the to-be-erased judging period corresponding to each effective sample block as each group of training data, wherein the training data comprises the total sample erasing times, the sample reading times, the sample error bit flipping times, the sample position information and the reference erasing judging period, and forming the training data.

Optionally, the use state information is an error bit flipping number after the last erasure processing, and the sample obtaining condition is that the error bit flipping number is within a preset error bit flipping number range.

It should be noted that: in the device for reducing the influence of read disturb according to the above embodiment, when reducing the influence of read disturb, only the division of each functional module is illustrated, and in practical applications, the function distribution may be completed by different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus for reducing the influence of read interference and the method for reducing the influence of read interference provided by the above embodiments belong to the same concept, and specific implementation processes thereof are described in the method embodiments in detail and are not described herein again.

Fig. 4 shows a block diagram of a terminal 400 according to an exemplary embodiment of the present application. The terminal 400 may be: a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III, motion video Experts compression standard Audio Layer 3), an MP4 player (Moving Picture Experts Group Audio Layer IV, motion video Experts compression standard Audio Layer 4), a notebook computer, or a desktop computer. The terminal 400 may also be referred to by other names such as user equipment, portable terminal, laptop terminal, desktop terminal, etc.

Generally, the terminal 400 includes: a processor 401 and a memory 402.

Processor 401 may include one or more processing cores, such as a 4-core processor, an 8-core processor, or the like. The processor 401 may be implemented in at least one hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), and a PLA (Programmable Logic Array). The processor 401 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 401 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 401 may further include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

Memory 402 may include one or more computer-readable storage media, which may be non-transitory. Memory 402 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 402 is used to store at least one instruction for execution by processor 401 to implement a method of reducing read disturb effects as provided by method embodiments herein.

In an exemplary embodiment, a computer-readable storage medium, such as a memory, including instructions executable by a processor in a terminal to perform a method of reducing read disturb effects in the embodiments described below is also provided. For example, the computer readable storage medium may be a ROM, a Random Access Memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.

The above description is intended to be exemplary only, and not to limit the present application, and any modifications, equivalents, improvements, etc. made within the spirit and scope of the present application are intended to be included therein.