阅读说明：本技术 存储装置和存储装置的重新训练方法 (Storage device and retraining method of storage device ) 是由 金东成 李将雨 李善奎 尹治元 任政燉 于 2021-04-01 设计创作，主要内容包括：公开了存储装置和存储装置的重新训练方法。所述存储装置包括NVM封装件和控制器,控制器通过通道连接到NVM封装件,并且控制NVM封装件的操作。NVM封装件包括接口芯片、第一NVM装置和第二NVM装置,第一NVM装置通过第一内部通道连接到接口芯片,第二NVM装置通过第二内部通道连接到接口芯片。接口芯片响应于从控制器接收的操作请求来选择第一内部通道,并且将第一内部通道连接到所述通道。接口芯片还确定是否需要与第二内部通道有关的重新训练,并且在需要重新训练时将重新训练请求发送到控制器。(A storage device and a method of retraining a storage device are disclosed. The storage device includes an NVM package and a controller connected to the NVM package by a channel and controlling operation of the NVM package. The NVM package includes an interface chip, a first NVM device connected to the interface chip by a first internal channel, and a second NVM device connected to the interface chip by a second internal channel. The interface chip selects a first internal channel in response to an operation request received from the controller, and connects the first internal channel to the channel. The interface chip also determines whether retraining is required in connection with the second internal channel and sends a retrain request to the controller when retraining is required.)

1. A memory device, comprising:

a non-volatile memory package; and

a controller connected to the non-volatile memory package through the channel and configured to control the non-volatile memory package,

wherein the non-volatile memory package includes an interface chip, a first non-volatile memory device connected to the interface chip through a first internal channel, and a second non-volatile memory device connected to the interface chip through a second internal channel,

the interface chip is configured to: the method includes selecting a first internal channel in response to an operation request received from a controller, connecting the first internal channel to the channel, and determining whether retraining is required in relation to a second internal channel, and sending a retrain request to the controller when retraining is required.

2. The memory device of claim 1, wherein the interface chip outputs a retrain request to the controller through at least one dedicated pin when it is determined that retrain is required.

3. The memory device of claim 1, wherein the interface chip includes a retraining checking circuit configured to: it is determined whether retraining is required in connection with the second internal passage.

4. The storage device of claim 3, wherein the operation request is a read request, and

the interface chip includes an activation signal generator configured to: chip select information is received and an activation signal is generated in response to a read enable signal to activate the retraining check circuit.

5. The memory device of claim 4, wherein the interface chip further comprises a chip enable signal decoder configured to: at least one chip enable signal is received from the controller, and chip selection information is output.

6. The storage device of claim 3, wherein the operation request is a read request, and

the interface chip includes a counter configured to: the method includes receiving chip selection information, counting a read enable signal to generate a count value for activating a retraining check circuit, and generating an activation signal by comparing the count value with a reference value.

7. The memory device of claim 6, wherein the interface chip further comprises a reference value storage device configured to store a reference value.

8. The memory device of claim 1, wherein the interface chip outputs a retrain request to the controller using a status read operation when it is determined that retrain is required.

9. The memory device of claim 8, wherein the interface chip further comprises logic circuitry configured to: the output value of the retraining checking circuit is compared with a status read result value corresponding to the status read command.

10. The storage device of claim 1, wherein the operation request is a write request, and

the interface chip determines whether retraining is required while performing a write operation to a non-volatile memory device connected to the first internal channel in response to a write request.

11. A memory device, comprising:

a non-volatile memory package including an interface chip, a first non-volatile memory device connected to the interface chip through a first internal channel, and a second non-volatile memory device connected to the interface chip through a second internal channel,

wherein the interface chip is configured to: selecting one of the first and second internal passages such that one of the first and second internal passages is designated as a selected internal passage and the other of the first and second internal passages is designated as an unselected internal passage, and

the interface chip is further configured to: determining whether retraining of the unselected internal channels is required, and upon determining that retraining of the unselected internal channels is required, providing a retrain request; and

a controller connected to the interface chip through a channel, wherein the controller is configured to: in response to the retrain request, a retrain command is sent to the non-volatile memory enclosure.

12. The storage device of claim 11, wherein the controller is further configured to: the status read command is transmitted to the interface chip using one of a DQ signal and a write enable signal, and a retrain request corresponding to the status read command is received using one of a DQ signal and a DQs signal provided by the interface chip.

13. The memory device of claim 11 or claim 12, wherein the controller periodically receives a retrain request from the interface chip through a dedicated pin.

14. The storage device of claim 11 or claim 12, wherein the controller provides one of a write request and a read request to the non-volatile memory package.

15. A method of retraining a storage device, the method comprising:

determining, by the interface chip, whether retraining is required in connection with the unselected internal channels; and

when it is determined that retraining is required, a retraining request is sent from the interface chip to the controller.

16. The retraining method of claim 15, further comprising:

one of the write request and the read request is sent to the corresponding non-volatile memory device using the selected internal channel.

17. The retraining method of claim 15, wherein the step of determining whether retraining is required comprises:

activating a retraining check circuit in response to a read enable signal;

outputting the expected data to the unselected internal channels;

receiving sample data from the unselected internal channel;

comparing the expected data with the sampled data; and

a retraining request is generated based on the comparison of the expected data to the sampled data.

18. The retraining method of claim 15, wherein the step of determining whether retraining is required comprises:

counting the DQS signals of the unselected internal channels to generate a count value;

comparing the count value with a reference value; and

and generating a retraining request according to the comparison result of the counting value and the reference value.

19. The retraining method of any one of claims 15 to 18, wherein the step of sending a retraining request to a controller comprises:

performing logic calculation on a state read value corresponding to the state read command and a retraining request corresponding to the determined result; and

the logical calculated value is sent to the controller.

20. The retraining method of any one of claims 15 to 18, wherein the step of sending a retraining request to a controller comprises:

the retraining request is sent via a dedicated pin.

Technical Field

Embodiments of the inventive concepts generally relate to memory devices and methods of retraining non-volatile memory devices (hereinafter, individually or collectively "NVM") that make up memory devices.

Background

The use of various error detection and/or correction techniques is known to be particularly useful for volatile and non-volatile memories. Many memory devices, including NVMs, are equipped with controllers that are capable of training (or calibrating) the NVM in the memory device to detect and/or minimize data errors.

In general, the operating frequency of a memory device may vary with power and/or temperature conditions, resulting in signal propagation delays, noise, and/or signal timing skew (signal timing skew), all of which degrade data integrity. Therefore, the memory device needs to better align the data signals through a retrain operation between the controller and the NVM in order to compensate for data degradation.

Disclosure of Invention

Certain embodiments of the inventive concept provide a memory device that is capable of retraining an NVM without time and/or region limitations. Other embodiments of the inventive concept provide methods of retraining storage devices.

According to an embodiment of the inventive concept, a memory device includes: a non-volatile memory (NVM) package; and a controller connected to the NVM package through the channel and configured to control operation of the NVM package. The NVM package includes an interface chip, a first NVM device connected to the interface chip by a first internal channel, and a second NVM device connected to the interface chip by a second internal channel, the interface chip configured to: the method includes selecting a first internal channel in response to an operation request received from the controller, connecting the first internal channel to the channel, and determining whether retraining is required in relation to a second internal channel, and sending a retrain request to the controller when retraining is required.

According to an embodiment of the inventive concept, a memory device includes: a non-volatile memory (NVM) package, the NVM package including an interface chip, a first NVM device, and a second NVM device, the first NVM device being connected to the interface chip by a first internal channel, the second NVM device being connected to the interface chip by a second internal channel, wherein the interface chip is configured to select one of the first internal channel and the second internal channel, thereby designating the one of the first internal channel and the second internal channel as the selected internal channel, and designating the other of the first internal channel and the second internal channel as an unselected internal channel, and the interface chip is further configured to: determining whether retraining of the unselected internal channels is required, and upon determining that retraining of the unselected internal channels is required, providing a retrain request; and a controller connected to the interface chip through a channel, wherein the controller is configured to: in response to the retrain request, a retrain command is sent to the NVM package.

According to an embodiment of the inventive concept, a method of retraining a storage device includes: determining, by the interface chip, whether retraining is required in connection with the unselected internal channels; and sending a retrain request from the interface chip to the controller when it is determined that retrain is required.

Drawings

The above and other aspects, features and advantages of the inventive concept may be better understood by reviewing the following detailed description in conjunction with the accompanying drawings, wherein:

fig. 1 is a diagram illustrating a memory device according to an embodiment of the inventive concept;

FIG. 2 is a diagram illustrating a non-volatile memory device NVM according to an embodiment of the inventive concept;

fig. 3A and 3B are perspective views illustrating a memory block according to an embodiment of the inventive concept, respectively;

fig. 4 is a diagram illustrating an interface chip according to an embodiment of the inventive concept;

FIG. 5 is a diagram illustrating a retraining check of an interface chip according to an embodiment of the inventive concept;

FIG. 6 is a diagram illustrating the operation of a retraining check circuit implemented as a BIST circuit;

FIG. 7 is a diagram illustrating the operation of a retraining check circuit implemented as an oscillator;

fig. 8 is a diagram illustrating an activation process of a retraining check circuit RCC using DQ/DQs/nRE signals according to an embodiment of the inventive concept;

fig. 9 is a diagram illustrating an activation process of a retraining check circuit RCC using a write/read command signal according to an embodiment of the inventive concept;

FIG. 10 is a ladder diagram illustrating the operation of a retraining check of a storage device according to an embodiment of the inventive concept;

FIG. 11 is a ladder diagram illustrating the operation of a retraining check of a storage device according to an embodiment of the inventive concept;

fig. 12 is a diagram illustrating a method of transmitting a retrain request of an interface chip to a controller according to an embodiment of the inventive concept;

fig. 13 is a diagram illustrating a method of transmitting a retrain request of an interface chip to a controller according to an embodiment of the inventive concept;

fig. 14 is a diagram illustrating a nonvolatile memory package 100 implemented as a stacked type nonvolatile memory package according to an embodiment of the inventive concept;

fig. 15 is a diagram illustrating a memory device according to an embodiment of the inventive concept;

fig. 16 is a diagram illustrating a storage device according to an embodiment of the inventive concept;

fig. 17 is a diagram illustrating a memory device according to an embodiment of the inventive concept;

fig. 18 is a flowchart outlining a method of operation of an interface chip according to an embodiment of the inventive concept;

fig. 19 is a flowchart outlining a method of operation of a controller according to an embodiment of the inventive concept;

fig. 20 is a diagram illustrating a storage device according to an embodiment of the inventive concept;

fig. 21 is a block diagram illustrating a computing system according to an embodiment of the inventive concept;

fig. 22 is a diagram illustrating a mobile device according to an embodiment of the inventive concept;

fig. 23 is a block diagram illustrating an electronic system according to an embodiment of the inventive concept; and

fig. 24 is a diagram illustrating a data center to which a memory device is applied according to an embodiment of the inventive concept.

Detailed Description

Hereinafter, specific embodiments of the inventive concept will be described with reference to the accompanying drawings.

Embodiments of the inventive concepts include a memory device capable of determining whether retraining is required using unselected channels in a memory input/output (I/O) fabric, and performing retraining using a buffer chip according to the determination.

Fig. 1 is a block diagram illustrating a memory device 10 according to an embodiment of the inventive concept. Referring to fig. 1, a memory device 10 may include an NVM package (NVM PCKG)100 and a memory Controller (CNTL)200, the memory Controller (CNTL) (hereinafter, also referred to as controller) 200 being configured to control the NVM package 100.

NVM package 100 may include an interface chip 110 (e.g., a frequency boost interface chip (FBI) or a buffer chip) and a plurality of NVMs 120, the plurality of NVMs 120 being connected to the interface chip 110 (e.g., via a first internal channel ICH1 and a second internal channel ICH 2). Here, it should be noted that more than two (2) internal channels may be used to connect the NVM to the interface chip 110.

The interface chip 110 may be connected to the controller 200 through the channel CH such that the channel CH may be efficiently and flexibly connected to one or more of the available internal channels (e.g., the first internal channel ICH1 and/or the second internal channel ICH2) through the interface chip 110.

In the illustrated example of fig. 1, the interface chip 110 includes a Retrain Check Circuit (RCC)111, the Retrain Check Circuit (RCC)111 being capable of determining whether internal retrain of the NVM is required and controlling execution of a retrain method between the interface chip 110 and the NVM package 100 in response to the determination.

The Retraining Check Circuit (RCC)111 may be configured to use, for example, an unselected internal channel (hereinafter, "unselected channel") between the first internal channel ICH1 and the second internal channel ICH2 to determine whether retraining is required. For example, the retraining checking circuit 111 may include a built-in self-test (BIST) circuit, an oscillator, and/or a Delay Locked Loop (DLL).

In effect, the Retraining Checking Circuit (RCC)111 effectively designates one of the available internal channels as the selected internal channel and also designates another of the available internal channels as the unselected internal channel.

Regardless of the particular implementation and/or configuration, the retraining checking circuit 111 may be used to check the alignment status between test mode data (i.e., expected data) that has passed through the data transmission path of the unselected channel and the clock signal that has passed through the clock transmission path of the unselected channel. The results of these alignment status checks can be used to determine whether retraining of the unselected channels is required.

Each of NVMs 120 can be implemented differently to store single-layer data (SLC) and/or multi-layer data (MLC). One or more NVMs 120 may be connected to each of the first internal channel ICH1 and/or the second internal channel ICH 2. In fig. 1, four (4) NVMs may be connected to each of the internal channels ICH1 and ICH2, but the number of NVMs connected to the internal channels ICH1 and ICH2 may vary according to design.

At least one of NVMs 120 can be used to store a boot loader. In this regard, the boot loader may be used, in whole or in part, as an initialization program that may be used to initialize the operation of the storage device 10. Those skilled in the art will recognize that NVM package 100 can be implemented differently using lateral and/or vertical stacking arrangements of NVM 120.

Memory Controller (CNTL)200 may be implemented to control the overall operation of NVM package 100. The memory controller 200 may define and/or control various functions required for management of data stored by the NVM package 100 (e.g., address mapping, error detection and/or correction, garbage collection, wear leveling, bad block management, etc.). Such functionality may be implemented using hardware, software, and/or firmware.

The controller 200 may receive a retrain request generated by the NVM package 100 and transmitted from the NVM package 100. In response to the retrain request, the controller 200 may issue a retrain command and send the retrain command to the NVM package 100. Thus, NVM package 100 can perform retraining operations with respect to unselected channels.

The retraining operation may include one or more data training operations (e.g., read training operations and/or write training operations). Here, the read training operation may include an operation of effectively centering the data strobe signal DQS output from the NVM device connected to the unselected channel on an eye pattern (eye pattern) of read data, and the write training operation may include an operation of aligning an eye pattern of data written to the NVM using the unselected channel.

The memory device may perform an initial training operation of the NVM after power-up in order to properly obtain optimal alignment conditions between data and clock signals in order to perform various operations (such as write operations and/or read operations). After the initial training operation (e.g., once a predetermined period of time has elapsed), deviations between the data and clock signals may occur due to, for example, changes in the operating environment of the memory device. Alternatively or additionally, when a particular failure condition is noted during the performance of a write operation and/or a read operation (e.g., a particular bit error rate or number of bit errors is exceeded), a retrain operation may be performed again to correct alignment between data and the clock signal.

Some compare memory devices may create duplicate paths from the trained I/O blocks using DQ-DQS including mismatches to check for the need for retraining of memory inputs and outputs, or may periodically perform retraining using an intermediate portion of normal I/O operations. However, these approaches may have time limitations and/or area limitations in creating the duplicate path.

In contrast, the memory device according to an embodiment of the inventive concept may check whether retraining is required using the interface chip 110 without such time and/or region limitation, and thereafter may inform the controller 200 whether the NVM needs retraining. For example, memory device 10 of fig. 1 may perform normal read/write operations using the selected internal channel (hereinafter, "selected channel"), but may simultaneously (i.e., at least partially overlap in time) use (or in relation to) the unselected channels to determine whether retraining of the NVM is required. And as a result of the retraining determination, memory device 10 may perform a retraining operation on the NVM.

Fig. 2 is a block diagram illustrating an exemplary NVM120 according to an embodiment of the inventive concept. Referring to fig. 2, NVM120 includes a memory cell array 121, an address decoder 122, a voltage generation circuit 123, an input and output circuit 124, and control logic 125.

NVM120 may be implemented as NAND flash, vertical NAND flash (VNAND), exclusive-or NOR flash, Resistive Random Access Memory (RRAM), phase change memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or spin torque transfer random access memory (STT-RAM). In the following description, it is assumed that NVM120 is implemented as a vertical NAND flash memory device.

Memory cell array 121 may include a plurality of memory blocks BLK1 through BLKz. Each of the memory blocks BLK1 through BLKz may be connected to the address decoder 122 through a word line WL, at least one string selection line SSL, and at least one ground selection line GSL, and may be connected to the input/output circuit 124 through a bit line BL. In this example embodiment, the word line WL may have a stacked plate structure.

The memory blocks BLK1 through BLKz may include strings having a three-dimensional structure, which may be arranged according to first and second directions (different from the first direction) and a third direction (a direction perpendicular to a plane formed in the first and second directions) on the substrate. Each string may include at least one string selection transistor, a memory cell, and at least one ground selection transistor connected in series between a bit line and a Common Source Line (CSL). Each memory cell may be implemented to store at least one bit at the intersection of a word line WL and a bit line BL. In one exemplary embodiment, at least one dummy cell may be included between the at least one string selection transistor and the plurality of memory cells. In another example embodiment, at least one dummy cell may be included between the memory cell and the at least one ground select transistor.

Address decoder 122 may be implemented to select one of memory blocks BLK1 through BLKz in response to an address. In addition, the address decoder 122 may be connected to the memory cell array 121 through word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. The address decoder 122 may select the word line WL, the string selection line SSL, and the ground selection line GSL using the decoded row address. In addition, the address decoder 122 may decode a column address among the input addresses. The decoded column address may be sent to input and output circuitry 124. In one example embodiment, the address decoder 122 may include a row decoder, a column decoder, an address buffer, and the like.

The voltage generation circuit 123 may be implemented to generate voltages (a program voltage, a pass voltage, a read pass voltage, a verify voltage, an erase voltage, a common source line voltage, a well voltage, etc.) required for the operation of the voltage generation circuit 123. The voltage generation circuit 123 may generate a word line voltage required for a program/read/erase operation.

The input and output circuit 124 may be connected to the memory cell array 121 through a bit line BL. Input and output circuitry 124 may be implemented to receive decoded column addresses from address decoder 122. The input and output circuit 124 may select the bit line BL using the decoded column address. The input and output circuits 124 may include a page buffer, which may store data to be programmed during a program operation or may store data read during a read operation. Each page buffer may include a plurality of latches. During a program operation, data stored in the page buffer may be programmed in a page corresponding to a selected memory block through the bit lines BL. During a read operation, data read from a page corresponding to a selected memory block may be stored in the page buffer through the bit line BL. The input and output circuit 124 may read data from a first region of the memory cell array 121 and may store the read data in a second region of the memory cell array 121. For example, the input and output circuitry 124 may be implemented as a copy-back (copy-back) execution.

The control logic 125 may be implemented to control the overall operation (program/read/erase, etc.) of the non-volatile memory device 100. The control logic 125 may operate in response to a control signal CTRL or a command input from an external entity.

Fig. 3A is a perspective view illustrating a memory block according to an embodiment of the inventive concept. Referring to fig. 3A, the memory block BLK1 may be formed in a direction perpendicular to the substrate SUB. An N + doped region may be formed on the substrate SUB.

Gate electrode layers and insulating layers may be alternately deposited on the substrate SUB. An information storage layer may be formed between the gate electrode layer and the insulating layer. When the gate electrode layer and the insulating layer are vertically patterned, a V-shaped pillar (pilar) may be formed. The pillars may penetrate the gate electrode layer and the insulating layer, and may be connected to the substrate SUB. The interior of the pillars may be filled with an insulating material (such as silicon oxide) in a filled dielectric pattern. The outer portions of the pillars may be formed of channel semiconductors in the vertical active pattern.

The gate electrode layer of the memory block BLK1 may be connected to the ground selection line GSL, the word lines WL1 to WL8, and the string selection line SSL. In addition, pillars of the memory block BLK1 may be connected to the bit lines BL1 to BL 3. In fig. 3A, a single memory block BLK1 may have two select lines GSL and SSL, eight (8) word lines WL 1-WL 8, and three (3) bit lines BL 1-BL 3, but example embodiments of the single memory block BLK1 are not limited thereto.

Fig. 3B is a perspective view illustrating a memory block according to another embodiment of the inventive concept. Referring to fig. 3B, for convenience of description, it may be assumed that the number of layers of word lines in the memory block BLKb is four (4). The memory block BLKb may be implemented to have a bit cost scalable (BiCS) structure that pipe transfers (pipe) lower ends of adjacent memory cells connected in series with each other. The memory block BLKb may include M × N (M and N are positive integers) strings NS.

Each string NS may include memory cells connected in series. The first upper ends of the memory cells may be connected to the string selection transistor SST, the second upper ends of the memory cells may be connected to a Ground Selection Transistor (GST), and the lower ends of the memory cells may be pipe-transferred to each other. The memory cells included in the string NS may be formed by being stacked on a plurality of semiconductor layers. Each string NS may include a first column PL11, a second column PL12, and a column connector PL13, the column connector PL13 being used to connect the first column PL11 to the second column PL 12. The first pillar PL11 may be connected to a bit line (e.g., BL1) and a pillar connection PL13, and may be formed by penetrating a region between the string select line SSL and the word lines WL5 to WL 8. The second pillar PL12 may be connected to the common source line CSL and the pillar connection PL13, and may be formed by penetratingly selecting a region between the line GSL and the word lines WL1 to WL 4. As shown in fig. 3B, the string NS may be implemented in a U-shaped column shape.

In one example embodiment, the back gate BG may be formed on the substrate, and the pillar connection PL13 may be implemented in the back gate BC. In one example embodiment, the back gates BG may commonly exist in the block BLKb. The Back Gate (BG) may be configured to be separated from the back gate of another block.

Fig. 4 is a block diagram further illustrating, in one example, an interface chip 110 according to an example embodiment of the inventive concepts. Referring to FIG. 4, the interface chip 110 may include a retraining checking circuit 111, a state decision logic 112, and a retraining circuit 114. In fig. 4, it is assumed that the interface chip 110 is suitable as an interface for a NAND flash memory device.

The retraining check circuit 111 may receive a read enable signal (RE/nRE), a data strobe signal (DQS/nqss), a write command, or a read command, and may be implemented to determine whether a retraining operation is required through unselected channels. That is, the retraining check circuit 111 may be activated using the read enable signal RE/nRE, the data strobe signal DQS/nDQS, the write command signal, or the read command signal. However, those skilled in the art will recognize that the retraining checking circuit 111 may be activated in other ways.

The state decision logic 112 may use at least one control signal (e.g., one or more of nCE [ n:1], nRE, ALE/CLE, nWE, DQS/nDQS) and/or a data signal (DQ [ k:1], where "n" and "k" are integers greater than 1) to generate at least one selection signal that determines an operating mode (e.g., a Receive (RX) mode or a Transmit (TX) mode) of the retraining circuitry 114.

The retraining circuit 114 may be implemented to select an operating mode in response to a selection signal output from the state decision logic 112 and to adjust the timing of the data signals DQ [ k:1] or the data strobe signal DQS/nDQS to be appropriate for the selected operating mode.

The retraining circuitry 114 may include at least one clock-based sampler and a delay-locked loop (DLL) circuit that generates a clock that is input to the sampler. Optionally, the retraining circuitry 114 may include at least one clock-based sampler and a delay unit that generates a clock that is input to the sampler. However, the retraining circuit 114 may be implemented differently to adjust signal timing.

In this regard, the retraining circuit 114 may be implemented to reduce training time by searching for a reference voltage using a self-training circuit. For example, the self-training circuit may reduce training time by simultaneously searching the NVM's respective reference voltages through different input and output pads (or pads) of NVM package 100.

The retraining circuitry 114 may include duty cycle correction circuitry to account for jitter caused by distortion of the duty cycle of the DQS from the NVM. In this regard, the retraining circuitry 114 may calibrate the drive strength of the NVM using a Z-Q calibration.

Referring to fig. 4, the connection relationship between pads of an exemplary layout may include the following. The data pads for the input and output data signals DQ [ k:1] may be connected to one of a first internal data pad for the input and output of the first internal data signal DQ1[ k:1] and a second internal data pad for the input and output of the second internal data signal DQ2[ k:1] through the retraining circuit 114. The data strobe pad may be connected to one of a first internal data strobe pad for inputting and outputting the first data strobe signal DQS 1/nqss 1 and a second internal data strobe pad for inputting and outputting the second data strobe signal DQS 2/nqss 2, through which the data strobe signal DQS/nqss is input and output.

The pad receiving the read enable signal RE/nRE from the controller 200 may be connected to a first read enable pad for outputting the first read enable signal RE1/nRE1 through an output Driver (DRV), and connected to a second internal read enable pad for outputting the second read enable signal RE2/nRE2 to the nonvolatile memory through the output driver.

The chip enable signal nCE [ n:1] may be received simultaneously in the interface chip 110 and the NVM by wire bonding (wire bonding).

The address latch enable/command latch enable pad may be connected through the state decision logic 112 to an internal address latch enable/command latch enable pad that outputs an address latch enable signal ALE/command latch enable signal CLE to the NVM, which may receive the address latch enable signal ALE/command latch enable signal CLE from the controller 200.

The write enable pad may be connected through state decision logic 112 to an internal write enable pad for outputting a write enable signal (nWE) to the NVM, which may receive the write enable signal nWE from the controller 200.

As shown in FIG. 4, the state decision logic 112 may send pass/fail information to the controller 200 using the DQ/DQS signal, and the state decision logic 112 may receive the read enable signal nrE.

The controller 200 may send a status read command to the status decision logic 112 using the data signal DQ or the write enable signal nWE. Further, the controller 200 may send a read enable signal nRE to the state decision logic 112. The retraining check circuit 111 may latch the status read data using the read enable signal nRE and may transmit the status read data to the controller 200 through the data signal DQ or the data strobe signal DQs.

The status read data may be divided into interface chip 110 status read data and NAND status read data.

The status read data may be selected as one of interface chip status read data and NAND status read data. The interface chip state read data in the example embodiment may include the determined result value of the retraining checking circuit 111.

Those skilled in the art will recognize that the connection relationships of the pads shown with respect to the interface chip 110 of fig. 4 are merely exemplary.

Fig. 5 is a block diagram further illustrating the interface chip 110 according to an embodiment of the inventive concept in one example.

Referring to fig. 5, the interface chip 110 may include at least one chip enable pad 116, a data pad 117, a first data pad 118, and a second data pad 119, the data pad 117 corresponding to a channel CH between the controller 200 and the interface chip 110, the first data pad 118 corresponding to a first internal channel ICH1, and the second data pad 119 corresponding to a second internal channel ICH 2. Here, for convenience of description, the first internal channel ICH1 is assumed to be an unselected channel, and the second internal channel ICH2 is assumed to be a selected channel.

The Retraining Checking Circuit (RCC)111 may be activated by receiving chip selection information from a chip enable signal decoder (nCE DEC)113 and at least one operation information from a selected channel ICH 2. The operation information may relate to a write operation (or a program operation), an erase operation, and/or a read operation.

The retraining check circuit 111 may send test data to the data pads 118 using a transmit path corresponding to the unselected channel (e.g., the first internal channel ICH1), may receive test data from the data pads 118 using a receive path corresponding to the unselected channel ICH1, and may determine whether retraining is required. The sensing portion of the retraining checking circuit 111 may be associated with the transmit path and the receive path of the unselected channel ICH 1.

The internal channel selector 115 may determine whether to connect the Channel (CH) to the first internal channel (ICH1) or the second internal channel ICH2 based on the chip selection information from the chip enable signal decoder 113.

The interface chip 110 may be used to check whether retraining for the unselected paths is required using the retraining check circuit 111 while the selected channel continues to be used to perform normal operations (e.g., read operations, write operations, and/or erase operations). Further, the interface chip 110 may be used to send information to the controller 200 regarding whether retraining is required, either by a status read operation or via a dedicated pin. Thus, the interface chip 110 may automatically respond to timing variations caused by variations in frequency, voltage, temperature, etc.

In a particular embodiment, the retraining check circuit 111 may be implemented as a built-in self-test (BIST) circuit or a DQS oscillator.

FIG. 6 is a block diagram illustrating the retraining check circuit 111 implemented with the BIST circuit 111a in one example. Referring to fig. 6, the retraining check circuit 111 may check pass/fail using a match between a DQ signal and a DQs signal output from the BIST circuit 111 a. For example, a flip-flop (DFF)111b may be used to latch the data signal DQ from the data strobe pad to the data pad in response to the data strobe signal DQS. The comparison logic 111c may receive the latched value from the flip-flop 111b and output a pass/fail signal (P/F) corresponding to the necessity of the retraining operation. After the DQ signal and the DQs signal generated in the BIST circuit 111a are transferred through the transmission path and the reception path, the retraining check circuit 111 may generate a pass/fail signal according to matching of the DQ signal and the DQs signal.

Fig. 7 is a block diagram illustrating a retraining check circuit 111 implemented with an oscillator 111d in one example. Referring to fig. 7, the count value DQS _ OSC _ CNT according to the input and output of the DQS signal may be output through an unselected channel with respect to the clock output from the oscillator 111 d. The retraining check circuit 111 may generate a pass/fail signal using the output count value DQS _ OSC _ CNT provided by the counter 111 e.

As described above, the retraining checking circuit 111 may be activated differently. For example, the retraining checking circuit 111 may be activated using the read enable signal nRE.

FIG. 8 is a block diagram illustrating one method of activating the Retraining Check Circuit (RCC)111 using DQ/DQS/nRE (or write/read command) signals. Referring to fig. 8, the chip enable signal decoder 111f may receive a chip enable signal nCE from the controller and output chip selection information. The activation signal generator EN GNRT 111-1 may receive chip selection information from the chip enable signal decoder 111f and may output the activation signal EN in response to the read enable signal nRE. The enable signal EN may be used to enable a Retraining Checking Circuit (RCC) 111. For example, when the chip selection information is unselected and the read enable signal nRE is at a high level, the enable signal generator 111-1 may output the enable signal EN to check whether retraining for the unselected channels is required.

Alternatively, the activation signal generator in example embodiments may also output the activation signal EN in response to a write command or a read command signal instead of the read enable signal nRE.

The retraining check circuit RCC shown in fig. 8 may be activated non-periodically in response to the read enable signal nRE. However, example embodiments of the retraining checking circuit RCC are not limited thereto.

FIG. 9 is a block diagram illustrating another method of activating the retraining check circuit RCC 111 using a write/read command (or DQ/DQS/nRE). Referring to fig. 9, the counter 111-2 may output the activation signal EN by counting a write command signal or a read command signal and comparing the count value with a reference value. The reference value may be stored in reference value storage 111-3. In an example embodiment, reference value storage 111-3 may be implemented as volatile memory or non-volatile memory. For example, when the write command signal or the read command signal is counted 1000 times, the retraining checking circuit may check whether retraining is required.

The retraining check circuit in an example embodiment may output the activation signal by counting the read enable signal nRE instead of counting the write command signal or the read command signal and comparing the count value with a reference value.

The retraining checking circuit RCC 111 may be implemented using an internal oscillator or using nRE/RE or DQS/nDQS.

Fig. 10 is a conceptual (ladder flow) diagram illustrating the execution of a retraining check operation in the storage device 10 of fig. 1.

Referring to fig. 1 and 10, the controller 200 may transmit a write request to the interface chip 110 (S11). The write request may include a write command, a write address, and write data. The interface chip 110 may transmit the write request received from the controller 200 to the selected NVM through the selected channel (S12). Thereafter, the selected NVM can perform a write operation corresponding to the write request (S13).

When the write operation is performed, the interface chip 110 may activate a Retraining Checking Circuit (RCC)111 (S14). Thereafter, the retraining check circuit 111 may transmit the expected data to the unselected NVM through the unselected channel (S15), and may receive the sampled data corresponding to the unselected NVM through the unselected channel (S16). The retraining check circuit 111 may determine whether retraining is required by comparing expected data with sampled data (S17). When retraining is required, the retraining check circuit 111 may send a retraining request to the controller 200 (S18).

Then, the selected NVM may complete the write operation and send completion information to the controller 200 (S19).

It is noted that the retrain check operation of FIG. 10 may be performed concurrently with the write operation.

Fig. 11 is another conceptual diagram illustrating the performance of a retraining checking operation in the storage device 10 of fig. 1.

Referring to fig. 1 and 11, the controller 200 may transmit a read request to the interface chip 110 (S21). The read request may include a read command and a read address. The interface chip 110 may transmit the read request received from the controller 200 to the selected NVM through the selected channel (S22). Thereafter, the selected NVM can perform a read operation corresponding to the read request (S23). Then, the NVM may send the read data to the controller 200 (S24).

When the read operation is performed, the interface chip 110 may activate a Retraining Checking Circuit (RCC)111 (S25). Thereafter, the retraining check circuit 111 may send expected data to the unselected NVM through the unselected channel (S26), and may receive corresponding sampled data from the unselected non-volatile memory device through the unselected channel (S27). The retraining check circuit 111 may determine whether retraining is required by comparing expected data with sampled data (S28). When retraining is required, the retraining check circuit 111 may send a retraining request to the controller 200 (S29).

It is noted that the retraining checking operation of FIG. 11 may be performed concurrently with the performance of the read operation.

FIG. 12 is a block diagram illustrating one method of sending a retrain request from the interface chip 110 to the controller 200. Referring to FIG. 12, a status read operation may be used to send a request for retraining. That is, the status read operation may be performed in response to a status read command provided by the controller 200. Alternatively, a state read operation may be performed in the NVM connected to the unselected channel in response to at least one operation signal related to a normal operation performed using the selected channel.

The interface chip 110 may send a result value obtained by performing OR (OR) calculation of a pass/fail result value provided by a Retraining Checking Circuit (RCC)111 and a state value provided by a state decision logic (e.g., a state determination logic) 112 to the controller 200 as state read information. In one example embodiment, the status read information may include at least one of status read information related to the interface chip and status read information related to the non-volatile memory. The controller 200 may issue a retrain command in response to status read information received from the interface chip 110 and may send the retrain command to the interface chip 110.

Fig. 13 is a block diagram illustrating another method of sending a retrain request from the interface chip 110 to the controller 200. Referring to fig. 13, the interface chip 110 may transmit a retrain request corresponding to an unselected channel to the controller 200 via a dedicated pin (EXP). The controller 200 may periodically receive a retrain request from the interface chip 110 through the dedicated pins. The retraining request may include a pass/fail result value of the Retraining Checking Circuit (RCC) 111. The controller 200 may send a retrain command to the interface chip 110 in response to a retrain request received over the pins EXP.

As described above, NVM package 100 of particular embodiments of the inventive concepts may include vertically stacked NVMs. One example of this variation is shown in the block diagram of fig. 14.

Referring to fig. 14, an NVM package (NVM PKG)100 includes an interface chip 110 (e.g., I/O buffer) and vertically stacked NVMs (e.g., NVM 1-NVM 8) 120. The first internal channel ICH1 may connect the first stacked NVMs (e.g., NVM 1-NVM 4) with the interface chip 110, respectively, and the second internal channel ICH2 may connect the second stacked NVMs (e.g., NVM 5-NVM 8) with the interface chip 110, respectively.

Interface chip 110 of fig. 14 is shown physically adjacent to the lowermost one of stacked NVMs 120 (e.g., NVM 1). However, the interface chip 110 may be disposed between the NVM of the first stack and the NVM of the second stack, or adjacent to the uppermost one of the NVMs of the stack (e.g., NVM 8).

The first internal channel ICH1 and the second internal channel ICH2 shown in fig. 14 may be implemented at least in part using wire channels (wire channels).

However, those skilled in the art will recognize that the foregoing examples are merely exemplary.

Fig. 15 is a block diagram illustrating a storage device 20 according to an embodiment of the inventive concept. Referring to FIG. 15, a memory device 20 may include a plurality of NVM memory packages (e.g., 100a-1 to 100a-i, where "i" is an integer greater than 1) and a controller 200a for differently controlling the NVM packages 100a-1 to 100 a-i.

Here, similar to the embodiment shown in fig. 1, the first NVM package 100a-1 may be connected to the memory controller 200a through a first internal channel CH 1. In a similar manner, each of the remaining NVM packages 100a-i may be connected to the controller 200a through a corresponding internal channel CHi.

As described with respect to the embodiments of fig. 1-14, each of the NVM packages 100a-1 through 100a-i can be implemented to include a retraining check circuit RCC 111. Retraining check circuits RCC 111 may be located in corresponding interface chips 111a-1 through 111a-i, respectively. Thus, each of the NVM packages 100a-1 to 100a-i can operate according to the method implemented by the retraining check circuit RCC 111 in its various embodiments.

In particular embodiments of the inventive concept, memory controller 200a may include a plurality of NVM managers 201-20 i, each operable to independently control a corresponding NVM package 100a-1 to 100a-i including a respective plurality of NVM120 a-1 to 120 a-i.

In this regard, separate circuits (as shown in fig. 15) may be used to implement NVM managers 201-20 i, respectively, or a single controller (or processor) 201 and associated software/firmware (as shown in fig. 16) may be used to implement the functionality of each NVM manager 201-20 i. For example, controller 200b in fig. 16 may include only one NVM manager 201.

In the embodiments variously illustrated in fig. 1 to 16, channel branching may be performed using the single-layer interface chip 110. However, the inventive concept is not limited thereto, and channel branching may be performed using a multi-layered interface chip.

Fig. 17 is a block diagram illustrating a storage device 40 according to an embodiment of the inventive concept. Referring to fig. 17, storage device 40 may include NVM package 100c and controller 200c configured to control NVM package 100 c.

NVM package 100c may include an interface circuit 110c and a plurality of NVMs connected via first to fourth internal channels ICH 1-ICH 4, respectively, the interface circuit 110c including multi-layer interface chips (e.g., FBI-1, FBI-2, and FBI-3).

The interface circuit 110c may include a first interface chip FBI-1 of a first layer and second and third interface chips FBI-2 and FBI-3 of a second layer. The first interface chip FBI-1 may branch the first channel CH1 into two branch channels DCH1 and DCH 2. The second interface chip FBI-2 and the third interface chip FBI-3 may be branched into two internal channels ICH1 to ICH2 and ICH3 to ICH4 corresponding to the branch channels DCH1 and DCH2, respectively.

In an example embodiment, the first, second and third interface chips FBI-1, FBI-2 and FBI-3 may be implemented in the same manner. In an example embodiment, each of the first, second and third interface chips FBI-1, FBI-2 and FBI-3 may include a circuit for checking whether a retrain operation is required and a retrain check circuit RCC for implementing the operation, which are described with reference to FIGS. 1 to 14.

The controller 200c may command a retrain operation for the corresponding lane in response to a retrain request received from at least one of the first, second, and third interface chips FBI-1, FBI-2, and FBI-3.

Fig. 18 is a flowchart outlining a method of operating an interface chip according to an embodiment of the inventive concept. Referring to fig. 1 and 18, the interface chip 110 may operate as follows. The interface chip 110 may determine whether a retrain operation is required using the unselected channel in the normal mode (S110). When the retraining operation is required, the interface chip 110 may send a retraining request to the controller 200 using a status reading operation or via a dedicated pin (S120).

In a particular embodiment, the interface chip 110 can send a write request or a read request to the corresponding NVM using the selected channel.

Here, the step of determining whether retraining is required may include: the retraining checking circuit is activated in response to a read enable signal, outputs expected data to the unselected channels, receives sampled data from the unselected channels, compares the expected data with the sampled data, and generates a retraining request according to the comparison result.

Optionally, the step of determining whether retraining is required may comprise: the DQS signals of the unselected channels are counted, the count value is compared to a reference value, and a retrain request is generated based on the comparison.

Here, the step of transmitting the retraining request to the controller may include: a state read value corresponding to the state read command and a retrain request corresponding to the determined result are ored and the calculated values are transmitted to the controller.

Optionally, the step of sending a retrain request to the controller may comprise: a retraining request corresponding to the determined result is sent to the controller through at least one dedicated pin.

Fig. 19 is another flowchart outlining a method of operating a controller according to an embodiment of the inventive concept. Referring to fig. 1 and 19, the controller 200 may operate as follows. The controller 200 may transmit an operation command to the interface chip (FBI chip) 110. The operation command may be a write command or a read command (S210). Thereafter, the controller 200 may receive a retrain request from the interface chip through a status read operation or via a dedicated pin (S220). The controller 200 may transmit a retrain command to the interface chip in response to the received retrain request (S230).

Fig. 20 is a block diagram illustrating a memory device 1000 according to an embodiment of the inventive concept. Referring to fig. 20, a memory device 1000 may include at least one NVM package (NVM PCKG)1100 and a memory controller 1200.

The non-volatile memory package 1100 may be implemented to perform the retraining checking operation and retraining operation described with reference to fig. 1-19 to improve data reliability. Further, the non-volatile memory package 1100 may include at least one Retrain Check Circuit (RCC) for determining whether retrain is required. In one example embodiment, the non-volatile memory device may be implemented to be optionally supplied with an external high voltage (Vpp).

The memory controller 1200 may be connected to a non-volatile memory package 1110. Memory controller 1200 may include at least one processor (CPU)1210, a buffer memory 1220, Error Correction Circuitry (ECC)1230, code memory 1240, a host interface 1250, and a non-volatile memory interface 1260.

The processor 1210 may be implemented to control overall operation. The processor 1210 may be implemented by a Central Processing Unit (CPU) or an Application Processor (AP).

The buffer memory 1220 may be implemented to temporarily store data required for the operation of the memory controller 1200. Although the buffer memory 1220 is illustrated in fig. 20 as being provided in the memory controller 1200, example embodiments of the buffer memory 1220 are not limited thereto. The buffer memory 1220 in the example embodiment may be provided outside the memory controller 1200 as a separate Intellectual Property (IP) block.

The error correction circuit 1230 may calculate an error correction code value of data to be programmed in the write operation, and may correct an error of the data read in the read operation based on the error correction code value, and may correct an error of the data recovered from the nonvolatile memory package 1100 in the data recovery operation. The error correction circuit 1230 may correct errors using code modulation such as Low Density Parity Check (LDPC) codes, BCH codes, turbo codes, reed-Solomon (reed-Solomon) codes, convolutional codes, Recursive Systematic Codes (RSC), Trellis Coded Modulation (TCM), Block Coded Modulation (BCM), and the like. The code memory 1240 may store code data required to operate the memory controller 1200. The code memory may be implemented as a non-volatile memory device.

The host interface 1250 may be implemented to provide a function of interfacing with an external device. The non-volatile memory interface 1260 may be implemented to provide functionality for interfacing with the non-volatile memory package 1100. Although not shown, the memory controller 1200 may include wireless communication functionality (e.g., Wi-Fi).

The memory device 1000 in the example embodiment may perform a retrain operation on unselected channels periodically or non-periodically while performing a normal operation through a selected channel, so that the performance of the system may be improved.

Fig. 21 is a block diagram illustrating a computing system 2000, according to an embodiment of the inventive concepts. Referring to fig. 21, a computing system 2000 may include at least one memory module (DIMM)2100, at least one non-volatile memory module (NVDIMM)2200, and at least one processor 2300. Each of the at least one memory module 2100 and the at least one non-volatile memory module 2200 may include a Retrain Check Circuit (RCC) that may perform the retrain check operations described above.

Example embodiments may be applicable to various types of computing systems (e.g., Central Processing Unit (CPU)/Graphics Processing Unit (GPU)/Neural Processor (NPU) platforms).

Fig. 22 is a block diagram illustrating a mobile device 3000 according to an embodiment of the inventive concept. Referring to fig. 22, the mobile device 3000 may include an application processor (AP, 3100), at least one buffer memory 3200, at least one storage device 3300, at least one sensor 3400, and a display/touch module 3500. For example, mobile device 3000 may be implemented by a laptop computer, a mobile phone, a smart phone, a tablet Personal Computer (PC), or a wearable computer.

The application processor (AP, 3100) may be implemented to control overall operation of the mobile device 3000. Application processor 3100 may execute applications that provide internet browsers, games, and videos. In one example embodiment, the application processor 3100 may include a single core or multiple cores. In an example embodiment, application processor 3100 may also include a cache memory disposed internal or external to application processor 3100. Further, the application processor 3100 may optionally include a controller, a Neural Processor (NPU), or the like.

In one example embodiment, application processor 3100 may be implemented as a system on a chip (SoC). A kernel of an operating system running on a system on a chip (SoC) may include input and output schedulers and a device driver for controlling the memory device 3300. The device driver may control access performance of the storage device 3300 by referring to the number of synchronization queues managed by the input and output schedulers, or may control a CPU mode, a DVFS level, and the like in the SoC.

Buffer memory 3200 may be implemented to store data required for the operation of application processor 3100. For example, the buffer memory 3200 may temporarily store an Operating System (OS) and application data, or may be used as an execution space of various software codes. In addition, buffer memory 3200 may store data related to artificial intelligence calculations. In one example embodiment, the buffer memory 3200 may be implemented as a DRAM or a PRAM.

Storage 3300 may be implemented to store user data. The storage device 3300 may be included in the mobile device 3000 in an embedded form. In another example embodiment, the storage device 3300 may be detachably included in the mobile device 3000.

The storage device 3300 may store data collected from at least one sensor, or may store network data, Augmented Reality (AR)/Virtual Reality (VR) data, and High Definition (HD) content. The storage 3300 may include a Solid State Drive (SSD), an embedded multimedia card (eMMC), and the like.

The at least one sensor 3400 may be implemented to perform various sensing operations.

The display/touch module 3500 may be implemented to output data or input data by touch. For example, the display/touch module 3500 may output sensed image data using at least one sensor, or may output calculated data using the application processor 3100. In addition, the display/touch module 3500 may recognize a touch of a user.

Fig. 23 is a block diagram illustrating an electronic system 4000 according to an embodiment of the inventive concept. Referring to fig. 23, an electronic system 4000 for a vehicle may include an Electronic Control Unit (ECU)4100, a memory device 4200, at least one dynamic range sensor (DVS)4300, a display device 4400, a communication processor (4500), and a safety ECU (not shown).

The ECU 4100 may be implemented to control the overall operation. The ECU 4100 may process image data received from the DVS 4300. The ECU 4100 may include a Neural Processor (NPU). The NPU can quickly derive an optimal image for driving by comparing the image received from the DVS 4300 with the learning model.

Memory device 4200 may be implemented to store learning models related to the operation of the NPU. Memory device 4200 may include volatile memory devices or non-volatile memory devices. For example, memory device 4200 may be implemented as DRAM, PRAM, NAND flash memory, or the like. Memory device 4200 in an example embodiment may be implemented to perform the retraining checking operations and retraining operations described with reference to fig. 1-19.

The DVS 4300 may be implemented to sense an external environment of the vehicle. The DVS 4300 may output an event signal in response to a change in the relative light intensity. The DVS 4300 may include a pixel array including a plurality of DVS pixels and an address event handler.

The display device 4400 may be implemented to display images processed by the ECU 4100 or transmitted by the communication processor 4500.

For example, the communication processor 4500 may be implemented to transmit a processed image to an external device (such as an external vehicle), or receive an image from an external vehicle. Accordingly, the communication processor 4500 may be implemented to communicate with an external device in a wired manner or a wireless manner.

Fig. 24 is a diagram illustrating a data center to which a memory device according to an embodiment of the inventive concept is applied. Referring to fig. 24, a data center 7000 may be implemented as a facility that can collect various data and can provide services, and may be referred to as a data storage center. Data center 7000 may be implemented as a system for operating search engines and databases, and may be implemented as a computing system used in a company, such as a bank or government organization. Data center 7000 may include application servers 7100 through 7100n and storage servers 7200 through 7200 m. In example embodiments, the number of application servers 7100-7100 n and the number of storage servers 7200-7200 m may vary, and the number of application servers 7100-7100 n may differ from the number of storage servers 7200-7200 m.

The application server 7100 or the storage server 7200 can include at least one of processors 7110 and 7210 and memory 7120 and 7220. Referring to storage server 7200 as an example, processor 7210 may control the overall operation of storage server 7200 and may access memory 7220 and may execute commands and/or data loaded in memory 7220. The memory 7220 may be implemented as double data rate synchronous dram (ddr sdram), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (nvmdimm). In an example embodiment, the number of processors 7210 and the number of memories 7220 included in storage server 7200 may be varied. In an example embodiment, the processor 7210 and the memory 7220 may provide a processor-memory pair. In an example embodiment, the number of processors 7210 may be different from the number of memories 7220. Processor 7210 may include a single core processor or a multi-core processor. The above description of storage server 7200 can be similarly applied to application server 7100. In an example embodiment, the application server 7100 may not include the storage device 7150. Storage server 7200 can include at least one or more storage devices 7250. In example embodiments, the number of storage devices 7250 included in storage server 7200 can vary.

Application servers 7100 through 7100n and storage servers 7200 through 7200m may communicate with each other via a network 7300. Network 7300 may be implemented using Fibre Channel (FC) or ethernet. In this case, the FC may be a medium for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. According to an access method of the network 7300, the storage servers 7200 to 7200m may be provided as a file storage device, a block storage device, or an object storage device.

In an example embodiment, the network 7300 may be implemented as a network dedicated to storage, such as a Storage Area Network (SAN). For example, a SAN may be implemented as a FC-SAN using a FC network and implemented according to a FC protocol (FCP). As another example, a SAN may be implemented as an IP-SAN using a TCP/IP network and implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In another example embodiment, the network 7300 may be implemented as a general purpose network (such as a TCP/IP network). For example, the network 7300 may be implemented according to protocols such as fc over ethernet (fcoe), Network Attached Storage (NAS), NVMe over network (NVMe-af), and the like.

In the following description, the application server 7100 and the storage server 7200 will be mainly described. The description of application server 7100 can apply to other application servers 7100n and the description of storage server 7200 can apply to other storage servers 7200 m.

The application server 7100 may store data requested by a user or a client to be stored in one of the storage servers 7200 to 7200m through the network 7300. In addition, the application server 7100 can acquire data, which a user or a client requests to read from one of the storage servers 7200 to 7200m, through the network 7300. For example, application server 7100 may be implemented as a web server or a database management system (DBMS).

The application server 7100 can access the memory 7120n or the storage device 7150n included in other application servers 7100n through the network 7300, or can access the memories 7220 to 7220m or the storage devices 7250 to 7250m included in the storage servers 7200 to 7200m through the network 7300. Accordingly, application server 7100 may perform various operations on data stored in application servers 7100 through 7100n and/or storage servers 7200 through 7200 m. For example, application server 7100 may execute commands to move data or copy data between application servers 7100 through 7100n and/or storage servers 7200 through 7200 m. In this case, data can be moved from the storage devices 7250 to 7250m of the storage servers 7200 to 7200m to the memories 7220 to 7220m of the storage servers 7200 to 7200m and the memories 7120 to 7120n of the application servers 7100 to 7100 n. Data moving through the network 7300 may be encrypted for security or privacy.

Referring to the storage server 7200 as an example, an interface (NIC)7254 may provide a physical connection between the processor 7210 and the controller 7251, as well as a physical connection between the NIC 7240 and the controller 7251. For example, the interface 7254 may be implemented by a Direct Attached Storage (DAS) method, which may directly connect the storage device 7250 using a dedicated cable. Also, for example, the interface 7254 may be implemented by various interface methods such as Advanced Technology Attachment (ATA), serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), serial attached SCSI (sas), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), universal flash memory (UFS), embedded universal flash memory (ewfs), and Compact Flash (CF) card interfaces. Similarly, application servers 7100 through 7100n may also include NICs 7140 through 7140n, respectively.

Storage server 7200 can also include switch 7230 and NIC 7240. The switch 7230 can selectively connect the processor 7210 to the storage device 7250 or can selectively connect the NIC 7240 to the storage device 7250 under the control of the processor 7210. Similar to storage server 7200, storage server 7200m may include a processor 7210m, memory 7220m, switch 7230m, NIC 7240m, and storage 7250 m. The memory device 7250m may include a DRAM 7253m, a controller 7251m, a NIC 7254m, and a NAND 7252 m.

In an example embodiment, NIC 7240 may comprise a network interface card, a network adapter, or the like. The NIC 7240 can be connected to the network 7300 by a wired interface, a wireless interface, a bluetooth interface, an optical interface, or the like. NIC 7240 may include internal memory, a DSP, a host bus interface, etc., and may be connected to processor 7210 and/or switch 7230 via the host bus interface. The host bus interface may be implemented as one of the examples of interface 7254 described above. In an example embodiment, NIC 7240 may be integrated with at least one of processor 7210, switch 7230, and storage 7250.

In the storage servers 7200 to 7200m or the application servers 7100 to 7100n, the processor may transmit a command to the storage devices 7130 to 7130n and 7250 to 7250m or the memories 7120 to 7120n and 7220 to 7220m, and may program or read data. In this case, the data may be error-corrected data in which an error has been corrected by an Error Correction Code (ECC) engine. The data may be data processed for Data Bus Inversion (DBI) or data Desensitised (DM) and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted data that is encrypted for security or privacy.

The memory devices 7150 to 7150n and 7250 to 7250m may transmit control signals and command/address signals to the NAND flash memory devices 7252 to 7252m in response to a read command received from the processor. Accordingly, when data is read from the NAND flash memory devices 7252 to 7252m, a Read Enable (RE) signal is input as a data output control signal, and the data may be output to the DQ bus. The data strobe (DQS) may be generated using the RE signal. The command and address signals may be latched into the page buffer according to a rising or falling edge of a Write Enable (WE) signal.

In an example embodiment, the storage devices 7150 through 7150n and 7250 through 7250m may be implemented by retraining operations of the storage devices and storage devices described with reference to fig. 1 through 19.

The controller 7251 may control the overall operation of the storage device 7250. In one example embodiment, the controller 7251 can include a Static Random Access Memory (SRAM). The controller 7251 can write data into the NAND flash memory device 7252 in response to a write command, or can read data from the NAND flash memory 7252 device in response to a read command. For example, write commands and/or read commands may be provided from processor 7210 in storage server 7200, processor 7210m in another storage server 7200m, or processors 7110 and 7110n in application servers 7100 and 7100 n. The DRAM 7253 may temporarily store (buffer) data to be written into the NAND flash memory device 7252 or data read from the NAND flash memory device 7252. In addition, DRAM 7253 may store metadata. The metadata may be user data or data generated by the controller 7251 for managing the NAND flash device 7252.

According to the above-described example embodiments, for a memory device and a retraining method of the memory device, the memory device may automatically cope with timing variations caused by frequency, voltage, or temperature by including an interface chip that may determine whether retraining is necessary using unselected channels and may transmit a retraining request to a controller according to the result of the determination.

Further, with the memory device and the retraining method of the memory device in the example embodiments, when the interface chip sends a retraining request to the controller, retraining may be performed without time/area limitation.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.