阅读说明：本技术 集成存储器组件的自适应折叠 (Adaptive folding of integrated memory components ) 是由 E.沙隆 A.巴扎斯基 I.阿尔罗德 于 2021-04-06 设计创作，主要内容包括：一种非易失性存储系统包含连接到集成存储器组件的存储器控制器。所述集成存储器组件包含包括非易失性存储器单元的存储器裸片和接合到所述存储器裸片的控制裸片。所述存储器控制器将数据提供到所述控制裸片以用于所述存储器裸片上的存储。数据最初作为每存储器单元单个位数据存储在所述存储器裸片上,以提升编程过程的性能。随后,所述控制裸片执行自适应折叠过程,所述自适应折叠过程包括从所述存储器裸片读取所述每存储器单元单个位数据、自适应地执行多个解码选项中的一个以及将所述数据作为每存储器单元多个位数据编程回到所述存储器裸片。(A non-volatile storage system includes a memory controller connected to an integrated memory component. The integrated memory component includes a memory die including non-volatile memory cells and a control die bonded to the memory die. The memory controller provides data to the control die for storage on the memory die. Data is initially stored on the memory die as a single bit of data per memory cell to improve performance of the programming process. Subsequently, the control die performs an adaptive folding process that includes reading the single bit of data per memory cell from the memory die, adaptively performing one of a plurality of decoding options, and programming the data back to the memory die as multiple bits of data per memory cell.)

1. An apparatus, comprising:

a first semiconductor die including a non-volatile memory cell and a first plurality of vias; and

a second semiconductor die comprising one or more control circuits, an interface to off-die circuitry, and a second plurality of lanes, the one or more control circuits configured to communicate signals through pairs of lanes of the first and second plurality of lanes, the one or more control circuits configured to:

reading a first set of data from the first semiconductor die as a single bit of data per memory cell;

determining, on the second semiconductor die, an error metric for the first set of data;

programming the first set of data to multiple bits of data per memory cell without decoding and re-encoding the first data if the error metric is less than a first threshold; and

in a case that the error metric is greater than the first threshold, decoding the first set of data on the second semiconductor die, re-encoding the decoded first set of data on the second semiconductor die, and programming the re-encoded first set of data to multiple bits of data per memory cell.

2. The apparatus of claim 1, wherein the one or more control circuits on the second semiconductor die are configured to transmit the first set of data to the off-die circuit by way of the interface to decode the first set of data at the off-die circuit if the error metric is greater than a second threshold, the second threshold being greater than the first threshold.

3. The apparatus of claim 2, further comprising:

a memory controller separate from the first semiconductor die and the second semiconductor die, the memory controller being the off-die circuitry, the memory controller connected by a communication channel to the second semiconductor die, the memory controller configured to decode codewords at a first resolution and a first power level, the one or more control circuits on the second semiconductor die configured to decode codewords at a second resolution lower than the first resolution and at a second power level lower than the first power level.

4. The apparatus of claim 1, wherein:

the one or more control circuits are further configured to read a second set of data from the first semiconductor die as a single bit of data per memory cell, and program the second set of data from the second semiconductor die with the first set of data as multiple bits of data per memory cell to a target set of non-volatile memory cells on the first semiconductor die such that a plurality of memory cells in the target set of non-volatile memory cells store data from both of the first set of data and the second set of data.

5. The apparatus of claim 1, wherein the one or more control circuits are further configured to:

reading a second set of data from the first semiconductor die as a single bit of data per memory cell;

reading a third set of data from the first semiconductor die as a single bit of data per memory cell; and

programming the second set of data and the third set of data from the second semiconductor die as multiple bits of data per memory cell with the first set of data to a target set of non-volatile memory cells on the first semiconductor die such that a plurality of memory cells in the target set of non-volatile memory cells store data from the first set of data, the second set of data, and the third set of data.

6. The apparatus of claim 1, wherein:

the error metric is a syndrome weight.

7. The apparatus of claim 1, wherein:

the one or more control circuits are configured to determine the error metric for the first set of data without decoding the first set of data.

8. The apparatus of claim 1, wherein:

the first semiconductor die is directly bonded to the second semiconductor die.

9. The apparatus of claim 1, further comprising:

a third semiconductor die comprising non-volatile memory cells, the one or more control circuits further configured to read a second set of data from the third semiconductor die as a single bit of data per memory cell, and program the second set of data from the second semiconductor die as multiple bits of data per memory cell with the first set of data to a set of target non-volatile memory cells on the first semiconductor die such that a plurality of memory cells in the target set of non-volatile memory cells store data from both the first set of data and the second set of data.

10. The apparatus of claim 1, further comprising:

a third semiconductor die comprising non-volatile memory cells, the one or more control circuits further configured to:

reading a second set of data from the first semiconductor die as a single bit of data per memory cell;

reading a third set of data from the first semiconductor die as a single bit of data per memory cell; and

programming the second set of data and the third set of data from the second semiconductor die as multiple bits of data per memory cell to a target set of non-volatile memory cells on the third semiconductor die such that a plurality of memory cells in the target set of non-volatile memory cells store data from the first set of data, the second set of data, and the third set of data.

11. The apparatus of claim 1, further comprising:

a third semiconductor die comprising a nonvolatile memory unit and a third plurality of vias; and

a fourth semiconductor die comprising a fourth plurality of lanes and an interface with the second semiconductor die, the fourth semiconductor die configured to transmit signals through lane pairs of the third and fourth plurality of lanes;

the second semiconductor die is configured to read a second set of data from the first semiconductor die as a single bit of data per memory cell and to transfer the second set of data to the fourth semiconductor die; and is

The fourth semiconductor die is configured to program the second set of data from the fourth semiconductor die as multiple bits of data per memory cell to a target set of non-volatile memory cells on the third semiconductor die.

12. The apparatus of claim 1, wherein:

the first semiconductor die includes a non-volatile memory array; and is

The second semiconductor die includes sense amplifiers for reading data from the non-volatile memory array on the first semiconductor die.

13. The apparatus of claim 12, wherein:

the non-volatile memory array includes word lines;

the second semiconductor die includes an address decoder for the non-volatile memory array on the first semiconductor die; and is

The second semiconductor die includes a signal generator configured to generate a voltage applied to the word line of the non-volatile memory array on the first semiconductor die.

14. The apparatus of claim 1, wherein:

the first set of data includes data bits and parity bits; and is

The one or more control circuits are configured to read the first set of data from the first semiconductor die by reading each data bit and parity bit by way of a different pair of lanes of the plurality of lanes.

15. A method, comprising:

reading a first set of data from a first set of non-volatile memory cells on a memory die bonded to a control die, the first set of data being stored in the first set of non-volatile memory cells as a single bit of data per memory cell;

reading a second set of data from a second set of non-volatile memory cells on the memory die, the second set of data being stored in the second set of non-volatile memory cells as a single bit of data per memory cell;

determining, on the control die, an error metric in the first set of data;

based on the determined error metric, selecting and performing between: performing the selecting on the control die without decoding the first set of data, performing decoding on the first set of data on the control die, or performing decoding on the first set of data at a memory controller, the memory controller being separate from the control die; and

programming the first and second sets of data as multiple bits of data per memory cell to a third set of non-volatile memory cells such that a plurality of memory cells in the third set of non-volatile memory cells store data from both of the first and second sets of data.

16. The method of claim 15, wherein:

the determining the error metric in the first set of data is performed without decoding the first set of data and includes determining a number of parity check equations that are not satisfied.

17. The method of claim 15, further comprising:

determining, on the control die, an error metric in the second set of data; and

on the control die, and independent of the selection of the first set of data, selecting between and, based on the determined error metric in the second set of data: not decoding the second set of data, performing decoding on the second set of data on the control die, or performing decoding on the second set of data at a memory controller.

18. An apparatus, comprising:

a memory controller; and

an integrated memory component in communication with the memory controller, the integrated memory component including a memory die including non-volatile memory cells and a control die bonded to the memory die;

the memory controller is configured to send a first request to the control die to program a first set of data to the memory die;

the memory controller is configured to send a second request to the control die to program a second set of data to the memory die;

the control die is configured to program the first set of data to the memory die as a single bit of data per memory cell in response to the first request;

the control die is configured to program the second set of data to the memory die as a single bit of data per memory cell in response to the second request;

the control die is further configured to:

reading the first set of data from the memory die as a single bit of data per memory cell;

reading the second set of data from the memory die as a single bit of data per memory cell;

determining syndrome weights for the first set of data;

in the event the syndrome weight is less than a first threshold, programming the first set of data to the memory die as multiple bits of data per memory cell with the second set of data such that the reading, determining the syndrome weight, and programming are performed without decoding and re-encoding the first set of data;

decoding the first set of data at the control die, re-encoding the decoded first set of data at the control die, and programming the re-encoded first set of data to the memory die as multiple bits of data per memory cell with the second set of data if the syndrome weight is greater than the first threshold and less than a second threshold; and

in the case where the syndrome weight is greater than the second threshold,

transmitting the first set of data from the control die to the memory controller,

decoding the first set of data at the memory controller,

receiving the first set of data from the memory controller after decoding at the memory controller, an

Programming the first set of data to the memory die as multiple bits of data per memory cell with the second set of data, the first threshold being less than the second threshold.

19. The apparatus of claim 18, wherein:

the memory controller is configured to decode at a first resolution and a first power level, the control die is configured to decode at a second resolution lower than the first resolution and at a second power level lower than the first power level.

20. The apparatus of claim 18, wherein:

the control die and the memory controller communicate by means of an interface including a data bus and control signals; and is

The control die is further configured to transmit the first set of data from the control die to the memory controller such that the first set of data can be decoded on the memory controller if the control die fails to successfully decode the first set of data.