阅读说明：本技术 用于顺序地存储的数据的经压缩逻辑到物理映射 (Compressed logical to physical mapping for sequentially stored data ) 是由 G·卡列洛 J·S·帕里 于 2021-04-29 设计创作，主要内容包括：本申请案是针对用于顺序地存储的数据的经压缩逻辑到物理映射。存储器装置可使用逻辑到物理映射表的分级集合以用于将由主机装置生成的逻辑块地址映射到所述存储器装置的物理地址。所述存储器装置可确定终端逻辑到物理映射表的所有条目是否为连续物理地址。响应于确定所有条目含有连续物理地址,存储器装置可将所述连续物理地址的开始物理地址连同旗标存储为较高层级表中的条目,所述旗标指示所述条目直接指向所述存储器装置中的数据而非指向终端逻辑到物理映射表。对于存储在所述连续物理地址中的一或多个中的数据的后续读取,所述存储器装置可略过终端表来读取所述数据。(The present application is directed to compressed logical-to-physical mapping of data for sequential storage. The memory device may use a hierarchical set of logical to physical mapping tables for mapping logical block addresses generated by the host device to physical addresses of the memory device. The memory device may determine whether all entries of the terminal logical to physical mapping table are consecutive physical addresses. In response to determining that all entries contain a consecutive physical address, the memory device may store a starting physical address of the consecutive physical address as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than to a terminal logical-to-physical mapping table. For subsequent reads of data stored in one or more of the consecutive physical addresses, the memory device may skip a termination table to read the data.)

1. An apparatus, comprising:

a memory array; and

a control component coupled with the memory array and configured to cause the apparatus to:

receiving a read command from a host device, the read command comprising a first logical block address associated with a location of at least a portion of data stored in the apparatus, wherein the data spans a plurality of consecutive physical addresses;

determining, based at least in part on the first logical block address, a memory location of a first plurality of entries mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses;

reading a first entry of the first plurality of entries based at least in part on the first logical block address, the first entry comprising a first physical address of the plurality of consecutive physical addresses and a first value of a flag;

reading at least the portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; and

transmitting the data to the host device.

2. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

determining the second physical address based at least in part on the first physical address and the first value of the flag and based at least in part on identifying an offset relative to the first physical address.

3. The apparatus of claim 1, wherein the first physical address corresponds to a starting page of a plurality of pages, the plurality of pages corresponding to the plurality of consecutive physical addresses.

4. The apparatus of claim 1, wherein the first physical address and the second physical address are the same physical address.

5. The apparatus of claim 1, wherein the control component is configured to cause the apparatus to determine the memory locations of the first plurality of entries by determining a third physical address indicating the locations of the first plurality of entries based at least in part on the first logical block address.

6. The apparatus of claim 5, wherein the third physical address indicates a location of a first page of a first type of memory of the apparatus and the plurality of consecutive physical addresses indicates locations of a plurality of pages of a second type of memory in the apparatus.

7. The apparatus of claim 6, wherein the first type of memory comprises SRAM of the apparatus and the second type of memory comprises NAND memory of the apparatus.

8. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

receiving a second read command from the host device comprising a second logical block address associated with second data stored in the apparatus;

determining the memory locations for mapping the first plurality of logical block addresses to the first plurality of entries of the corresponding first plurality of physical addresses based at least in part on the second logical block addresses, wherein the first plurality of logical block addresses includes the second logical block address;

reading a second entry of the first plurality of entries based at least in part on determining the memory location of the first plurality of entries and based on the second logical block address, the second entry comprising a second physical address and a second value of the flag, wherein the second physical address indicates a location of a second plurality of entries used to map a subset of the first plurality of logical block addresses, including the second logical block address, to a corresponding subset of the first plurality of physical addresses;

identifying a first entry of the second plurality of entries based at least in part on the second entry of the first plurality of entries, the first entry of the second plurality of entries including a fourth physical address indicating a location of the second data;

reading the second data from the fourth physical address based at least in part on identifying the first entry of the second plurality of entries; and

transmitting the second data to the host device.

9. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to:

receiving a plurality of write commands from the host device prior to receiving the read command, a first write command of the plurality of write commands comprising the first logical block address corresponding to the first physical address, wherein the plurality of write commands are associated with writing the data to the plurality of consecutive physical addresses; and

storing the data at the plurality of consecutive physical addresses based at least in part on receiving the plurality of write commands.

10. The apparatus of claim 9, wherein the control component is further configured to cause the apparatus to:

storing the first value of the flag and the first one of the plurality of consecutive physical addresses in the first one of the first plurality of entries based at least in part on writing the data to the plurality of consecutive physical addresses prior to receiving the read command.

11. The apparatus of claim 1, wherein the first value of the flag indicates that the first physical address comprises a location of the at least the portion of the data.

12. An apparatus, comprising:

a memory array; and

a control component coupled with the memory array and configured to cause the apparatus to:

receiving, from a host device, a plurality of write commands for writing data to the apparatus, the plurality of write commands comprising:

a first write command comprising a first logical block address corresponding to a first entry of a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and

a plurality of remaining write commands of the plurality of write commands each comprising a respective consecutive logical block address;

storing the data in the device at a plurality of consecutive physical addresses starting from a first physical address based at least in part on receiving the plurality of write commands;

determining whether a number of logical block addresses including the first logical block address and the respective logical block address matches the number of entries; and

storing a first value of the first physical address and flag in a first entry of a plurality of entries for mapping a plurality of logical block addresses including the number of logical block addresses to a corresponding plurality of physical block addresses including the plurality of consecutive physical addresses based at least in part on determining that the number of logical block addresses matches the number of entries.

13. The apparatus of claim 12, wherein the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address of the plurality of consecutive physical addresses.

14. The apparatus of claim 12, wherein the control component is further configured to cause the apparatus to:

for each write command of the plurality of write commands, storing a respective entry of a second plurality of entries including the number of entries, the second plurality of entries for mapping the number of logical block addresses to the plurality of consecutive physical addresses; and

discarding the second plurality of entries based at least in part on determining that the number of logical block addresses matches the number of entries.

15. The apparatus of claim 12, wherein the control component is further configured to cause the apparatus to:

receiving a read command from the host device including a third logical block address of the consecutive logical block addresses after storing the first physical address and the first value of the flag in the first entry;

reading the first entry of the plurality of entries to read the first physical address and the first value of the flag based at least in part on receiving the read command comprising the third logical block address;

identifying a second physical address of the plurality of consecutive physical addresses based at least in part on reading the first entry;

reading a second portion of the data from the second physical address based at least in part on identifying the second physical address; and

transmitting the second portion of the data to the host device.

16. The apparatus of claim 12, wherein the plurality of consecutive physical addresses are included in a first block of the apparatus, the apparatus further comprising:

receiving, from the host device, a second plurality of write commands for writing second data to the apparatus, the second plurality of write commands interleaved with the plurality of write commands and comprising:

a second write command comprising a third logical block address corresponding to the first entry of the second number of entries for mapping the second plurality of consecutive logical block addresses to the corresponding second plurality of physical addresses, and

a second plurality of remaining write commands of the second plurality of write commands each comprising a second respective consecutive logical block address;

identifying a second block different from the first block based at least in part on receiving the second plurality of write commands;

storing the second data in the device at a second plurality of consecutive physical addresses of the second block starting from a fourth physical address;

determining whether a second number of logical block addresses including the third logical block address and the second corresponding logical block address matches the second number of entries; and

storing the fourth physical address and the first value of the flag in a first entry of a second plurality of entries for mapping a second plurality of logical block addresses comprising the second number of logical block addresses to a corresponding second plurality of physical block addresses comprising the second plurality of consecutive physical addresses based at least in part on determining that the second number of logical block addresses matches the second number of entries.

17. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to:

receiving a read command from a host device, the read command comprising a first logical block address associated with a location of at least a portion of data stored in the electronic device, wherein the data spans a plurality of consecutive physical addresses;

determining, based at least in part on the first logical block address, a memory location of a first plurality of entries mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses;

reading a first entry of the first plurality of entries based at least in part on the first logical block address, the first entry comprising a first physical address of the plurality of consecutive physical addresses and a first value of a flag;

reading at least the portion of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and the first value of the flag; and

transmitting the data to the host device.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

determining the second physical address based at least in part on the first physical address and the first value of the flag and based at least in part on identifying an offset relative to the first physical address.

19. The non-transitory computer-readable medium of claim 17, wherein the first physical address corresponds to a starting page of a plurality of pages, the plurality of pages corresponding to the plurality of consecutive physical addresses.

20. The non-transitory computer-readable medium of claim 17, wherein the first physical address and the second physical address are the same physical address.

21. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, cause the electronic device to determine the memory location of the first plurality of entries by determining a third physical address indicative of the location of the first plurality of entries based at least in part on the first logical block address.

22. The non-transitory computer-readable medium of claim 21, wherein the third physical address indicates a location of a first page of a first type of memory of the electronic device and the plurality of consecutive physical addresses indicate locations of a plurality of pages of a second type of memory in the electronic device.

23. The non-transitory computer-readable medium of claim 22, wherein the first type of memory comprises SRAM of the electronic device and the second type of memory comprises NAND memory of the electronic device.

24. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving, from the host device, a second read command comprising a second logical block address associated with second data stored in the electronic device;

determining the memory locations for mapping the first plurality of logical block addresses to the first plurality of entries of the corresponding first plurality of physical addresses based at least in part on the second logical block addresses, wherein the first plurality of logical block addresses includes the second logical block address;

reading a second entry of the first plurality of entries based at least in part on determining the memory location of the first plurality of entries and based on the second logical block address, the second entry comprising a second physical address and a second value of the flag, wherein the second physical address indicates a location of a second plurality of entries used to map a subset of the first plurality of logical block addresses, including the second logical block address, to a corresponding subset of the first plurality of physical addresses;

identifying a first entry of the second plurality of entries based at least in part on the second entry of the first plurality of entries, the first entry of the second plurality of entries including a fourth physical address indicating a location of the second data;

reading the second data from the fourth physical address based at least in part on identifying the first entry of the second plurality of entries; and

transmitting the second data to the host device.

25. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to:

receiving a plurality of write commands from the host device prior to receiving the read command, a first write command of the plurality of write commands comprising the first logical block address corresponding to the first physical address, wherein the plurality of write commands are associated with writing the data to the plurality of consecutive physical addresses; and

storing the data at the plurality of consecutive physical addresses based at least in part on receiving the plurality of write commands.

Technical Field

The technical field relates to compressed logical-to-physical mapping of data for sequential storage.

Background

The following generally relates to one or more memory systems, and more particularly relates to compressed logical-to-physical mapping of data for sequential storage.

Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell can be programmed to one of two support states, often designated by a logic 1 or a logic 0. To access the stored information, the component may read or sense at least one stored state in the memory device. To store information, a component may write or program a state in a memory device.

There are various types of memory devices, including magnetic hard disks, Random Access Memories (RAMs), Read Only Memories (ROMs), dynamic RAMs (drams), synchronous dynamic RAMs (sdrams), ferroelectric RAMs (ferams), magnetic RAMs (mrams), resistive RAMs (rrams), flash memories, Phase Change Memories (PCMs), 3-dimensional cross point memories (3D xpoints), flash memories (such as floating gate flash devices and charge trapping flash devices, which may be used in NOR (NOR) or NAND (NAND) memory devices), and the like. The memory devices may be volatile or non-volatile. Non-volatile memory cells, such as flash memory cells, can maintain their stored logic state for long periods of time even in the absence of an external power source. Volatile memory cells (e.g., DRAM cells) can lose their stored state over time unless they are periodically refreshed by an external power source. Flash-based memory devices may have different performance compared to other non-volatile and volatile memory devices.

Disclosure of Invention

An apparatus is described. The apparatus may include a memory array and a control component coupled with the memory array and configured to cause the apparatus to: receiving a read command from a host device, the read command comprising a first logical block address associated with a location of at least a portion of data stored in a device, wherein the data spans a plurality of consecutive physical addresses; determining, based at least in part on the first logical block address, a memory location for a first plurality of entries mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses; reading a first entry of a first plurality of entries based at least in part on a first logical block address, the first entry comprising a first physical address of a plurality of consecutive physical addresses and a first value of a flag; reading at least part of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and a first value of the flag; and transmitting the data to the host device.

An apparatus is described. The apparatus may include a memory array and a control component coupled with the memory array and configured to cause the apparatus to: receiving, from a host device, a plurality of write commands for writing data to a device, the plurality of write commands comprising: a first write command comprising a first logical block address corresponding to a first entry of a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and a plurality of remaining write commands of the plurality of write commands each comprising a respective consecutive logical block address; storing data in the device at a plurality of consecutive physical addresses starting from the first physical address based at least in part on receiving the plurality of write commands; determining whether a number of logical block addresses including the first logical block address and the corresponding logical block address matches a number of entries; and storing the first physical address and a first value of the flag in a first entry of a plurality of entries for mapping a plurality of logical block addresses including the number of logical block addresses to a corresponding plurality of physical block addresses including a plurality of consecutive physical addresses based at least in part on determining that the number of logical block addresses matches the number of entries.

A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a read command from a host device, the read command comprising a first logical block address associated with a location of at least a portion of data stored in an electronic device, wherein the data spans a plurality of consecutive physical addresses; determining, based at least in part on the first logical block address, a memory location for a first plurality of entries mapping a first plurality of logical block addresses including the first logical block address to a corresponding first plurality of physical addresses; reading a first entry of a first plurality of entries based at least in part on a first logical block address, the first entry comprising a first physical address of a plurality of consecutive physical addresses and a first value of a flag; reading at least part of the data from a second physical address of the plurality of consecutive physical addresses based at least in part on the first physical address and a first value of the flag; and transmitting the data to the host device.

Drawings

FIG. 1 illustrates an example of a memory device supporting compressed logical-to-physical mapping of data for sequential storage in accordance with examples disclosed herein.

FIG. 2 illustrates an example of NAND circuitry supporting compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

FIG. 3 illustrates an example of a system that supports compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

FIG. 4 illustrates an example of an operational flow to support compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

FIG. 5 illustrates an example of an operational flow to support compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

FIG. 6 illustrates an example of a process to support compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

FIG. 7 shows a block diagram of a memory device that supports compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

Fig. 8 and 9 show flow diagrams illustrating one or more methods of supporting compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein.

Detailed Description

Memory devices, such as devices including flash memory, among other examples, can be coupled with a host device and can receive commands (e.g., read and write commands) from the host device for reading or writing data. Flash memory is typically organized into pages and blocks, where each block may contain multiple pages. Flash memory cells can be read and written at the page level, but can be erased at the block level. In some examples, flash memory cells may be rewritten without first erasing. Thus, when a flash memory device updates a page of data (e.g., in response to a command from a host device), the memory device can write new data to a different page and mark old pages as obsolete rather than erasing a block of memory and rewriting any valid pages in the block.

For write operations, a host device may refer to the location of data stored in a memory device using a Logical Block Address (LBA) to identify the logical (e.g., conceptual) location of a page of data. The LBAs may be mapped to physical addresses of the memory pages of the memory device at which the data is stored. Because the physical address of the data may change (e.g., when the data is updated by writing the updated data to a different page), some memory devices maintain one or more logical-to-physical (L2P) tables that map LBAs generated by the host device to corresponding physical addresses of pages in the memory device. In this way, the host device can request that data be read from the memory device using the same LBA as was used to write the data, even if the data has been moved to a different physical address. In some examples, the physical address may include an offset index that indicates a particular subset of the page. For example, if the memory device has a page size of 16kB, each page may be further partitioned into four 4kB page subsets that may be accessed based on the offset index of the physical address.

Memory devices having relatively large storage capacities may use a hierarchical L2P table architecture having multiple hierarchical tables to identify the location of a page of data to be read, such as a two-tier architecture or a three-tier architecture. In some examples, the memory device may step back to the location of the data page in flash memory using a multi-level L2P table. For example, a three-level L2P table architecture may include a relatively small first-level table that may include a list of physical addresses that point to locations of multiple second-level L2P tables. The second-level L2P table may include a list of physical addresses that point to locations of a plurality of third-level L2P tables. The third level L2P table may include a list of physical addresses that point to pages of data in flash memory; for example, it may be a terminal (e.g., last) table in the hierarchy. Thus, to access data in flash memory, a memory device can navigate through three levels to identify the location of a requested page of data. Such an approach may allow a relatively small first level L2P table to be stored in SRAM on a memory device for fast access and updates, but may increase read latency by introducing additional operations, such as two additional reads (e.g., for reading entries in the first level table and the second level table), to identify the physical address of the data.

The third level table may include a list of physical addresses that may be ordered by a corresponding LBA index. That is, the first entry in the third level table may include the physical address corresponding to LBA0, the second entry may include the physical address corresponding to LBA 1, and so on. The physical addresses may not be sequential in all cases. However, when host data is written to flash memory sequentially (e.g., data is written to sequential physical addresses), the physical addresses in the third level L2P table may also be sequential, similar to the corresponding LBAs. Such sequential writing may be faster than non-sequential writing and may occur, for example, when downloading or streaming data.

In some examples, the third level L2P table may contain between 512 bytes and a physical address of 4kB (depending on the architecture), thereby mapping between 2 and 16MB of user data in flash memory.

In some examples, if the data pages of the third-level table are stored sequentially (e.g., the physical addresses in the table are sequential), the data pages mapped by the third-level table may then be read based on the first physical address of the third-level table (e.g., the starting physical address corresponding to the first LBA of the table). For example, the memory device may calculate the physical address of any of the sequentially stored pages of data based on the first physical address, or may read multiple sequential pages of data starting from the first physical address. Such sequentially stored data may be instances of a data stream or referred to as a data stream.

As described herein, the starting physical address of sequentially stored data may be stored as an entry in the second-level L2P table (e.g., rather than storing a pointer to an entry of the third-level L2P table), and may point directly to the sequential data. In this example, the memory device may locate the data by traversing the first two levels of the L2P table without accessing the third level L2P table, thereby eliminating one of the L2P table reads and improving read latency, among other advantages.

In some examples, the second level L2P may include some entries that point to physical addresses of sequential user data (e.g., bypassing the need for the third level L2P table), as well as other entries that include pointers to the third level L2P table (e.g., for non-sequentially stored data). In some examples, it may be beneficial to provide an indication to the memory device as to which of these two types of entries is included in each of the second-level L2P entries to enable the memory device to accurately locate user data and skip through the third-level L2P table when possible.

In some examples, each entry (e.g., pointer) in the L2P table may occupy 4 bytes (for ease of computation) and may point to up to 16TB of flash memory (with a 4kB memory block). In memory devices with smaller capacity (e.g., up to 512GB), some bits in each entry are not available for L2P mapping. Any available bits of each entry may actually be used to store additional information, such as whether the physical address is valid. In some examples, one or more such available bits may be used to indicate to a memory device whether an L2P entry includes a pointer to a third level L2P table or a pointer to user data, among other examples.

The techniques described herein may provide several benefits. For example, random read performance may be improved by eliminating the terminal L2P table lookup by calculating the physical address of the data page in sequential data based on an offset from the first LBA starting with the physical address. Furthermore, the terminal L2P table update may be eliminated, resulting in more available space in the NAND flash memory (e.g., the third level L2P table may consume hundreds of MB) and less wear on the NAND memory cells for performing unnecessary operations.

To optimize read levels, the memory device may store temperature and time codes from when a programming operation (e.g., a write operation) occurs for each page or LBA in the NAND flash memory. By marking sequential data using indicators in the second-level L2P table, when an entire block (e.g., the entire terminal L2P table) is filled, the dedicated SRAM table may be compressed and skip the temperature and time stamp of each page in the block, since sequential writes are done atomically.

The features of the present disclosure are described initially in the context of the memory device and NAND circuit described with reference to fig. 1 and 2. As described with reference to fig. 3-6, features of the present disclosure are further described in the context of systems, processes, and flows for generating and using entries in an L2P table for sequentially stored data. These and other features of the present disclosure are further illustrated and described with reference to apparatus diagrams and flowcharts relating to compressed logical-to-physical mapping of sequentially stored data as described with reference to fig. 7-9.

FIG. 1 illustrates an example of a memory device 100 in accordance with examples disclosed herein. In some examples, memory device 100 may be referred to as (or may be included in) a managed memory device, a Universal Flash Storage (UFS) device, a solid state storage device, a memory chip, or an electronic device or apparatus. Memory device 100 may include one or more memory cells, such as memory cell 105-a and memory cell 105-b (other memory cells not labeled). Memory cell 105 may be, for example, a flash memory cell (such as depicted in the enlarged view of memory cell 105-a shown in fig. 1), a DRAM memory cell, a FeRAM memory cell, a PCM memory cell, or another type of memory cell.

Each memory cell 105 may be programmed to store a logical state representing one or more bits of information. Different memory cell architectures may store logic states in different ways. In a FeRAM architecture, for example, each memory cell 105 may include a capacitor including a ferroelectric material for storing a charge and/or polarization representing a programmable state. In a DRAM architecture, each memory cell 105 may include a capacitor that includes a dielectric material (e.g., an insulator) for storing a charge representing a programmable state. In a flash memory architecture, each memory cell 105 may include a transistor having a floating gate and/or a dielectric material for storing charge representing a logic state. For example, an enlarged view of memory cell 105-a is a flash memory cell including a transistor 110 (e.g., a Metal Oxide Semiconductor (MOS) transistor) that may be used to store a logic state. Transistor 110 has a control gate 115 and may include a floating gate 120 sandwiched between dielectric materials 125. The transistor 110 includes a first node 130 (e.g., source or drain) and a second node 135 (e.g., drain or source). A logic state may be stored in the transistor 110 by placing (e.g., writing, storing) a certain number of electrons (e.g., charges) on the floating gate 120. The amount of charge to be stored on floating gate 120 may depend on the logic state to be stored. The charge stored on floating gate 120 may affect the threshold voltage of transistor 110, thereby affecting the amount of current that may flow through transistor 110 when transistor 110 is activated. The logic state stored in the transistor 110 may be read by applying a voltage to the control gate 115 (e.g., at the control node 140) to activate the transistor 110 and measuring (e.g., detecting, sensing) the resulting amount of current flowing between the first node 130 and the second node 135.

For example, the sensing component 170 can determine the logic state stored on the flash memory cell based on the presence or absence of current from the memory cell or based on whether the current is above or below a threshold current. Similarly, a flash memory cell can be written by applying a voltage (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell to store (or not store) a charge on the floating gate that represents one of the possible logic states.

The charge trapping flash memory cell can operate in a similar manner to a floating gate flash memory cell, but instead of (or in addition to) storing charge on the floating gate 120, the charge trapping flash memory cell can store charge representing a state in the dielectric material under the control gate 115. Thus, a charge trapping flash memory cell may or may not include a floating gate 120.

In some examples, each row of memory cells 105 may be connected to a word line 160 and each column of memory cells 105 is connected to a digit line 165. Thus, one memory cell 105 may be located at the intersection of a word line 160 and a digit line 165. This intersection may be referred to as the address of the memory cell. The digit lines are sometimes referred to as bit lines. In some examples, word line 160 and digit line 165 can be substantially perpendicular to each other and can result in an array (e.g., in a memory array) of memory cells 105. In some examples, word line 160 and digit line 165 may be generally referred to as an access line or a select line.

In some examples, memory device 100 may include a three-dimensional (3D) memory array, with multiple two-dimensional (1D) memory arrays formed over one another. This may increase the number of memory cells that can be placed or created on a single die or substrate, which in turn may reduce manufacturing costs, or increase performance of the memory array, or both, as compared to a 1D array. In the example of FIG. 1, memory device 100 includes multiple levels of a memory array. In some examples, the levels may be separated by electrically insulating material. Each level may be aligned or positioned such that the memory cells 105 may be aligned (precisely, overlapping, or approximately) with each other on each level, forming a memory cell stack 175. In some examples, memory cell stack 175 may be referred to as a memory cell string, discussed in more detail with reference to fig. 3.

Access to memory cells 105 may be controlled by a row decoder 145 and a column decoder 150. For example, the row decoder 145 may receive a row address from a memory controller 155 (e.g., a control component) and activate the appropriate word line 160 based on the received row address. Similarly, column decoder 150 may receive a column address from memory controller 155 and activate the appropriate digit lines 165. Thus, by activating one word line 160 and one digit line 165, one memory cell 105 can be accessed.

After access, the memory cells 105 may be read or sensed by the sense component 170. For example, the sensing component 170 may be configured to determine a stored logic state of the memory cell 105 based on a signal generated by accessing the memory cell 105. The signal may comprise a voltage or a current or both, and the sensing component 170 may comprise a voltage sense amplifier, a current sense amplifier, or both. For example, a current or voltage may be applied to memory cell 105 (using the corresponding word line 160 and/or digit line 165), and the magnitude of the resulting current or voltage on digit line 165 may depend on the logic state stored by memory cell 105. For example, for a flash memory cell, the amount of charge stored on the floating gate or in the insulating layer of the transistor in memory cell 105 can affect the threshold voltage of the transistor, thereby affecting the amount of current flowing through the transistor in memory cell 105 when memory cell 105 is accessed. Such differences in current may be used to determine the logic state stored on memory cell 105.

The sensing component 170 may include various transistors or amplifiers in order to detect and amplify signals (e.g., current or voltage) on the digit line 165. The detected logic state of memory cell 105 may then be output via input/output block 180. In some examples, the sensing component 170 can be part of the column decoder 150 or the row decoder 145, or the sensing component 170 can be otherwise connected or in electronic communication with the column decoder 150 or the row decoder 145.

Memory cell 105 may be set or written by similarly activating the associated word line 160 and digit line 165 to enable a logical state (e.g., representing one or more bits of information) to be stored in memory cell 105. Column decoder 150 or row decoder 145 may accept data to be written to memory cells 105, for example, from input/output block 180. As previously discussed, in the case of flash memory, such as that used in NAND and 3D NAND memory devices, the memory cells 105 can be written by storing electrons in a floating gate or insulating layer.

The memory controller 155 may control the operation (e.g., read, write, re-write, refresh, etc.) of the memory cells 105 through various components such as the row decoder 145, the column decoder 150, and the sense component 170. In some examples, one or more of the row decoder 145, the column decoder 150, and the sensing component 170 may be co-located with the memory controller 155. Memory controller 155 may generate row and column address signals in order to activate desired word line 160 and digit line 165. Memory controller 155 may also generate and control various voltages or currents used during operation of memory device 100. In some examples, memory controller 155 or another component of memory device 100 may construct (e.g., build, generate, and/or maintain) one or more L2P tables for mapping LBAs (e.g., LBAs generated by a host device) to physical addresses in memory device 100 (e.g., addresses of physical pages in memory device 100 corresponding to LBAs). In some examples, memory device 100 may generate and/or maintain multiple levels of L2P tables, such as in a three-level L2P table architecture. In some examples, the memory device 100 may determine whether a terminal L2P table (e.g., a third-level L2P table) is populated (or is to be populated) with sequential physical addresses, such as when data is written to the memory device sequentially. In this case, the memory device 100 may store the first of the sequential physical addresses in an entry of a higher-level L2P table (e.g., a second-level L2P table), and may discard (or avoid generating) the terminal L2P table (e.g., a third-level L2P table). The memory device 100 may store an indication (e.g., a value of a flag) of whether the entry includes a pointer directly to sequential physical data in one or more entries of a higher-level L2P table (e.g., a second-level L2P table), thereby enabling the memory device 100 to skip a terminal L2P table (e.g., a third-level L2P table), or a pointer to a terminal L2P table.

Although the discussion herein focuses on a three-tier L2P table architecture, similar approaches may be used in other examples of multi-tier L2P table architectures, such as a two-tier L2P architecture, a four-tier L2P architecture, etc., where the terminating (e.g., last) L2P table may be eliminated (e.g., discarded, not generated, skipped) if the data pointed to by the table is stored sequentially.

Fig. 2 illustrates an example of a NAND circuit 200 supporting compressed logical-to-physical mapping of data for sequential storage in accordance with an example of the present disclosure. The NAND circuit 200 may be an example of a portion of a memory device, such as the memory device 100. Although some elements included in fig. 2 are labeled with a reference numeral and other corresponding elements are not labeled, they are the same or will be understood to be similar in order to increase the visibility and clarity of the depicted features.

NAND circuit 200 includes a plurality of flash memory cells 205 (which may be, for example, flash memory cells described with reference to figure 1) connected in a NAND configuration. In a NAND memory configuration, referred to as NAND memory, a plurality of flash memory cells 205 are connected in series with one another to form a string 210 of memory cells 205, with the drain of each flash memory cell 205 in the string 210 coupled with the source of another flash memory cell 205 in the string. In some examples, flash memory cells connected in a NAND configuration to form a NAND memory may be referred to as NAND memory cells.

Each string 210 of memory cells 205 may be associated with a corresponding digit line 215 (e.g., digit lines 215-a, 215-b) that is shared by the memory cells 205 in the string 210. Each memory cell 205 in the string 210 may be associated with a separate word line 230 (e.g., word lines 230-a, 230-i, 230-n), such that the number of word lines 230 may equal the number of memory cells 205 in the string 210.

The NAND memory may be organized hierarchically as strings 210 including a plurality of memory cells 205, pages 255 including one or more memory cells 205 connected to the same word line 230 (e.g., memory cells 205 from a plurality of strings 210), blocks 260 including one or more pages 255, planes including one or more blocks 260, and dies including one or more planes. In some examples, a die may include one plane, or may include two planes that may operate in parallel. The page of memory may be, for example, 4kB of memory, 8kB of memory, or another size.

NAND memory cells can be erased before they can be rewritten. In some examples, the NAND memory may be written and read (e.g., by activating the corresponding word line 230) at a page granularity level, but may not be erased at the page granularity level. In some examples, the NAND memory may actually be erased at a higher level of granularity (e.g., at a block granularity level). That is, page 255 may be the smallest unit that can be written, and block 260 may be the smallest unit that can be erased in some examples. Different memory devices may have different read/write/erase characteristics.

Each string 210 of memory cells 205 in the NAND circuit 200 is coupled with a drain side Select Gate Device (SGD) transistor 220 at one end of the string 210 and a source side select gate device (SGS) transistor 235 at the other end of the string 210. The SGD transistors 220 and the SGS transistors 235 may be used to couple the string 210 of memory cells 205 to the digit line 215 and/or source nodes 250 (e.g., source nodes 250-a, 250-b) by applying voltages at the gates 245 of the SGD transistors 220 and/or the gates 240 of the SGS transistors 235, respectively.

During a NAND memory operation, various voltage levels associated with the source node 250, the gate 240 of the SGS transistor 235 associated with the source node 250, the word line 230, the drain node 225, the gate 245 of the SGD transistor 220 associated with the drain node 225, and the digit line 215 may be applied to perform one or more operations (e.g., program, erase, or read) on at least some of the NAND memory cells in the string 210.

In some examples, during a read operation, a positive voltage may be applied to digit line 215 connected to drain node 225, while source node 250 may be connected to ground or virtual ground (e.g., approximately 0V). For example, the voltage applied to the drain node 225 may be 1V. At the same time, the voltage applied to the gates 245 and 240 may increase above the threshold voltage of the one or more SGS transistors 235 associated with the source node 250 and the one or more SGD transistors 220 associated with the drain node 225, such that the channel associated with the string 210 may be electrically connected to the drain node 225 and the source node 250. The channel may be an electrical path through the memory cells 205 in the string 210 (e.g., through transistors in the memory cells 205) that may conduct current under certain operating conditions.

Meanwhile, a plurality of word lines 230 (e.g., word lines 230-a, 230-i, 230-n, or in some examples, all word lines 230) other than the selected word line (i.e., the word line associated with the unselected cells in the string 210) may be connected to a voltage (e.g., VREAD) that is higher than the highest threshold Voltage (VT) of the memory cells in the string 210. VREAD may cause all unselected memory cells in the string 210 to be "on" so that each unselected memory cell may maintain high conductivity in the channel associated with it. In some examples, the word line 230 associated with the selected cell may be connected to a voltage Vtarget. Vtarget may be selected to be a value between the VT of erased memory cells and the VT of programmed memory cells in string 210. When a selected memory cell exhibits an erased VT (e.g., vtarget > VT of the selected memory cell), the selected memory cell 205 may be "on" in response to application of the vtarget and thus allow current to flow in the channel of the string 210 from the digit line 215 to the source 250. When the selected memory cell exhibits a programmed VT (e.g., so vtarget < VT of the selected memory cell), the selected memory cell may be "off" in response to vtarget, and thus inhibit current from flowing in the channel of the string 210 from the digit line 215 to the source 250. The amount of current (or lack thereof) may be sensed by the sensing component 170 as described with reference to FIG. 1 to read stored information in the selected memory cells 205 within the string 210.

Fig. 3 is an example of a system 300 that supports compressed logical-to-physical mapping of data for sequential storage in accordance with an example of the present disclosure. System 300 includes a host device 305 coupled with a memory device 310.

The memory device 310 may be an example of a memory device 100 as described with reference to FIG. 1, such as a managed memory device, a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage device (UFS) drives, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

The memory device 310 may include a memory device controller 315, which may be an example of the memory controller 155 described with reference to fig. 1, and one or more memory arrays 320 for storing data. The memory array 320 can include one or more NAND memory arrays, e.g., or data for reading and writing to the host device 305; such as other types of memory arrays for data provided by host device 305. The memory array 320 may include user data blocks 325 for storing user data.

Host device 305 may use memory device 310 to store data in one or more memory arrays 320 and to read data from one or more memory arrays 320. Host device 305 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., aircraft, drone, train, automobile, or other transport), internet of things (IoT) -enabled device, embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or networked business device), or such computing device including memory and processing devices. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, serial attached scsi (sas), and the like.

In some examples, memory device 310 may include, for example, SRAM330 in addition to memory array 320 or other types of memory that may be used by memory device 310 for internal storage or computation. In some examples, the SRAM330 may be included within or coupled with the memory device controller 315. In some examples, memory device 310 may store (e.g., write) a first level L2P table (e.g., a set of entries) in SRAM 330.

In some examples, the memory device 310 may include a system table block 335, which may be used, for example, to store information related to the state of blocks of the memory array 320. In some examples, the system table block 335 may be included within the memory array 320. The system table block 335 may include non-volatile memory, such as NAND memory, DRAM, ferroelectric memory, other types of memory, or any combination thereof. In some examples, the memory device 310 may store one or more second-level L2P tables and/or third-level L2P tables (or other levels of L2P tables, which may be referred to as sets of entries) in the system table block 335.

In some examples, the SRAM330 and the system table block 335 may be coupled to each other, and the SRAM330 and/or the system table block 335 may be coupled with the memory device controller 315.

In some examples, memory device 310 may maintain one or more sets of entries (e.g., L2P lookup tables) for mapping LBAs generated by host device 305 to physical addresses (e.g., page addresses) of memory array 320. Such sets of entries may be generated based on receiving one or more write commands from host device 305 that each include an LBA for writing data. In some examples, the L2P table may include a first-level L2P table having entries pointing to a second-level L2P table, which in turn may include entries pointing to a third-level (e.g., terminal) L2P table or directly to data stored sequentially in the memory array 320.

In some examples, the entries of the terminal L2P table may be ordered sequentially by LBA index. For example, a first entry in the terminal L2P table, for example, may include a first physical address corresponding to LBAN (thereby mapping LBA N to the first physical address), a second (consecutive) entry in the set of entries includes a second physical address corresponding to LBA N +1, a third entry includes a third physical address corresponding to LBA N +2, and so on. In some examples, if the entire terminal L2P table consists of sequential physical addresses (e.g., sequentially indexed LBAs corresponding to the table), the memory device controller 315 may store an entry in a higher-level L2P table that includes a first physical address (e.g., a first physical address corresponding to a first (LBA n) of the table) along with an indication that the entry points directly to data in the memory array 320 rather than to the terminal L2P table in the system table block 335.

Host device 305 includes a host controller interface 340. Host controller interface 340 may provide an interface for passing control, address, data, and other signals between host device 305 and memory device 310. Host device 305 can transmit memory access commands (e.g., read or write commands) to memory device 310 using host controller interface 340.

Memory device controller 315 may receive signals from host device 305 via host controller interface 340 and may cause memory device 310 to perform certain operations in response to receiving such signals. For example, memory device controller 315 may receive read or write commands from host device 305 and, in response, may cause memory device 310 to read or write data to memory array 320 based on the received commands.

In some examples, memory device controller 315 may access an entry in the first level L2P table in SRAM330 during a read operation based on the LBA received in the read command from host device 305. Entries in the first level L2P table may point to pages of system blocks 335 that include a second level L2P table associated with LBAs received in read commands. The memory device controller 315 may access an entry of the second level L2P table based on the LBA. The entries of the second-level L2P table may include pointers to physical addresses of the memory array 320 (e.g., for accessing data within sequentially stored data in the user data block 325) or pointers to a third-level (e.g., terminal) L2P table in the system table block 335. The entries of the second level L2P table may also include a value of a flag that indicates whether the entry points to data in the user data block 325 or to the third level L2P table in the system table block 335.

If an entry in the second level L2P table indicates that the entry points to sequential data in the user data block 325, the memory device controller 315 may read at least some, if not all, of the sequential data (e.g., one or more pages of data) in the user data block 325 based on the starting physical address and may transmit the data to the host device 305.

If an entry in the second-level L2P table indicates that the entry points to a third-level (terminal) L2P table in the system table block 335, the memory device controller 315 may read the entry of the third-level L2P table in the system table block 335 to identify the physical address of the data in the user data block 325. Memory device controller 315 can read data (e.g., a page of data) in user data block 325 based on the physical address and can transmit the data to host device 305.

Fig. 4 illustrates an operational flow 400 for reading data from a memory array using a hierarchical L2P table (e.g., L2P tables 405, 415, 430) that supports compressed logical-to-physical mapping of data for sequential storage, according to examples disclosed herein. In some examples, operational flow 400 may be performed by a memory device (e.g., memory device 310) in response to receiving a read command including or involving an LBA (e.g., based on receiving a read command from host device 305), for example, and may include or involve mapping the LBA to a physical address in user data block 425 of the memory device. Operational flow 400 may illustrate an example of a flow for reading data that skips over a terminal (e.g., third level) L2P table.

The operational flow 400 depicts the use of the system table block 410, which may be an example of the system table block 335 described with reference to fig. 3. A system table block 410 may be included in or coupled with an SRAM (e.g., SRAM 330) of a memory device. The system table block 410 may be organized into a plurality of dies (e.g., die 0 and die 1), each of which includes one or more planes (e.g., plane 0, plane 1). Each plane may include multiple pages (e.g., pages 0-9). In some examples, each square 440 (e.g., square 440-a) of system table block 410 may represent a page or a subset of pages. For example, if the page of the system table block 410 is 16kB, each square 440 (e.g., including square 440-a) may represent a 4kB subset of the page.

Operational flow 400 further depicts the use of user data block 425, which may be an example of user data block 325 described with reference to FIG. 3. User data block 425 may be included in a memory array (e.g., memory array 320) of a memory device. Similar to system table block 410, user data block 425 may be organized into a plurality of dies (e.g., die 0 and die 1), each of which includes one or more planes (e.g., plane 0, plane 1). Each plane may include multiple pages (e.g., pages 0-9). Each square 440 (e.g., including square 440-b) of user data block 425 may represent a page or a subset of pages.

In some examples, the first level L2P table 405 may be stored in the system table block 410. In response to receiving a read command that includes an LBA, the memory device may read (e.g., retrieve, lookup) an entry 405-a in the first level L2P table 405 based on the LBA. In some examples, entry 405-a may be associated with a group of LBAs that includes the LBA received in the read command. The entry 405-a may include the physical address of the page of the system table block 410 that contains (e.g., stores) the second level L2P table 415. In operational flow 400, for example, entry 405-a may include a physical address pointing to page 5 (or a subset of page 5) of plane 0 of die 0, which may contain a second level L2P table 415.

The memory device may then read the entry 415-a in the second level L2P table 415 based on the LBA. Entry 415-a may include a physical address of a page of user data block 425, the page corresponding to a first page of a plurality of pages of sequentially stored data. The plurality of pages of sequentially stored data may include a page of data requested by the host device; e.g., a page of data indicated by an LBA in the read command.

In the example of operational flow 400, entry 415-a may be a four byte entry including a physical address pointing to page 4 (or a subset of page 4) of plane 0 of die 1, where page 4 may be the first page of a plurality of pages including sequentially stored data. (the size of the entries of the L2P table may vary depending on the various characteristics of the memory device.)

In some examples, the entry 415-a may include a flag 420 that may be set to a first value indicating that the physical address in the entry 415-a points directly to a data page in the user data block 425, or may be set to a second value indicating that the physical address in the entry 415-a points to a third level L2P table in the system table block 410. In operational flow 400, the value of the flag may be the first value indicating that the physical address of entry 415-a points directly to a page of data in user data block 425. In some examples, the value of the flag 420 may occupy one or more bits in the entry 415-a, such as bits in the least significant byte (e.g., byte 3).

If the LBA included in the read command corresponds to a starting page 435 (e.g., first page, initial page) of sequentially stored data (e.g., pages pointed to by physical addresses in entries 415-a), the memory device can read the data from the starting page 435 and transmit the data to the host device.

If the LBAs included in the read command correspond to different pages of sequentially stored data (e.g., pages other than the starting page), the memory device may determine (e.g., calculate) a second physical address corresponding to the different pages, such as by applying an offset to the physical address of entry 415-a to determine the second physical address. The memory device may read data from a different page indicated by a second physical address based on determining (e.g., calculating) the second physical address corresponding to the different page. The memory device may transmit data to the host device.

Fig. 5 illustrates an operational flow 500 for reading data from a memory array using a hierarchical L2P table (e.g., L2P tables 405, 415, 430) that supports compressed logical-to-physical mapping of data for sequential storage, according to examples disclosed herein. In some examples, operational flow 500 may be performed by a memory device (e.g., memory device 310) based on receiving a read command (e.g., from host device 305) that includes an LBA, and may include mapping the LBA to a physical address in user data block 425 of the memory device. Operational flow 500 may be similar to operational flow 400, but may illustrate an example of a flow for reading data that does not skip an end (e.g., third level) L2P table.

In response to receiving a read command that includes a different LBA (e.g., a different LBA than the LBA described with reference to operational flow 400). In operational flow 500, different LBAs may be included within the group of LBAs associated with entry 405-a. Thus, the memory device may read the entry 405-a in the first level L2P table 405 based on a different LBA. As discussed with reference to operational flow 400, an entry 405-a may include the physical address of the page of the system table block 410 containing the second level L2P table 415. In various examples, the different LBAs may be within different groups of LBAs, and may thus be associated with different entries of the first level L2P table 405 that point to a second level L2P table that is different from the second level L2P table 415.

The memory device may read the entry 415-b in the second level L2P table 415 based on the LBA. The entry 415-b may be associated with a group of LBAs that include different LBAs, and may include the physical addresses of pages of the system table block 410 that contains a third level L2P table 430 for mapping the group of LBAs to physical addresses. In operational flow 500, for example, entry 415-b may include a physical address pointing to page 8 (or a subset of page 8) of plane 0 of die 1, which may contain third level L2P table 430.

In the example of operational flow 500, similar to entry 415-a of operational flow 400, entry 415-b may be a four byte entry including a flag 420 whose value indicates whether the physical address in entry 415-b points directly to a data page in user data block 425 or to a third level L2P table in system table block 410. In operational flow 500, the value of the flag may indicate that the physical address of entry 415-b points to the third level L2P table.

The memory device may be based on LBAs and based on value flags that indicate that physical addresses point to a third level L2P table in system table block 410; for example, the entry 430-a in the third level L2P table 430 is read based on the LBA and in response to determining that the value of the flag indicates that the physical address points to the third level L2P table. Entry 430-a may contain data requested by the host device; for example, the physical address of the page of user data block 425 of data associated with the LBA contained in the read command. The memory device may read the data at the page of user data block 425 pointed to by the physical address of entry 430-a and transmit the data to the host device.

Thus, the operational flow 500 may generate additional latency for reading data requested by the host device relative to the operational flow 400, as in the operational flow 500 the memory device may traverse (e.g., read entries from) all three levels of the L2P table, while in the operational flow 400 the memory device may skip over the terminal L2P table.

Fig. 6 illustrates an example of a flow 600 for building or updating a built-in L2P table that supports compressed logical to physical mappings for sequentially stored data in accordance with examples disclosed herein. Flow 600 may be used to build or update an intermediate L2P table (e.g., a second level L2P table) that may include entries pointing directly to sequentially stored data and other entries pointing to a terminal L2P table.

At 605, the memory device may initiate a process for building or updating one or more L2P tables in response to (e.g., based on) receiving a write command, for example, from a host device. The write command may include the LBA associated with writing data to the user data block of the memory device.

In response to receiving the write command, the memory device may determine whether a sequential data stream is open at 610. For example, the memory device may determine whether the LBA included in the write command received at 605 is sequential (has a sequential index, is contiguous) with the LBA included in a previous write command (e.g., the most recently received previous write command), or whether the physical address corresponding to the LBA included in the write command is contiguous with the physical address corresponding to the LBA of the previous write command, or whether other conditions or relationships exist, or any combination thereof.

In response to determining that the flow does not open, at 615, the memory device may determine whether the LBA included in the write command corresponds to the first LBA of the terminal L2P table (e.g., the third level L2P table). That is, where a subsequent write command causes the memory device to store data sequentially, the memory device may determine whether a new stream may be initialized.

In response to determining that the LBA included in the write command does not correspond to the first LBA of the terminal L2P table, at 620, the memory device may store (e.g., write, save) one or more physical addresses in the L2P table that point to the data written in response to receiving the write command, and may end the current process at 650. In some examples, the L2P table may be an end table (e.g., if step 620 is performed after determining not to open a flow at 610) or a higher-level table, such as a second-level table (e.g., if step 620 is performed after closing a flow at 635, as described below).

In response to determining that the LBA included in the write command does correspond to the first LBA of the terminal L2P table, at 625 the memory device may initialize the stream. For example, the memory device may store an indication that the stream associated with the L2P table has been opened or that data has been written at a physical address corresponding to the first entry of the terminal L2P table. In some examples, the memory device may hold an indication of the number of entries in the L2P table that correspond to pages that have been stored sequentially. In some examples, the memory device may store the physical address in a first entry of the terminal L2P table.

Returning to decision point 610, in response to determining that the flow is open (e.g., at least a first entry of the terminal L2P table has been written to the terminal L2P table or that data has been written to a user data block at a physical address corresponding to a first entry of the terminal table), at 630, the memory device may determine whether the flow continues (e.g., in relation to one or more previous processes or operations, such as an access operation). For example, the memory device can determine whether the LBA in the write command received at 605 is associated with storing data sequentially (e.g., at consecutive physical addresses) relative to data written in response to receiving a previous write command in the stream.

In response to determining that the flow does not continue, the memory device may close the flow at 635. For example, the memory device may update an indication that the flow associated with the L2P table is open to indicate that the flow is now closed. The memory device may proceed to 615 and perform other steps of flow 600 as previously discussed.

In response to determining that the flow continues, the memory device may update the flow at 640. For example, the memory device may update (e.g., increment) an indication of the number of entries in the L2P table corresponding to pages that have been sequentially stored.

At 645, the memory device may determine whether the terminal L2P table has been populated with sequentially stored physical addresses.

In response to determining that the terminal L2P table has not been populated with sequentially stored physical addresses, the memory device may end the current process at 650.

In response to determining that the terminal L2P table has been populated with sequentially stored physical addresses, the memory device may close the flow at 635, as previously described. In this case, the memory device may save the physical address of the first LBA of the end table in a higher level L2P table, such as a second level L2P table, at 620.

In some examples, when the flow is open, the memory device may continue to store entries (physical addresses) in the terminal L2P table each time the memory device stores data at sequential physical addresses, and may subsequently discard (e.g., erase, overwrite) the terminal L2P table if the memory device determines that the terminal L2P table has been filled with sequentially stored physical addresses.

Thus, flow 600 describes a process for building or maintaining an L2P table, which may enable a memory device to skip accessing (or maintaining) a terminal L2P table while sequentially storing data.

In some examples, the memory device may receive two or more interleaved streams of write commands, where each stream includes write commands that may include consecutive logical block addresses that may cause the memory device to write data of each stream to a corresponding set of consecutive physical addresses. In this example, the memory device may identify different blocks of memory at which to write data for each stream to enable multiple streams to be associated with corresponding entries in the second level L2P table. For example, a memory device may write a first stream of data (e.g., associated with a first stream of write commands) at contiguous physical addresses of a first block of memory, and may write a second stream of data (e.g., associated with a second stream of write commands) at contiguous physical addresses of a second block of memory (e.g., different from the first block of memory). The memory device may store the first entry in an L2P table containing the starting physical address of the first stream and may store the second entry in an L2P table containing the starting physical address of the second stream.

FIG. 7 shows a block diagram 700 of a memory device that supports compressed logical-to-physical mapping of sequentially stored data in accordance with examples disclosed herein. The memory device 705 may be an example of an aspect of a memory device as described with reference to fig. 1-5. Memory device 705 may include a command component 710, a location determination component 715, a data read component 720, a data transmit component 725, a data write component 730, and a table management component 735. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

Command component 710 can receive, at a memory device, a read command from a host device that includes a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses.

In some examples, command component 710 may receive, at a memory device, a set of write commands from a host device for writing data to the memory device, the set of write commands including: a first write command comprising a first logical block address corresponding to a first entry of the number of entries for mapping the set of consecutive logical block addresses to the corresponding set of physical addresses, and a set of remaining write commands of the set of write commands each comprising a respective consecutive logical block address.

In some examples, command component 710 may receive, at the memory device, a second read command from the host device that includes a second logical block address associated with second data stored in the memory device.

In some examples, command component 710 may receive a set of write commands from the host device prior to receiving the read command, a first write command of the set of write commands including a first logical block address corresponding to a first physical address, wherein the set of write commands is associated with writing data to a set of consecutive physical addresses.

In some examples, command component 710 may receive a read command including a third of the consecutive logical block addresses at the memory device from the host device after storing the first physical address and the first value of the flag in the first entry.

In some examples, command component 710 may receive, at the memory device, a second set of write commands from the host device for writing second data to the memory device, the second set of write commands interleaved with the set of write commands and including: a second write command including a third logical block address corresponding to the first entry of the second number of entries for mapping the second set of consecutive logical block addresses to the corresponding second set of physical addresses, and a second set of remaining write commands in the second set of write commands each including a second corresponding consecutive logical block address.

In some examples, the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address in the set of consecutive physical addresses.

Location determining component 715 may determine, based on the first logical block address, a memory location for mapping a first set of logical block addresses including the first logical block address to a first set of entries of a corresponding first set of physical addresses.

In some examples, the location determining component 715 may determine the second physical address based on the first physical address and a first value of a flag and based on identifying an offset from the first physical address.

In some examples, location determining component 715 may determine a third physical address indicating a location of the first set of entries based on the first logical block address.

In some examples, location determining component 715 may determine memory locations for mapping the first set of logical block addresses to the first set of entries of the corresponding first set of physical addresses based on a second logical block address, wherein the first set of logical block addresses includes the second logical block address.

In some examples, the location determining component 715 may identify a second block different from the first block based on receiving the second set of write commands.

In some examples, the third physical address indicates a location of a first page of the first type of memory of the memory device, and the set of consecutive physical addresses indicates a location of a set of pages of the second type of memory in the memory device.

In some examples, the first type of memory includes SRAM of the memory device and the second type of memory includes NAND memory of the memory device.

The data reading component 720 may read at least a portion of the data from a second physical address of the set of consecutive physical addresses based on the first physical address and a first value of the flag.

In some examples, the data reading component 720 may read the second data from the fourth physical address based on identifying the first entry in the second set of entries.

In some examples, the data reading component 720 may read the second portion of the data from the second physical address based on identifying the second physical address.

The data transmission component 725 may transmit data to a host device.

In some examples, the data transmission component 725 may transmit the second data to the host device.

In some examples, the data transmission component 725 may transmit the second portion of the data to the host device.

The data write component 730 may store data in the memory device at a set of consecutive physical addresses starting from the first physical address based on receiving the set of write commands.

In some examples, the data write component 730 may store data at a set of consecutive physical addresses based on receiving a set of write commands.

In some examples, the data write component 730 may store the second data in the memory device at a second set of consecutive physical addresses of a second block starting from the fourth physical address.

Table management component 735 may read a first entry in a first set of entries based on the first logical block address, the first entry including a first physical address in the set of consecutive physical addresses and a first value of the flag.

In some examples, table management component 735 may determine whether a number of logical block addresses including the first logical block address and the respective logical block address matches a number of entries.

In some examples, table management component 735 may store a first value of a first physical address and flag in a first entry of a set of entries for mapping a set of logical block addresses including a number of logical block addresses to a corresponding set of physical block addresses including a set of consecutive physical addresses based on determining that the number of logical block addresses matches the number of entries.

In some examples, table management component 735 may read a second entry in the first set of entries based on determining a memory location of the first set of entries and based on the second logical block address, the second entry including a second physical address and a second value of the flag, wherein the second physical address indicates a location for mapping a subset of the first set of logical block addresses including the second logical block address to a second set of entries of a corresponding subset of the first set of physical addresses.

In some examples, the table management component 735 may identify a first entry in the second set of entries based on a second entry in the first set of entries, the first entry in the second set of entries including a fourth physical address indicating a location of the second data.

In some examples, the table management component 735 may store the first value of the flag and the first physical address of the set of consecutive physical addresses in a first entry of the first set of entries based on writing data to the set of consecutive physical addresses prior to receiving the read command.

In some examples, table management component 735 may store, for each write command of the set of write commands, a respective entry of a second set of entries including a number of entries, the second set of entries used to map a number of logical block addresses to a set of contiguous physical addresses.

In some examples, table management component 735 may discard the second set of entries based on determining that the number of logical block addresses matches the number of entries.

In some examples, table management component 735 may read a first entry of the set of entries to read a first physical address and a first value of the flag based on receiving a read command that includes a third logical block address.

In some examples, table management component 735 may identify a second physical address in the set of consecutive physical addresses based on reading the first entry.

In some examples, table management component 735 may determine whether a second number of logical block addresses including a third logical block address and a second corresponding logical block address matches a second number of entries.

In some examples, table management component 735 may store the first value of the fourth physical address and the flag in the first entry in the second set of entries for mapping the second set of logical block addresses including the second number of logical block addresses to the corresponding second set of physical block addresses including the second set of consecutive physical addresses based on determining that the second number of logical block addresses matches the second number of entries.

In some examples, the first physical address corresponds to a starting page in a set of pages, the set of pages corresponding to a set of consecutive physical addresses.

In some examples, the first physical address and the second physical address are the same physical address.

In some examples, a first value of the flag indicates a location where the first physical address includes at least a portion of the data.

Fig. 8 shows a flow diagram illustrating one or more methods 800 that support compressed logical-to-physical mapping of sequentially stored data, in accordance with aspects of the present disclosure. The operations of method 800 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 800 may be performed by a memory device as described with reference to fig. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 805, the memory device can receive, at the memory device, a read command from a host device that includes a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses. The operations of 805 may be performed according to methods described herein. In some examples, aspects of the operations of 805 may be performed by a command component as described with reference to fig. 7.

At 810, the memory device may determine, based on the first logical block address, a memory location for mapping a first set of logical block addresses including the first logical block address to a first set of entries of a corresponding first set of physical addresses. The operations of 810 may be performed according to methods described herein. In some examples, aspects of the operations of 810 may be performed by a position determination component as described with reference to fig. 7.

At 815, the memory device may read a first entry in a first set of entries based on the first logical block address, the first entry including a first physical address in a set of consecutive physical addresses and a first value of the flag. The operations of 815 may be performed according to methods described herein. In some examples, aspects of the operations of 815 may be performed by a table management component as described with reference to fig. 7.

At 820, the memory device may read at least a portion of data from a second physical address of the set of consecutive physical addresses based on the first physical address and a first value of the flag. The operations of 820 may be performed according to methods described herein. In some examples, aspects of the operations of 820 may be performed by a data reading component as described with reference to fig. 7.

At 825, the memory device may transmit data to the host device. The operations of 825 may be performed according to methods described herein. In some examples, aspects of the operations of 825 may be performed by a data transmission component as described with reference to fig. 7.

In some examples, an apparatus as described herein may perform one or more methods, such as method 800. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device, a read command from a host device, the read command including a first logical block address associated with a location of at least a portion of data stored in the memory device, wherein the data spans a set of consecutive physical addresses; determining, based on the first logical block address, a memory location for mapping a first set of logical block addresses including the first logical block address to a first set of entries of a corresponding first set of physical addresses; reading a first entry in a first set of entries based on a first logical block address, the first entry including a first physical address in the first set of consecutive physical addresses and a first value of a flag; reading at least part of the data from a second physical address of the set of consecutive physical addresses based on the first physical address and a first value of the flag; and transmitting the data to the host device.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: the second physical address is determined based on the first physical address and a first value of a flag and based on identifying an offset from the first physical address.

In some examples of the method 800 and apparatus described herein, the first physical address corresponds to a starting page of a set of pages, the set of pages corresponding to a set of consecutive physical addresses.

In some examples of the method 800 and the apparatus described herein, the first physical address and the second physical address may be the same physical address.

In some examples of the method 800 and apparatus described herein, determining memory locations of the first set of entries may include operations, features, means, or instructions for: a third physical address indicating a location of the first set of entries is determined based on the first logical block address.

In some examples of the method 800 and apparatus described herein, the third physical address indicates a location of a first page of the first type of memory of the memory device, and the set of consecutive physical addresses indicates a location of a set of pages of the second type of memory in the memory device.

In some examples of the method 800 and apparatus described herein, the first type of memory comprises SRAM of the memory device and the second type of memory comprises NAND memory of the memory device.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: receiving, at the memory device from the host device, a second read command including a second logical block address associated with second data stored in the memory device; determining, based on a second logical block address, a memory location for mapping the first set of logical block addresses to a first set of entries of a corresponding first set of physical addresses, wherein the first set of logical block addresses includes the second logical block address; reading a second entry in the first set of entries based on determining a memory location of the first set of entries and based on a second logical block address, the second entry including a second physical address and a second value of the flag, wherein the second physical address indicates a location for mapping a subset of the first set of logical block addresses including the second logical block address to a second set of entries of a corresponding subset of the first set of physical addresses; identifying a first entry in the second set of entries based on a second entry in the first set of entries, the first entry in the second set of entries including a fourth physical address indicating a location of the second data; reading second data from the fourth physical address based on identifying the first entry in the second set of entries; and transmitting the second data to the host device.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: receiving a set of write commands from a host device prior to receiving the read command, a first write command of the set of write commands including a first logical block address corresponding to a first physical address, wherein the set of write commands may be associated with writing data to and storing data at a set of consecutive physical addresses based on receiving the set of write commands.

Some examples of the method 800 and apparatus described herein may further include operations, features, means, or instructions for: storing, prior to receiving the read command, a first value of a flag of a first entry in a first set of entries and a first physical address in the set of consecutive physical addresses based on writing data to the set of consecutive physical addresses.

In some examples of the method 800 and the apparatus described herein, the first value of the flag indicates a location where the first physical address includes at least a portion of the data.

Fig. 9 shows a flow diagram illustrating one or more methods 900 to support compressed logical-to-physical mapping of sequentially stored data in accordance with aspects of the present disclosure. The operations of method 900 may be implemented by a memory device or components thereof as described herein. For example, the operations of method 900 may be performed by a memory device as described with reference to fig. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, the memory device may perform aspects of the described functions using dedicated hardware.

At 905, the memory device can receive, at the memory device, a set of write commands for writing data to the memory device from a host device, the set of write commands including. The operations of 905 may be performed according to methods described herein. In some examples, aspects of the operations of 905 may be performed by a command component as described with reference to fig. 7.

At 910, the memory device may store data in the memory device at a set of consecutive physical addresses starting from the first physical address based on receiving the set of write commands. The operations of 910 may be performed according to methods described herein. In some examples, aspects of the operations of 910 may be performed by a data write component as described with reference to fig. 7.

At 915, the memory device may determine whether a number of logical block addresses including the first logical block address and the respective logical block address matches a number of entries. The operations of 915 may be performed according to methods described herein. In some examples, aspects of the operations of 915 may be performed by a table management component as described with reference to fig. 7.

At 920, the memory device may store a first value of a first physical address and a flag in a first entry of a set of entries for mapping a set of logical block addresses including a number of logical block addresses to a corresponding set of physical block addresses including a set of consecutive physical addresses based on determining that the number of logical block addresses matches the number of entries. The operations of 920 may be performed according to methods described herein. In some examples, aspects of the operations of 920 may be performed by a table management component as described with reference to fig. 7.

In some examples, an apparatus as described herein may perform one or more methods, such as method 900. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving, at a memory device from a host device, a set of write commands for writing data to the memory device, the set of write commands including: a first write command comprising a first logical block address corresponding to a first entry of a number of entries for mapping a plurality of consecutive logical block addresses to a corresponding plurality of physical addresses, and a plurality of remaining write commands of the plurality of write commands each comprising a respective consecutive logical block address; storing data in the memory device at a set of consecutive physical addresses starting from the first physical address based on receiving the set of write commands; determining whether a number of logical block addresses comprising the first logical block address and the corresponding logical block address matches a number of entries; and storing a first value of the first physical address and flag in a first entry of a set of entries for mapping a set of logical block addresses including a number of logical block addresses to a corresponding set of physical block addresses including a set of consecutive physical addresses based on determining that the number of logical block addresses matches the number of entries.

In some examples of method 900 and devices described herein, the first logical block address corresponds to the first physical address, and each of the respective consecutive logical block addresses corresponds to a respective consecutive physical address in the set of consecutive physical addresses.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: for each write command of the set of write commands, storing a respective entry of a second set of entries containing a number of entries, the second set of entries for mapping a number of logical block addresses to a set of contiguous physical addresses; and discarding the second set of entries based on determining that the number of logical block addresses matches the number of entries.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: receiving a read command at the memory device from the host device after storing the first physical address and the first value of the flag in the first entry, the read command including a third of the consecutive logical block addresses; reading a first entry of the set of entries to read a first physical address and a first value of a flag based on receiving a read command including a third logical block address; identifying a second physical address in the set of consecutive physical addresses based on reading the first entry; reading a second portion of the data from the second physical address based on identifying the second physical address; and transmitting the second portion of the data to the host device.

Some examples of the method 900 and apparatus described herein may further include operations, features, means, or instructions for: receiving, at the memory device from the host device, a second set of write commands for writing second data to the memory device, the second set of write commands being interleaved with the set of write commands and including: a second write command comprising a third logical block address corresponding to the first entry of the second number of entries for mapping the second plurality of consecutive logical block addresses to the corresponding second plurality of physical addresses, and a second plurality of remaining write commands of the second plurality of write commands each comprising a second corresponding consecutive logical block address; identifying a second block different from the first block based on receiving a second set of write commands; storing the second data in the memory device at a second set of consecutive physical addresses of the second block starting from the fourth physical address; determining whether a second number of logical block addresses including a third logical block address and a second corresponding logical block address matches a second number of entries; and storing the first value of the fourth physical address and flag in the first entry in a second set of entries for mapping a second set of logical block addresses including the second number of logical block addresses to corresponding second sets of physical block addresses including a second set of consecutive physical addresses based on determining that the second number of logical block addresses matches the second number of entries.

It should be noted that the methods described herein are possible embodiments, and that the operations and steps may be rearranged or modified, and that other embodiments are possible. Further, portions from two or more methods may be combined.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, those skilled in the art will appreciate that the signals may represent a signal bus, where the bus may have a variety of bit widths.

Devices including memory arrays discussed herein may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some examples, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate may be controlled by doping using various chemistries including, but not limited to, phosphorous, boron, or arsenic. The doping may be performed during the initial formation or growth of the substrate, by ion implantation or by any other doping method.

The switching components or transistors discussed herein may represent Field Effect Transistors (FETs) and include three terminal devices including a source, a drain and a gate. The terminals may be connected to other electronic components through conductive materials such as metals. The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), the FET may be referred to as a p-type FET. The channel may be terminated by an insulated gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. A transistor may be "on" or "activated" when a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate. A transistor may be "off" or "deactivated" when a voltage less than the threshold voltage of the transistor is applied to the transistor gate.

Example configurations are described herein in connection with the description set forth in the figures and are not intended to represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," and is not "preferred" or "superior to" other examples. The detailed description contains specific details that provide an understanding of the described technology. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

In the drawings, similar components or features may have the same reference numerals. In addition, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description may apply to any one of the similar components having the same first reference label but not the second reference label.

Information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and embodiments are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features that perform a function may also be physically located at various positions, including being distributed such that portions of the function are performed at different physical locations. Further, as used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that a list of at least one of, for example, A, B or C means a or B or C or AB or AC or BC or ABC (i.e., a and B and C). Further, as used herein, the phrase "based on" should not be construed as referring to a closed condition set. For example, exemplary steps described as "based on condition a" may be based on both condition a and condition B without departing from the scope of the present disclosure. In other words, the phrase "based on" as used herein should likewise be construed as the phrase "based at least in part on".

Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium may be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, a non-transitory computer-readable medium may comprise RAM, ROM, electrically erasable programmable read-only memory (EEPROM), Compact Disc (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that may be used to carry or store desired program code means in the form of instructions or data structures and that may be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Further, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes CD, laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.