阅读说明：本技术 一种板级封装的方法 (Board level packaging method ) 是由 邓榕秀 梁万里 于 2021-10-13 设计创作，主要内容包括：本发明涉及一种板级封装的方法,步骤1,准备一个可剥离的第一载体；步骤2,准备一个可剥离的第二载体；步骤3,在第一载体的第一导电金属层,贴一层感光膜,通过图形、电镀的方式,在第一载体形成至少两个孤立的焊盘；步骤4,在第一载体的一个焊盘上进行至少一个芯片的贴装、焊接；步骤5,在第二载体的第二导电金属层的表面生成至少两个连接体,用于焊接,其中至少一个连接体的高度,与芯片的厚度匹配；步骤6,用一张压合片,在对应芯片和焊盘的位置开窗；步骤7,在第一载体的芯片及另外焊盘上分别涂抹焊料；步骤8,将第一载体的芯片及焊盘套上压合片,相对于第二载体的连接体,通过压合片压合在一起、再经过焊接后形成封装体。(The invention relates to a method for packaging board level, step 1, prepare a strippable first carrier; step 2, preparing a second peelable carrier; step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode; step 4, carrying out mounting and welding of at least one chip on one bonding pad of the first carrier; step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip; step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad; step 7, respectively coating solder on the chip of the first carrier and the other bonding pads; and 8, sleeving the chip and the bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to the connector of the second carrier, and welding to form the packaging body.)

1. A method of board level packaging, comprising the steps of:

step 1, preparing a first strippable carrier;

the first carrier comprises a first carrier plate, a first conductive metal layer and a first bonding layer, wherein the first bonding layer is used for temporarily bonding the first conductive metal layer and the first carrier plate together;

step 2, preparing a second peelable carrier;

the second carrier comprises a second carrier plate, a second conductive metal layer and a second adhesive layer, and the second adhesive layer is used for temporarily adhering the second conductive metal layer and the second carrier plate together;

step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode;

step 4, coating solder on a corresponding position on a pad of the first carrier, and carrying out surface mounting and welding on at least one chip;

step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip;

step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad;

step 7, respectively coating solder on the chip of the first carrier and the other bonding pads;

step 8, sleeving a chip and a bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to a connector of the second carrier, and welding to form a packaging body;

step 9, stripping the second carrier from the packaging body, only keeping the connector and the second conductive metal layer on the packaging body, carrying out pattern processing on the second conductive metal layer, and etching off redundant metal to realize interconnection of chip electrodes;

step 10, carrying out secondary plastic package on the whole device, protecting the interconnected graphs and using the protected graphs as a reinforcing layer of the whole structure;

step 11, stripping the first carrier from the packaging body, and carrying out patterning and etching processing on the first conductive metal layer to form an external bonding pad of the device;

and step 12, performing chemical tin surface treatment on the surface of the external bonding pad to finish the whole board-level packaging process.

2. The method of board level packaging according to claim 1, wherein: the first carrier plate and the second carrier plate are made of any one of organic materials, metal steel plates, aluminum plates or FR4 plates.

3. The method of board level packaging according to claim 1, wherein: the first conductive metal layer and the second conductive metal layer have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer and the second conductive metal layer are made of copper.

4. The method of board level packaging according to claim 1, wherein: the first adhesive layer and the second adhesive layer are materials which can be pyrolyzed, photolyzed or directly peeled off mechanically.

5. The method of board level packaging according to claim 1, wherein: the laminating sheet is any one of a prepreg or a plastic-packaging material sheet.

6. The method of board level packaging according to claim 1, wherein: the solder is any one of tin paste, conductive adhesive or silver paste.

7. The method of board level packaging according to claim 6, wherein: the solder has good conductivity and bonding capability.

8. The method of board level packaging according to claim 1, wherein: and 7, the thickness of the coating solder is more than at least 20 μm, so that the solder has a buffer effect and makes up height errors between the bonding pad and the chip and between the connector and the bonding pad caused by process capability.

9. The method for board level packaging according to claim 1, wherein the method for forming the connector in step 5 comprises:

step 511, attaching a layer of photosensitive film on the surface of the second conductive metal layer of the second carrier, and forming at least two isolated pads on the second carrier by means of patterning and electroplating;

step 512, a layer of photosensitive film is attached to the surface of the second conductive metal layer of the second carrier, and at least one pad on the second carrier is heightened through a pattern and electroplating mode, wherein the heightened height of the pad is equal to the thickness of the chip.

10. The method for board level packaging according to claim 1, wherein the method for forming the connector in step 5 comprises: at least two copper strips with different heights are welded on the surface of the second conductive metal layer of the second carrier, and the height difference of the copper strips is equal to the thickness of the chip.

Technical Field

The invention relates to the technical field of chip board level packaging, in particular to a board level packaging method.

Background

In the existing panel level packaging process flow, the following defects exist in the lead-out mode of the chip electrode:

(1) for the laser drilling blind hole and the copper deposition electroplating mode, the main problems are high cost (laser drilling equipment is more expensive), high requirement on a chip bonding pad (common materials cannot tolerate laser and are easy to damage) and large limitation.

(2) The Bump (value ball) process mode mainly has the problems that firstly, the cost is high when a chip is used for manufacturing the Bump, and the mounting difficulty is high after the chip is used for manufacturing the Bump; the chip and the bonding pad to be interconnected with the chip are required to have the same height, and the process is difficult to realize;

(3) in the Cu Clip (copper sheet) process mode, firstly, a separate manufacturing tool is needed for manufacturing the Clip, the cost is high, the tolerance of the process on the height difference between a chip and a bonding pad is poor, and when the height difference between the chip and the bonding pad is large, the process cannot process;

(4) in addition to the above problems, the existing board level packaging process is affected by the interconnection mode, and the problems of poor heat dissipation and large internal resistance are also significant, which seriously affects the performance index of the device.

In order to overcome the existing problems, a board level packaging method is invented.

Disclosure of Invention

The invention aims to solve the problems that the existing lead-out mode of a chip electrode has high cost, high requirements on a chip bonding pad and large limitation in a laser blind hole drilling and copper deposition electroplating mode, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pad cannot be processed when the height difference is large. The concrete solution is as follows:

a method for board level packaging is carried out according to the following steps:

step 1, preparing a first strippable carrier;

the first carrier comprises a first carrier plate, a first conductive metal layer and a first bonding layer, wherein the first bonding layer is used for temporarily bonding the first conductive metal layer and the first carrier plate together;

step 2, preparing a second peelable carrier;

the second carrier comprises a second carrier plate, a second conductive metal layer and a second adhesive layer, and the second adhesive layer is used for temporarily adhering the second conductive metal layer and the second carrier plate together;

step 3, pasting a layer of photosensitive film on the first conductive metal layer of the first carrier, and forming at least two isolated bonding pads on the first carrier in a pattern and electroplating mode;

step 4, coating solder on a corresponding position on a pad of the first carrier, and carrying out surface mounting and welding on at least one chip;

step 5, generating at least two connectors on the surface of the second conductive metal layer of the second carrier for welding, wherein the height of at least one connector is matched with the thickness of the chip;

step 6, a laminating sheet is used for windowing at the position corresponding to the chip and the bonding pad;

step 7, respectively coating solder on the chip of the first carrier and the other bonding pads;

step 8, sleeving a chip and a bonding pad of the first carrier with a pressing sheet, pressing the pressing sheet together relative to a connector of the second carrier, and welding to form a packaging body;

step 9, stripping the second carrier from the packaging body, only keeping the connector and the second conductive metal layer on the packaging body, carrying out pattern processing on the second conductive metal layer, and etching off redundant metal to realize interconnection of chip electrodes;

step 10, carrying out secondary plastic package on the whole device, protecting the interconnected graphs and using the protected graphs as a reinforcing layer of the whole structure;

step 11, stripping the first carrier from the packaging body, and carrying out patterning and etching processing on the first conductive metal layer to form an external bonding pad of the device;

and step 12, performing chemical tin surface treatment on the surface of the external bonding pad to finish the whole board-level packaging process.

Further, the first carrier plate and the second carrier plate are made of any one of organic materials, metal steel plates, aluminum plates or FR4 plates.

Furthermore, the first conductive metal layer and the second conductive metal layer have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer and the second conductive metal layer are made of copper.

Further, the first adhesive layer and the second adhesive layer are materials which can be pyrolyzed, photolyzed or directly mechanically peeled.

Further, the laminating sheet is any one of a prepreg or a plastic-packaging material sheet.

Further, the solder is any one of tin paste, conductive adhesive or silver paste.

Further, the solder has good conductivity and bonding ability.

Further, the thickness of the coating solder in the step 7 is larger than at least 20 μm, so that the solder has a buffer effect and makes up height errors between the bonding pad and the chip and between the connector and the bonding pad caused by process capability.

Alternative 1:

the method for forming the connecting body in the step 5 comprises the following steps:

step 511, attaching a layer of photosensitive film on the surface of the second conductive metal layer of the second carrier, and forming at least two isolated pads on the second carrier by means of patterning and electroplating;

step 512, a layer of photosensitive film is attached to the surface of the second conductive metal layer of the second carrier, and at least one pad on the second carrier is heightened through a pattern and electroplating mode, wherein the heightened height of the pad is equal to the thickness of the chip.

Alternative 2:

the method for forming the connecting body in the step 5 comprises the following steps: at least two copper strips with different heights are welded on the surface of the second conductive metal layer of the second carrier, and the height difference of the copper strips is equal to the thickness of the chip.

In summary, the technical scheme of the invention has the following beneficial effects:

the invention solves the problems that the existing lead-out mode of the chip electrode has high cost of laser drilling blind holes and copper deposition electroplating, high requirements on chip bonding pads and large limitations, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pads cannot be processed when the height difference is large. The invention has the following advantages:

1. compared with a method for leading out an electrode by laser drilling, the method has the advantages of high processing efficiency, no need of expensive equipment and low requirement on the property of a bonding pad of a chip.

2. The scheme of the invention solves the problems of high processing cost and large chip mounting difficulty of the Bump process.

3. The scheme of the invention has no requirement on the height difference between the chip and the bonding pad needing interconnection, and can be compatible with larger height difference.

4. According to the scheme, the electrodes are interconnected through the copper bar or the thickened electroplating pad, the copper bar or the thickened electroplating pad is welded above the chip, the heat dissipation capacity of the device is greatly improved, the cross section area of the copper bar or the thickened electroplating pad is large, the conductivity is good, and the internal resistance value of the device can be reduced to the maximum extent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.

FIG. 1 is a diagram of a first carrier of a method of board level packaging according to the present invention;

FIG. 2 is a diagram of a second carrier of the method of board level packaging of the present invention;

FIG. 3 is a diagram of a first carrier plated pad configuration of a method of board level packaging according to the present invention;

FIG. 4 is a block diagram of a first carrier mounted chip of a method of board level packaging of the present invention;

FIG. 5 is a structural view of a second carrier plating pad of embodiment 1;

FIG. 6 is a diagram of a lamination sheet of a method of board level packaging according to the present invention;

FIG. 7 is a schematic view of a pressing apparatus for a method of board level packaging according to the present invention;

FIG. 8 is a diagram of a laminated package structure according to a method of board level packaging of the present invention;

fig. 9 is a structural diagram of an external bonding pad of a device formed by secondary plastic packaging and processing after the first carrier and the second carrier are peeled off from the package body;

FIG. 10 is a structural view of a second carrier solder copper bar of example 2;

FIG. 11 is a structural view of a three pin package of embodiment 3;

FIG. 12 is a cross-sectional view taken along line B-B of FIG. 11;

FIG. 13 is a cross-sectional view taken along line A-A of FIG. 11;

fig. 14 is a top structural view of a chip of embodiment 3.

Description of reference numerals:

10-a first carrier, 11-a first carrier, 12-a first conductive metal layer, 13-a first adhesive layer, 14-a pad, 15-solder, 20-a second carrier, 21-a second carrier, 22-a second conductive metal layer, 23-a second adhesive layer, 24-a thickened electroplated pad, 25-a copper strip, 30-a chip, 31-a pin, 40-a laminated sheet, 41-a window, 50-a reinforcing layer, 100-a package body, 101-an external pad.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1:

as shown in fig. 1 to 9: a method for board level packaging is carried out according to the following steps:

step 1, preparing a first peelable carrier 10;

the first carrier 10 comprises a first carrier 11 with better rigidity, a first conductive metal layer 12 and a first adhesive layer 13, wherein the first adhesive layer 13 is used for temporarily adhering the first conductive metal layer 12 and the first carrier 11 together;

step 2, preparing a second peelable carrier 20;

the second carrier 20 comprises a second carrier 21 with better rigidity, a second conductive metal layer 22 and a second adhesive layer 23, wherein the second adhesive layer 23 is used for temporarily adhering the second conductive metal layer 22 and the second carrier 21 together;

step 3, pasting a layer of photosensitive film on the first conductive metal layer 12 of the first carrier 10, and forming at least two isolated pads 14 (namely electroplating pads) on the first carrier 10 in a pattern and electroplating manner;

step 4, coating solder 15 on a corresponding position on a pad of the first carrier 10, and carrying out surface mounting and welding on at least one chip 30;

step 5, generating at least two connectors on the surface of the second conductive metal layer 22 of the second carrier 20 for soldering, wherein the height of at least one connector (i.e. the longer connector) matches with the thickness of the chip 30; (Note: the difference in height between the longer and shorter connectors is equal to the thickness of the chip 30)

Optionally, the method for forming the connecting body comprises:

step 511, pasting a photosensitive film on the surface of the second conductive metal layer 22 of the second carrier 20, and forming at least two isolated pads 14 on the second carrier 20 by means of patterning and electroplating;

step 512, a photosensitive film is further attached to the surface of the second conductive metal layer 22 of the second carrier 20, and at least one bonding pad 14 on the second carrier 20 is heightened through a pattern and electroplating manner to become a thickened electroplating bonding pad 24, wherein the heightened height of the bonding pad (i.e., the thickened electroplating bonding pad 24) is equal to the thickness of the chip 30.

Step 6, a laminating sheet 40 is used for windowing 41 (such as rectangular windowing) at the position corresponding to the chip 30 and the bonding pad 14;

step 7, respectively coating solder 15 on the chip 30 and the additional bonding pad 14 of the first carrier 10;

step 8, sleeving the chip 30 and the bonding pad 14 of the first carrier 10 on a pressing sheet 40, pressing the pressing sheet 40 together relative to the connector of the second carrier 20, and welding to form a packaging body 100; the lamination process of the lamination sheet 40 is to perform a plastic package.

Step 9, stripping the second carrier 20 from the package body 100, only keeping the connector and the second conductive metal layer 22 on the package body 100, performing pattern processing on the second conductive metal layer 22, and etching away excess metal to realize interconnection of the electrodes of the chip 30;

step 10, performing secondary plastic package on the whole device (namely the package 100), protecting the interconnected patterns, and using the protected patterns as a reinforcing layer 50 of the whole structure;

step 11, stripping the first carrier 10 from the package body 100, and performing patterning and etching processing on the first conductive metal layer 12 to form an external pad 101 of the device;

and step 12, performing chemical tin surface treatment on the surface of the external bonding pad 101 to complete the whole board-level packaging process.

Specifically, the first carrier plate 11 and the second carrier plate 21 are made of any one of an organic material, a metal steel plate, an aluminum plate, or an FR4 plate.

Specifically, the first conductive metal layer 12 and the second conductive metal layer 22 have good conductivity and can be removed by chemical etching or grinding, and the first conductive metal layer 12 and the second conductive metal layer 22 are preferably copper (other metals may be used instead according to actual situations). The first adhesive layer 13 and the second adhesive layer 23 are materials that can be pyrolyzed, photolyzed, or directly mechanically peeled off. The laminate 40 is any one of a prepreg and a sheet of plastic molding. The solder 15 is any of a solder paste, a conductive paste, or a silver paste. The solder 15 has good conductivity and adhesion ability.

Specifically, the thickness of the applied solder 15 in step 7 is greater than at least 20 μm, so that the solder 15 has a buffer effect to compensate for the height error between the pad (including the pad 14, the thickened plated pad 24, and the copper bar 25 in example 2) and the chip 30, and the longer connector (the thickened plated pad 24 or the tall copper bar 25 in example 2) and the pad 14 due to the process capability.

Example 2:

as shown in fig. 10, unlike example 1, the method for forming the linker in step 5 is: at least two copper strips 25 with different heights are welded on the surface of the second conductive metal layer 22 of the second carrier 20, and the height difference of the copper strips 25 is equal to the thickness of the chip 30. The rest of the contents are completely the same as embodiment 1, and are not described again here.

Example 3:

as shown in fig. 11 to 14, different from embodiment 1, the chip 30 in embodiment 1 has one upper pin and one lower pin, the chip 30 in embodiment 3 has one bottom pin and two top pins 31, accordingly, three pads 14 are provided on the first carrier 10, four connectors (for example, four pads 14 and two thickened plating pads 24 are provided) are provided on the second carrier 20, and accordingly, three external pads 101 are provided on the lower portion of the package 100 as the pins of the device. The rest of the description is identical to (or similar in principle to) embodiment 1, and will not be described herein again.

In summary, the technical scheme of the invention has the following beneficial effects:

the invention solves the problems that the existing lead-out mode of the chip electrode has high cost of laser drilling blind holes and copper deposition electroplating, high requirements on chip bonding pads and large limitations, a Bump process mode has high cost and large mounting difficulty, a Cu Clip process mode has high cost, and the chip and the bonding pads cannot be processed when the height difference is large. The invention has the following advantages:

1. compared with a method for leading out an electrode by laser drilling, the method has the advantages of high processing efficiency, no need of expensive equipment and low requirement on the property of a bonding pad of a chip.

2. The scheme of the invention solves the problems of high processing cost and large chip mounting difficulty of the Bump process.

3. The scheme of the invention has no requirement on the height difference between the chip and the bonding pad needing interconnection, and can be compatible with larger height difference.

4. According to the scheme, the electrodes are interconnected through the copper bar or the thickened electroplating pad, the copper bar or the thickened electroplating pad is welded above the chip, the heat dissipation capacity of the device is greatly improved, the cross section area of the copper bar or the thickened electroplating pad is large, the conductivity is good, and the internal resistance value of the device can be reduced to the maximum extent.

The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.