阅读说明：本技术 一种新型六相电荷泵电路结构 (Novel six-phase charge pump circuit structure ) 是由 赵洪飞 张福泉 王国瑞 汪金铭 王圣礼 于 2021-08-12 设计创作，主要内容包括：本发明公开了一种新型六相电荷泵电路结构,包括PUMP-REG电路模块,所述PUMP-REG电路模块的输入端设有PUMP-STG电路模块,所述PUMP-STG电路模块的输入端设有六相非交叠时钟电路模块。本发明采用六相非交叠时钟电路,主要是产生相位依次错位,频率相同,使用六相非交叠时钟控制PUMP-STG,使M1/M2/M3/M4不存在同时导通的情况,也不存在交叠的情况,避免了相互影响,采用了DBBN和DBBP模块,避免寄生二极管导通漏电,CLK1/CLK2/CLK3/CLK4/CLKA/CLKB时采用的相位依次错位的频率相同,占空比50％的时钟,消除VTH压降,避免逆向电流产生,提高pump效率,简化时钟控制,增加动态衬底偏置,避免寄生二极管导通漏电,使PUMP-STG主体管子都单独导通,减少相互影响。(The invention discloses a novel six-phase charge PUMP circuit structure which comprises a PUMP _ REG circuit module, wherein the input end of the PUMP _ REG circuit module is provided with a PUMP _ STG circuit module, and the input end of the PUMP _ STG circuit module is provided with a six-phase non-overlapping clock circuit module. The invention adopts a six-phase non-overlapping clock circuit, mainly generates phase sequential dislocation, has the same frequency, controls the PUMP _ STG by using the six-phase non-overlapping clock, ensures that the M1/M2/M3/M4 has no condition of simultaneous conduction and no overlapping condition, avoids mutual influence, adopts DBBN and DBBP modules, avoids parasitic diodes from conducting and leaking electricity, adopts the same frequency of the phase sequential dislocation when CLK1/CLK2/CLK3/CLK4/CLKA/CLKB, has 50 percent of duty ratio clock, eliminates VTH voltage drop, avoids reverse current generation, improves PUMP efficiency, simplifies clock control, increases dynamic substrate bias, avoids parasitic diodes from conducting and leaking electricity, ensures that the tubes of the PUMP _ STG main body are independently conducted, and reduces mutual influence.)

1. A novel six-phase charge PUMP circuit structure, comprising a PUMP _ REG circuit module (1), characterized in that: the input end of the PUMP _ REG circuit module (1) is provided with a PUMP _ STG circuit module (2), and the input end of the PUMP _ STG circuit module (2) is provided with a six-phase non-overlapping clock circuit module (3).

2. The novel six-phase charge pump circuit structure of claim 1, wherein: the PUMP _ STG circuit module (2) comprises an NM1 transistor, an NM2 transistor, a PM1 transistor and a PM2 transistor, wherein the source end of the NM1 transistor and the source end of the NM2 transistor are all connected with a conversion output voltage, the drain end of the NM1 transistor is electrically connected with the drain end of the PM1 transistor, the drain end of the NM2 transistor is electrically connected with the drain end of the PM2 transistor, the gate end of the NM1 transistor is electrically connected with the gate end of the PM2 transistor, and the gate end of the NM2 transistor is electrically connected with the gate end of the PM1 transistor.

3. The novel six-phase charge pump circuit structure of claim 2, wherein: the output end of the PM1 transistor is provided with an NM3 transistor, a PM4 transistor and an NM4 transistor, the output end of the PM2 transistor is provided with a PM6 transistor, an NM6 transistor and a PM8 transistor, the source ends of the NM3 transistor, the drain end of the PM4 transistor and the source end of the NM4 transistor are all connected with the source end of the PM1 transistor, the drain end of the PM6 transistor, the source end of the NM6 transistor and the source end of the PM8 transistor are all electrically connected with the source end of the PM2 transistor, the gate end of the PM4 transistor and the gate end of the NM4 transistor are connected, and the gate end of the PM6 transistor and the gate end of the NM6 transistor are connected.

4. The novel six-phase charge pump circuit structure of claim 3, wherein: the output of NM3 transistor is equipped with the PM3 transistor, the output of PM4 transistor is equipped with the PM5 transistor, the output of NM4 transistor is equipped with NM5 transistor, just the drain-terminal of PM3 transistor is connected with the drain-terminal of NM3 transistor, the drain-terminal of PM5 transistor is connected with the source end of PM4 transistor, the source end of NM5 transistor is connected with the drain-terminal of NM4 transistor, the grid end of PM4 transistor is connected with the grid end of NM4 transistor, the grid end of PM5 transistor is connected with the grid end of NM5 transistor.

5. The novel six-phase charge pump circuit structure of claim 3, wherein: the output of PM6 transistor is equipped with the PM7 transistor, the output of NM6 transistor is equipped with NM7 transistor, the output of PM8 transistor is equipped with NM8 transistor, just the drain terminal of PM7 transistor is connected with the source end of PM6 transistor, the source end of NM7 transistor and the drain terminal electric connection of NM6 transistor, the drain terminal of NM8 transistor and the drain terminal electric connection of PM8 transistor, the grid end of PM6 transistor is connected with the grid end of NM6 transistor, the grid end of PM7 transistor is connected with the grid end of NM7 transistor.

6. The novel six-phase charge pump circuit structure of claim 4 or 5, wherein: the source end of the PM3 transistor, the source end of the PM5 transistor, the drain end of the NM5 transistor, the source end of the PM7 transistor, the drain end of the NM7 transistor and the source end of the NM8 transistor are all input with low-voltage domain voltage signals.

7. The novel six-phase charge pump circuit structure of claim 1, wherein: the PUMP _ STG circuit module (2) further comprises a PM9 transistor, a PM10 transistor, an NM10 transistor, a PM12 transistor, an NM12 transistor and an NM14 transistor, wherein the grid end of the PM10 transistor is connected with the grid end of the NM10 transistor, the grid end of the PM12 transistor is connected with the grid end of the NM12 transistor, and the source end of the PM9 transistor, the source end of the PM10 transistor, the drain end of the NM10 transistor, the source end of the PM12 transistor, the drain end of the NM12 transistor and the source end of the NM14 transistor are all connected to convert output voltage.

8. The novel six-phase charge pump circuit structure of claim 7, wherein: the output end of the PM9 transistor is provided with an NM9 transistor, the output end of the PM10 transistor is provided with a PM11 transistor, the output end of the NM10 transistor is provided with an NM11 transistor, the output end of the PM12 transistor is provided with a PM13 transistor, the output end of the NM12 transistor is provided with an NM13 transistor, the output end of the NM14 transistor is provided with a PM14 transistor, the drain end of the PM9 transistor is connected with the drain end of the NM9 transistor, the drain end of the PM10 transistor is connected with the source end of the PM11 transistor, the source end of the NM10 transistor is connected with the drain end of the NM11 transistor, the source end of the NM13 transistor is connected with the drain end of the PM12 transistor, the source end of the NM12 transistor is connected with the drain end of the NM13 transistor, and the drain end of the NM14 transistor is connected with the drain end of the PM14 transistor.

9. The novel six-phase charge pump circuit architecture of claim 8, wherein: the output ends of the NM9 transistor, the PM11 transistor and the NM11 transistor are provided with a PM15 transistor, the output ends of the PM13 transistor, the NM13 transistor and the PM14 transistor are provided with a PM16 transistor, the source terminal of the NM9 transistor, the drain terminal of the PM11 transistor and the source terminal of the NM11 transistor are all connected with the source terminal of the PM15 transistor, the drain terminal of the PM13 transistor, the source terminal of the NM13 transistor and the source terminal of the PM14 transistor are all connected with the source terminal of the PM16 transistor, the output end of the PM15 transistor is provided with an NM15 transistor, the output end of the PM16 transistor is provided with an NM16 transistor, the drain terminal of the NM15 transistor is connected with the drain terminal of the PM15 transistor, the drain terminal of the NM16 transistor is connected with the drain terminal of the PM16 transistor, the gate terminal of the PM15 transistor is connected with the gate terminal of the NM16 transistor, the gate terminal of the NM15 transistor is connected with the gate terminal of the PM16 transistor, the source terminal of the NM15 transistor and the source terminal of the NM16 transistor both input a low voltage domain voltage signal.

10. The novel six-phase charge pump circuit structure of claim 1, wherein: the PUMP _ STG circuit module (2) further comprises two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor and an M4 transistor, the DBBN modules are electrically connected with the DBBP modules, low-voltage domain voltage signals are input into drain terminals of the M3 transistor and drain terminals of the M4 transistor, drain terminals of the M1 transistor and drain terminals of the M2 transistor are connected with a conversion output voltage, the two DBBP modules are electrically connected with the M1 transistor and the M2 transistor respectively, the two DBBN modules are electrically connected with the M3 transistor and the M4 transistor respectively, and the six-phase non-overlapping clock circuit module (3) comprises a GLK1 interface, a GLK2 interface, a GLK3 interface, a GLK4 interface, a GLKA interface and a GLKB interface.

Technical Field

The invention relates to the technical field of integrated circuit chips, in particular to a novel six-phase charge pump circuit structure.

Background

The charge pump is generally of a two-phase or four-phase structure, commonly used two-phase charge pumps are of Dickson CP, Static CTS CP, Dynamic CTS CP and Pelliconi CP structures, and commonly used four-phase charge pumps are of CTS CP type and cross-coupled type.

The existing charge pump structure has the following defects:

1. the pump path has VTH voltage drop, and the pump efficiency is reduced;

2. the reverse current leaks electricity, so that the output voltage and the output current are reduced, and the pump efficiency is reduced;

3. when the substrate voltage of the NMOS tube/PMOS tube is higher or lower than the source or drain voltage, the parasitic diode conducts and leaks electricity;

4. the four-phase charge pump has complex clock control;

5. the four-phase charge pump has the condition that two input-stage pipes or two output-stage pipes are conducted simultaneously, so that the two input-stage pipes or the two output-stage pipes are influenced mutually, and the pump efficiency is reduced.

Disclosure of Invention

In order to overcome the above-mentioned drawbacks of the prior art, embodiments of the present invention provide a novel six-phase charge PUMP circuit structure, which employs a six-phase non-overlapping clock circuit, mainly generates phase sequential misalignment and frequency identity, controls PUMP _ STG using the six-phase non-overlapping clock, so that there is no simultaneous conduction and no overlapping between M1/M2/M3/M4, and avoids mutual influence, and employs DBBN and DBBP modules, to avoid parasitic diode conduction leakage, the frequency of phase sequential misalignment employed in CLK1/CLK2/CLK3/CLK4/CLKA/CLKB is identical, and a 50% duty cycle clock is used to eliminate VTH voltage drop, avoid reverse current generation, improve PUMP efficiency, simplify clock control, increase dynamic substrate bias, avoid parasitic diode conduction leakage, and make the bulk tubes of the PUMP _ STG conduct individually, and reduce mutual influence, to solve the problems set forth in the background art described above.

In order to achieve the purpose, the invention provides the following technical scheme: the circuit comprises a PUMP _ REG circuit module, wherein the input end of the PUMP _ REG circuit module is provided with a PUMP _ STG circuit module, and the input end of the PUMP _ STG circuit module is provided with a six-phase non-overlapping clock circuit module.

In a preferred embodiment, the PUMP _ STG circuit module includes an NM1 transistor, an NM2 transistor, a PM1 transistor, and a PM2 transistor, wherein a source terminal of the NM1 transistor and a source terminal of the NM2 transistor are all connected to the conversion output voltage, a drain terminal of the NM1 transistor is electrically connected to a drain terminal of the PM1 transistor, a drain terminal of the NM2 transistor is electrically connected to a drain terminal of the PM2 transistor, a gate terminal of the NM1 transistor is electrically connected to a gate terminal of the PM2 transistor, and a gate terminal of the NM2 transistor is electrically connected to a gate terminal of the PM1 transistor.

In a preferred embodiment, an output end of the PM1 transistor is provided with an NM3 transistor, a PM4 transistor and an NM4 transistor, an output end of the PM2 transistor is provided with a PM6 transistor, an NM6 transistor and a PM8 transistor, a source end of the NM3 transistor, a drain end of the PM4 transistor and a source end of the NM4 transistor are all connected with a source end of the PM1 transistor, a drain end of the PM6 transistor, a source end of the NM6 transistor and a source end of the PM8 transistor are all electrically connected with a source end of the PM2 transistor, a gate end of the PM4 transistor and a gate end of the NM4 transistor are connected, and a gate end of the PM6 transistor and a gate end of the NM6 transistor are connected.

In a preferred embodiment, the output end of the NM3 transistor is provided with a PM3 transistor, the output end of the PM4 transistor is provided with a PM5 transistor, the output end of the NM4 transistor is provided with an NM5 transistor, the drain end of the PM3 transistor is connected with the drain end of the NM3 transistor, the drain end of the PM5 transistor is connected with the source end of the PM4 transistor, the source end of the NM5 transistor is connected with the drain end of the NM4 transistor, the gate end of the PM4 transistor is connected with the gate end of the NM4 transistor, and the gate end of the PM5 transistor is connected with the gate end of the NM5 transistor.

In a preferred embodiment, the output end of the PM6 transistor is provided with a PM7 transistor, the output end of the NM6 transistor is provided with an NM7 transistor, the output end of the PM8 transistor is provided with an NM8 transistor, the drain end of the PM7 transistor is connected with the source end of the PM6 transistor, the source end of the NM7 transistor is electrically connected with the drain end of the NM6 transistor, the drain end of the NM8 transistor is electrically connected with the drain end of the PM8 transistor, the gate end of the PM6 transistor is connected with the gate end of the NM6 transistor, and the gate end of the PM7 transistor is connected with the gate end of the NM7 transistor.

In a preferred embodiment, a source terminal of the PM3 transistor, a source terminal of the PM5 transistor, a drain terminal of the NM5 transistor, a source terminal of the PM7 transistor, a drain terminal of the NM7 transistor, and a source terminal of the NM8 transistor all input a low-voltage domain voltage signal.

In a preferred embodiment, the PUMP _ STG circuit module further includes a PM9 transistor, a PM10 transistor, an NM10 transistor, a PM12 transistor, an NM12 transistor, and an NM14 transistor, wherein a gate terminal of the PM10 transistor is connected to a gate terminal of the NM10 transistor, a gate terminal of the PM12 transistor is connected to a gate terminal of the NM12 transistor, and a source terminal of the PM9 transistor, a source terminal of the PM10 transistor, a drain terminal of the NM10 transistor, a source terminal of the PM12 transistor, a drain terminal of the NM12 transistor, and a source terminal of the NM14 transistor are all connected to the converted output voltage.

In a preferred embodiment, an NM9 transistor is disposed at an output end of the PM9 transistor, a PM11 transistor is disposed at an output end of the PM10 transistor, an NM11 transistor is disposed at an output end of the NM10 transistor, a PM13 transistor is disposed at an output end of the PM12 transistor, an NM13 transistor is disposed at an output end of the NM12 transistor, a PM14 transistor is disposed at an output end of the NM14 transistor, a drain end of the PM9 transistor is connected to a drain end of the NM9 transistor, a drain end of the PM10 transistor is connected to a source end of the PM11 transistor, a source end of the NM10 transistor is connected to a drain end of the NM11 transistor, a source end of the NM13 transistor is connected to a drain end of the PM12 transistor, a source end of the NM12 transistor is connected to a drain end of the NM13 transistor, and a drain end of the NM14 transistor is connected to a drain end of the PM14 transistor.

In a preferred embodiment, the output terminals of the NM9 transistor, the PM11 transistor and the NM11 transistor are provided with a PM15 transistor, the output terminals of the PM13 transistor, the NM13 transistor and the PM14 transistor are provided with a PM16 transistor, the source terminals of the NM9 transistor, the drain terminal of the PM11 transistor and the NM11 transistor are all connected with the source terminal of the PM15 transistor, the drain terminal of the PM13 transistor, the source terminal of the NM13 transistor and the source terminal of the PM14 transistor are all connected with the source terminal of the PM16 transistor, the output terminal of the PM15 transistor is provided with an NM15 transistor, the output terminal of the PM16 transistor is provided with an NM16 transistor, the drain terminal of the NM15 transistor is connected with the drain terminal of the PM15 transistor, the drain terminal of the NM16 transistor is connected with the drain terminal of the PM16 transistor, the gate terminal of the PM15 transistor is connected with the gate terminal of the NM16 transistor, the gate terminal of the PM15 transistor is connected with the gate terminal of the PM16 transistor, the source terminal of the NM15 transistor and the source terminal of the NM16 transistor both input a low voltage domain voltage signal.

In a preferred embodiment, the PUMP _ STG circuit module further includes two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor, and an M4 transistor, and the DBBN modules are electrically connected to the DBBP modules, a drain terminal of the M3 transistor and a drain terminal of the M4 transistor are respectively inputted with a low-voltage domain voltage signal, a drain terminal of the M1 transistor and a drain terminal of the M2 transistor are both connected to a conversion output voltage, the two DBBP modules are respectively electrically connected to the M1 transistor and the M2 transistor, the two DBBN modules are respectively electrically connected to the M3 transistor and the M4 transistor, and the six-phase non-overlapping clock circuit module includes a GLK1 interface, a GLK2 interface, a GLK3 interface, a GLK4 interface, a GLKA interface, and a GLKB interface.

The invention has the technical effects and advantages that:

the six-phase non-overlapping clock circuit mainly generates clocks CLK1/CLK2/CLK3/CLK4/CLKA/CLKB with sequentially staggered phases, the same frequency and 50% duty ratio, a PUMP _ STG circuit, a main circuit of charge _ PUMP, and also a main circuit of the six-phase non-overlapping clock circuit, wherein the PUMP _ REG circuit is used for modifying the output of the charge _ PUMP and connecting the open-loop charge _ PUMP into a closed loop state, the output stable voltage is trimmed according to the requirement, six-phase non-overlapping clock is used for controlling the PUMP _ STG, so that the condition that M1/M2/M3/M4 are not conducted simultaneously does not exist, the DBBN and DBBP modules are adopted to avoid the conduction and leakage of a parasitic diode, the frequencies of the adopted phases are sequentially staggered and are the same when the CLK1/CLK2/CLK3/CLK4/CLKA/CLKB is adopted, and the clock with 50% of duty ratio is simple and easy to understand;

1. VTH pressure drop is eliminated, and pump efficiency is improved;

2. reverse current is avoided, and pump efficiency is improved;

3. clock control is simplified;

4. the dynamic substrate bias is increased, and the conduction and leakage of a parasitic diode are avoided;

5. the main pipes of the PUMP _ STG are independently conducted, so that the mutual influence is reduced, and the PUMP efficiency is improved.

Drawings

FIG. 1 is a schematic diagram of a four-stage PUMP _ STG series system according to the present invention.

FIG. 2 is a schematic diagram of a two-string two-parallel PUMP _ STG system according to the present invention.

FIG. 3 is a schematic circuit diagram of the PUMP _ STG of the present invention.

FIG. 4 is a timing diagram of a six-phase non-overlapping clock circuit block of the present invention.

The reference signs are: 1. a PUMP _ REG circuit module; 2. a PUMP _ STG circuit module; 3. a six-phase non-overlapping clock circuit block.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-4 of the specification, a novel six-phase charge PUMP circuit structure according to an embodiment of the present invention includes a PUMP _ REG circuit module 1, a PUMP _ STG circuit module 2 is disposed at an input end of the PUMP _ REG circuit module 1, a six-phase non-overlapping clock circuit module 3 is disposed at an input end of the PUMP _ STG circuit module 2, the PUMP _ STG circuit module 2 includes a NM1 transistor, a NM2 transistor, a PM1 transistor, and a PM2 transistor, a source end of the NM1 transistor and a source end of the NM2 transistor are all connected to a conversion output voltage, a drain end of the NM1 transistor is electrically connected to a drain end of the PM1 transistor, a drain end of the NM2 transistor is electrically connected to a drain end of the PM2 transistor, a gate end of the NM1 transistor is electrically connected to a gate end of the PM2 transistor, a gate end of the NM2 transistor is electrically connected to a gate end of the PM1 transistor, and a six-phase non-overlapping clock circuit mainly generates phase shift in sequence, the frequency is the same, the frequency of the clock CLK1/CLK2/CLK3/CLK4/CLKA/CLKB with 50% duty ratio, the PUMP _ STG circuit and the main circuit of the charge _ PUMP are also main circuits of the invention, the PUMP _ REG circuit is used for modifying the output of the charge _ PUMP, the open-loop charge _ PUMP is connected into a closed loop state, the output stable voltage is modified according to the requirement, the PUMP _ STG is controlled by using a six-phase non-overlapping clock, the condition that M1/M2/M3/M4 is not simultaneously conducted or overlapped is not existed, the mutual influence is avoided, a DBBN module and a DBBP module are adopted, the conduction leakage of a parasitic diode is avoided, the frequency of the adopted phase when CLK1/CLK2/CLK3/CLK4/CLKA/CLKB is sequentially staggered is the same, the clock with 50% duty ratio is simple and easy to understand.

Further, the output terminal of the PM1 transistor is provided with an NM1 transistor, a PM1 transistor and an NM1 transistor, the output terminal of the PM1 transistor is provided with a PM1 transistor, an NM1 transistor and a PM1 transistor, the source terminals of the NM1 transistor, the drain terminal of the PM1 transistor and the source terminal of the NM1 transistor are all connected with the source terminal of the PM1 transistor, the gate terminal of the PM1 transistor and the gate terminal of the NM1 transistor are connected, when t is t1, CLK 1/CLKA are all at a low level, and CLKB is only PM 1/PM1, PM 1/PM 1/PA when t is at a, so that VIN is turned on, and VIN PA is PA, so M1/M2/M3/M4 is off.

Further, a PM3 transistor is arranged at an output end of the NM3 transistor, a PM5 transistor is arranged at an output end of the PM4 transistor, an NM5 transistor is arranged at an output end of the NM4 transistor, a drain end of the PM3 transistor is connected with a drain end of the NM3 transistor, a drain end of the PM5 transistor is connected with a source end of the PM4 transistor, a source end of the NM5 transistor is connected with a drain end of the NM4 transistor, a gate end of the PM4 transistor is connected with a gate end of the NM4 transistor, a gate end of the PM5 transistor is connected with a gate end of the NM5 transistor, when t is 1, CLK2/CLK 2/CLK3/CLK4/CLKB is at a low level, CLKA is at a high level, VA is raised with CLKA, VB is pulled down with CLKB, and M1/M2/M3/M4 is kept off.

Further, an output end of the PM6 transistor is provided with a PM6 transistor, an output end of the NM6 transistor is provided with an NM6 transistor, an output end of the PM6 transistor is provided with an NM6 transistor, a drain end of the PM6 transistor is connected with a source end of the PM6 transistor, a source end of the NM6 transistor is electrically connected with a drain end of the NM6 transistor, a drain end of the NM6 transistor is electrically connected with a drain end of the PM6 transistor, a gate end of the PM6 transistor is connected with a gate end of the NM6 transistor, when t6 is equal to t6, CLK 6/CLKB is low, CLK 6/CLK is high, only NM 6/PM 6 is on, so that NA is equal to mn 6/PA, so that mn 6/PA 6/PM 6 is turned on, current flows from VIN into VB until VB ═ VIN.

Further, a source terminal of the PM3 transistor, a source terminal of the PM5 transistor, a drain terminal of the NM5 transistor, a source terminal of the PM7 transistor, a drain terminal of the NM7 transistor, and a source terminal of the NM8 transistor are all inputted with a low voltage domain voltage signal, the PUMP-STG circuit module 2 further includes a PM9 transistor, an NM9 transistor, a gate terminal of the PM9 transistor is connected with a gate terminal of the NM9 transistor, a source terminal of the PM9 transistor, a drain terminal of the NM9 transistor, a source terminal of the NM9 transistor, a drain terminal of the NM9 transistor, and a source terminal of the NM9 transistor are all switched in a conversion output voltage, when t is t9, CLK 9/CLKB is all in a low level, CLK 9/NM 9/9 a/72 a NM9 a high level is only when t 9/9 a high level is reached The paths NM14/PM14 and PM15/NM15 are turned on, so PA-NB-VIN and PB-VOUT, so M2/M3/M4 are turned off, M1 is turned on, and current flows from VA to VOUT until VOUT reaches VA.

Further, an output end of the PM9 transistor is provided with an NM9 transistor, an output end of the PM10 transistor is provided with a PM11 transistor, an output end of the NM10 transistor is provided with an NM11 transistor, an output end of the PM12 transistor is provided with a PM13 transistor, an output end of the NM12 transistor is provided with an NM13 transistor, an output end of the NM14 transistor is provided with a PM14 transistor, a drain end of the PM9 transistor is connected with a drain end of the NM9 transistor, a drain end of the PM9 transistor is connected with a source end of the PM9 transistor, a source end of the NM9 transistor is connected with a drain end of the NM9 transistor, a source end of the NM9 transistor is connected with a drain end of the PM9 transistor, and CLKB is low, CLK 9/CLK/9/CLK is high/CLK a 9 a, at this time, only NM4/NM5, NM6/NM7, NM10/NM11 and NM12/NM13 are on, so NA-NB-VIN and PA-PB-VOUT are off, and M1/M2/M3/M4 are off.

Further, the output ends of the NM9 transistor, the PM11 transistor and the NM11 transistor are provided with a PM15 transistor, the output ends of the PM13 transistor, the NM13 transistor and the PM14 transistor are provided with a PM16 transistor, the source ends of the NM9 transistor, the drain end of the PM11 transistor and the NM11 transistor are all connected with the source end of the PM15 transistor, the drain end of the PM13 transistor, the source end of the NM13 transistor and the source end of the PM14 transistor are all connected with the source end of the PM16 transistor, the output end of the PM15 transistor is provided with a NM15 transistor, the output end of the PM16 transistor is provided with a NM16 transistor, the drain end of the NM15 transistor is connected with the drain end of the PM15 transistor, the drain end of the NM16 transistor is connected with the drain end of the PM16 transistor, the gate end of the PM15 transistor is connected with the gate end of the NM16 transistor, the NM15 transistor is connected with the gate end of the PM16 transistor, the NM15 transistor is connected with the source end of the PM16 transistor, and the input end of the PM15 transistor is connected with the low voltage input region, when t is t6, CLKA is low, CLK1/CLK2/CLK3/CLK4/CLKB is high, and only NM4/NM5, NM6/NM7, NM10/NM11, NM12/NM13 paths are on at this time, so NA is NB is VIN, PA is PB is VOUT, so M1/M2/M3/M4 is off, and VA is lowered to VC (VC < VIN) with CLKA, VB is raised with CLKB, and VB is VIN + VCLKB.

Further, the PUMP _ STG circuit module 2 further includes two DBBN modules, two DBBP modules, an M1 transistor, an M2 transistor, an M3 transistor, and an M4 transistor, the DBBN modules are electrically connected to the DBBP modules, a drain terminal of the M3 transistor and a drain terminal of the M4 transistor are respectively inputted with a low-voltage domain voltage signal, a drain terminal of the M1 transistor and a drain terminal of the M2 transistor are both connected to the conversion output voltage, the two DBBP modules are respectively electrically connected to the M1 transistor and the M2 transistor, the two DBBN modules are respectively electrically connected to the M3 transistor and the M4 transistor, the six-phase non-overlapping clock circuit module 3 includes a GLK1 interface, a GLK2 interface, a GLK3 interface, a 4 interface, a GLKA interface, and a GLKB interface, when t is equal to t7, CLK 2/CLKA is at a low level, CLK 53/1/NM 3/NM, and when t is equal to PM 868672/8672, only PM 8672/8672 The NM10/NM11 and NM12/NM13 channels are conducted, so that NB is VIN, NA is PA is PB is VOUT, and M1/M2/M4 is closed; m3 is turned on, the current is transmitted from VIN to VA until VA is VIN, when t is t8, CLK3/CLK4/CLKA is low, CLK1/CLK2/CLKB is high, at this time, only PM4/PM5, PM6/PM7, NM10/NM11, NM12/NM13 are on, so that NA is NB is VIN, PA is PB is VOUT, so M1/M2/M3/M4 is off, when t is t9, CLK1/CLK3/CLK4/CLKA is low, CLK2/CLKB is high, at this time, only PM4/PM5, PM6/PM7, PM 9/9, PM 16/M16 is on, so that mn 4/PM 1/NM 1 is off; m2 turns on and current flows from VB to VOUT until VOUT becomes VB.

Example 1:

when t is t0, CLK1/CLK2/CLK3/CLK4/CLKA are all low, and CLKB is high, and only paths of PM4/PM5, PM6/PM7, PM10/PM11 and PM12/PM13 are on, so that NA is NB is VIN, PA is PB is VOUT, and M1/M2/M3/M4 is off;

when t is t1, CLK1/CLK2/CLK3/CLK4/CLKB are all low level, CLKA is high, VA is raised along with CLKA, VB is pulled down along with CLKB, and M1/M2/M3/M4 are kept closed;

when t is t2, CLK1/CLK2/CLK3/CLKB are all low level, CLK4/CLKA is high, and at this time, only NM2/PM2, NM3/PM3, PM10/PM11, PM12/PM13 paths are on, so NA is VIN, NB is PA is PB is VOUT, so M1/M2/M3 is off, M4 is on, and current flows from VIN to VB until VB is VIN;

when t is t3, CLK1/CLK2/CLKB are all low, CLK3/CLK4/CLKA is high, and at this time, only NM4/NM5, NM6/NM7, PM10/PM11, and PM12/PM13 paths are on, so that NA is NB is VIN, PA is PB is VOUT, and M1/M2/M3/M4 is off;

when t is t4, CLK1/CLKB are both low level, CLK2/CLK3/CLK4/CLKA are high, and at this time, only NM4/NM5, NM6/NM7, NM14/PM14, PM15/NM15 paths are on, so PA is NA NB VIN, PB is VOUT, so M2/M3/M4 is off, M1 is on, and current flows from VA to VOUT until VOUT is VA;

when t is t5, CLKB is low, CLK1/CLK2/CLK3/CLK4/CLKA is high, and only NM4/NM5, NM6/NM7, NM10/NM11, NM12/NM13 paths are on, so NA is NB is VIN, PA is PB is VOUT, so M1/M2/M3/M4 is off;

when t is t6, CLKA is low, CLK1/CLK2/CLK3/CLK4/CLKB is high, and only NM4/NM5, NM6/NM7, NM10/NM11, NM12/NM13 paths are on at this time, so NA is NB is VIN, PA is PB is VOUT, so M1/M2/M3/M4 is off, VA is lowered to VC (VC is VIN) with CLKA, VB is raised with CLKB, and VB is VIN + VCLKB;

when t is t7, CLK4/CLKA is low, CLK1/CLK2/CLK3/CLKB is high, and only NM1/PM1, PM8/NM8, NM10/NM11, NM12/NM13 paths are on at this time, so NB is VIN, NA is PA is VOUT, and M1/M2/M4 is off; m3 is turned on and current passes from VIN to VA until VA ═ VIN;

ninthly, when t is t8, CLK3/CLK4/CLKA is low level, CLK1/CLK2/CLKB is high, and only PM4/PM5, PM6/PM7, NM10/NM11 and NM12/NM13 paths are on, so that NA is NB is VIN, PA is PB is VOUT, and M1/M2/M3/M4 is off;

when t is t9, CLK1/CLK3/CLK4/CLKA is low, CLK2/CLKB is high, and only PM4/PM5, PM6/PM7, PM9/NM9, PM16/NM16 paths are on at this time, so PB — NB — VIN, PA — VOUT, so M1/M3/M4 is off; m2 turns on and current flows from VB to VOUT until VOUT becomes VB;

the working principle time sequence ((c)) - (r) ((c) ()) - (r) ((c) ()) is a CLK period, CLKA/CLKB/CLK1/CLK2/CLK3/CLK4 is a non-overlapping clock with the same frequency and different phases, M1/M2/M3/M4 are all independently started, the condition of simultaneous conduction does not exist, DBBN/DBBP is a dynamic substrate bias circuit of NMOS and PMOS respectively, the Bulk of the NMOS can be always connected to one end with lower voltage by adopting DBBN, and the Bulk of the PMOS can be always connected to one end with higher voltage by adopting DBBP similarly.

Example 2: fig. 1 shows a four-stage PUMP _ STG series system structure, which is suitable for high-voltage output and low-current driving capability applications, such as Vcc 3.3v and PUMP _ out 13.2 v; the number of stages is determined as required.

Example 3: fig. 2 shows a two-serial two-parallel PUMP _ STG system structure, which is suitable for high current driving capability applications, and the number of parallel stages is determined according to the requirement.

The points to be finally explained are: first, in the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounted," "connected," and "connected" should be understood broadly, and may be a mechanical connection or an electrical connection, or a communication between two elements, and may be a direct connection, and "upper," "lower," "left," and "right" are only used to indicate a relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may be changed;

secondly, the method comprises the following steps: in the drawings of the disclosed embodiments of the invention, only the structures related to the disclosed embodiments are referred to, other structures can refer to common designs, and the same embodiment and different embodiments of the invention can be combined with each other without conflict;

and finally: the above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that are within the spirit and principle of the present invention are intended to be included in the scope of the present invention.