阅读说明：本技术 基于奇偶校验提高fpga运行可靠性的方法 (Method for improving FPGA operation reliability based on parity check ) 是由 单悦尔 徐彦峰 季振凯 惠锋 于 2021-08-19 设计创作，主要内容包括：本发明公开了一种基于奇偶校验提高FPGA运行可靠性的方法,涉及FPGA技术领域,该方法在生成用户设计对应的初始配置码流后,将其处理为逻辑功能不变、但所有配置链具有全偶校验或者全奇校验的基准配置码流,继而再下载到FPGA内,FPGA正常运行用户设计的过程中,其内部控制电路通过校验器即可对存储的配置链进行校验,并在校验出错时由外部的基准配置码流覆盖更新,从而保证内部存储的基准配置码流的准确性,提高FPGA的运行可靠性。(The invention discloses a method for improving FPGA operation reliability based on parity check, which relates to the technical field of FPGA, and is characterized in that after an initial configuration code stream corresponding to user design is generated, the initial configuration code stream is processed into a reference configuration code stream with unchanged logic function but all configuration chains have full even check or full odd check, and then the reference configuration code stream is downloaded into the FPGA.)

1. A method for improving FPGA operation reliability based on parity check is characterized in that the method comprises the following steps:

generating initial configuration code streams which correspond to user design of the FPGA and take configuration chains as units, wherein each configuration chain comprises continuous configuration bits with preset digits in the initial configuration code streams;

performing data processing on the initial configuration code stream to obtain a reference configuration code stream which takes a configuration chain as a unit and all has a target parity check result, wherein the logic function of the reference configuration code stream is the same as that of the initial configuration code stream, and the target parity check result is odd check or even check;

and sequentially writing the reference configuration code stream into the FPGA for storage by taking the configuration chain as a unit, wherein a checker and a control circuit are integrated in the FPGA, the control circuit traverses the configuration chain stored in the FPGA at preset time intervals in the process of normal operation user design of the FPGA and sends the configuration chain into the checker to check whether the target parity check result exists, and when the configuration chain is checked to be wrong, the reference configuration code stream outside the FPGA is used for updating the reference configuration code stream stored in the FPGA in a covering manner.

2. The method according to claim 1, wherein the performing data processing on the initial configuration code stream includes:

and the configuration chain with the target parity check result in the initial configuration code stream is kept unchanged, the data of the target configuration bits which accord with a preset rule in the configuration chain without the target parity check result is modified to be adjusted to have the target parity check result, and the target configuration bits which accord with the preset rule are the configuration bits which do not influence the logic function realized by the configuration code stream.

3. The method of claim 2,

when the configuration bit corresponds to a signal end in an idle module in the FPGA, an idle signal end in a working module or a working signal end which is a random value in the working module under the current mode, determining that the configuration bit accords with the preset rule;

the idle module is a configurable module which is not used in the user design in the FPGA, the working module is a configurable module which is used in the user design in the FPGA, the idle signal terminal is a signal terminal which is not used in the user design in the working module, and the working signal terminal is a signal terminal which is used in the user design in the working module.

4. The method of claim 3, further comprising:

for a configuration chain without a target parity check result, if a configuration bit corresponding to a signal end in an idle module in the FPGA exists in the configuration chain, selecting the configuration bit corresponding to the signal end in the idle module in the FPGA as the target configuration bit;

if the configuration bit corresponding to the signal end in the idle module in the FPGA does not exist and the configuration bit corresponding to the idle signal end in the working module exists, selecting the configuration bit corresponding to the idle signal end in the working module as the target configuration bit;

and if the configuration bit corresponding to the idle signal end in the working module does not exist and the configuration bit corresponding to the working signal end which is at random value in the working module in the current mode exists, selecting the working signal end which is at random value in the working module in the current mode as the target configuration bit.

5. The method according to claim 4, wherein if there are at least two configuration bits in the configuration chain that meet the predetermined rule and belong to the same rule category, any one of the configuration bits is selected as the target configuration bit, and the rule category includes a signal terminal corresponding to an idle module in the FPGA, an idle signal terminal corresponding to an active module, and an active signal terminal corresponding to an active module that is at an arbitrary value in the active module in the current mode.

6. The method of claim 2, further comprising:

and for the configuration chain without the target parity check result, if the configuration chain does not have the configuration bit meeting the preset rule, the step of generating the initial configuration code stream which corresponds to the user design of the FPGA and takes the configuration chain as a unit is executed again under the new layout and wiring result.

7. The method according to claim 1, wherein when the target parity result is an even parity, the performing data processing on the initial configuration code stream includes:

and respectively performing parity check on each configuration chain in the initial configuration code stream, and adding a one-bit parity check result of each configuration chain into the configuration chains to obtain configuration chains of which the parity check results in the reference configuration code stream are even check, so that each configuration chain in the reference configuration code stream has one more bit relative to the corresponding configuration chain in the initial configuration code stream.

8. The method according to any one of claims 1 to 7, wherein the performing overlay update on the reference configuration code stream stored inside the FPGA by using the reference configuration code stream outside the FPGA comprises:

and rewriting the reference configuration code stream from the exterior of the FPGA to perform full-chip reconfiguration.

9. The method according to any one of claims 1 to 7, wherein the performing overlay update on the reference configuration code stream stored inside the FPGA by using the reference configuration code stream outside the FPGA comprises:

and the control circuit transmits an error configuration chain address to the outside of the FPGA, the error configuration chain address is the address of the configuration chain for checking errors, and the configuration chain corresponding to the error configuration chain address in the reference configuration code stream is rewritten from the outside of the FPGA to reconfigure the configuration chain for checking errors.

10. The method of claim 9, wherein the control circuit transmits the misconfiguration link address to outside the FPGA through a configuration port or a dynamically reconfigurable port.

11. A method according to any of claims 1-7, characterized in that the control circuit traverses all configuration chains or parts of configuration chains in a predetermined order at a time and feeds them to the checker for checking.

12. The method of claim 11 wherein the predetermined order of traversal is an address order of configuration chains.

13. The FPGA of any one of claims 1-7, further comprising a timer connected to the control circuit, wherein the control circuit traverses the configuration chain stored inside the FPGA according to the delay duration of the timer and sends the configuration chain to the checker for checking, and an input clock of the timer is from outside the FPGA or from inside the FPGA.

14. The FPGA of claim 13,

and when receiving an instant enabling signal, the timer immediately triggers the control circuit to traverse the configuration chain and sends the configuration chain into the checker for checking, wherein the instant enabling signal comes from the exterior of the FPGA or from the user design in the FPGA.

15. The FPGA of any one of claims 1-7, wherein the control circuit is connected to a built-in boundary scan chain of the FPGA, and the control circuit obtains an external control signal of the FPGA through the built-in boundary scan chain, and traverses a configuration chain stored inside the FPGA and sends the configuration chain to a checker for checking.

Technical Field

The invention relates to the technical field of FPGA, in particular to a method for improving the running reliability of FPGA based on parity check.

Background

With the development of very large scale integrated circuit technology, an FPGA (Field Programmable Gate Array) chip is widely used depending on its superior interface performance, abundant logic and IP resources, and flexible and convenient Field Programmable capability.

The FPGA chip is internally provided with a configurable module and a winding resource, and when the user design is mapped to the FPGA chip, the user design can determine the function realized by the configurable module in the FPGA chip and the winding path selected by the winding resource by defining configuration content (the content of a configuration bit), so that the function realized by the FPGA chip is defined. The FPGA design software carries out the sum-up, layout and wiring processing on the user design input, maps the user design input to the FPGA chip, and generates a code stream file according to the preset format according to the configuration content of the configurable module and the winding resource. The code stream is downloaded to the FPGA device, each configuration content can be correctly filled, the function of the FPGA chip is defined, and after the downloading is completed, the FPGA chip is operated to realize the function of user design.

The FPGA chip is affected by external factors such as power supply, radiation, electromagnetism, and particles, and is prone to a Single Event Upset (SEU) problem, thereby causing an error in the inversion of configuration contents and causing a failure in circuit functions.

Disclosure of Invention

The invention provides a method for improving the running reliability of an FPGA (field programmable gate array) based on parity check aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a method for improving FPGA operation reliability based on parity check comprises:

generating initial configuration code streams which correspond to user design of the FPGA and take configuration chains as units, wherein each configuration chain comprises continuous configuration bits with preset digits in the initial configuration code streams;

performing data processing on the initial configuration code stream to obtain a reference configuration code stream which takes the configuration chain as a unit and all has a target parity check result, wherein the logic function of the reference configuration code stream is the same as that of the initial configuration code stream, and the target parity check result is odd check or even check;

the method comprises the steps that a reference configuration code stream is sequentially written into an FPGA for storage by taking a configuration chain as a unit, a checker and a control circuit are integrated in the FPGA, the control circuit traverses the configuration chain stored in the FPGA at preset time intervals in the process of normal operation user design of the FPGA and sends the configuration chain into the checker to check whether a target parity check result exists, and when the configuration chain is checked to be wrong, the reference configuration code stream stored in the FPGA is covered and updated by using the reference configuration code stream outside the FPGA.

The further technical scheme is that the data processing is carried out on the initial configuration code stream, and the data processing comprises the following steps:

and the configuration chain with the target parity check result in the initial configuration code stream is kept unchanged, the data of the target configuration bits which accord with the preset rules in the configuration chain without the target parity check result is modified to be adjusted to have the target parity check result, and the target configuration bits which accord with the preset rules are the configuration bits which do not influence the logic function realized by the configuration code stream.

The method comprises the following steps that when a configuration bit corresponds to a signal end in an idle module in the FPGA, an idle signal end in a working module or a working signal end which is a random value in a working module under a current mode, the configuration bit is determined to accord with a preset rule;

the idle module is a configurable module which is not used in user design in the FPGA, the working module is a configurable module which is used in user design in the FPGA, the idle signal end is a signal end which is not used in user design in the working module, and the working signal end is a signal end which is used in user design in the working module.

The further technical scheme is that the method also comprises the following steps:

for a configuration chain without a target parity check result, if a configuration bit corresponding to a signal end in an idle module in the FPGA exists in the configuration chain, selecting the configuration bit corresponding to the signal end in the idle module in the FPGA as a target configuration bit;

if the configuration bit corresponding to the signal end in the idle module in the FPGA does not exist and the configuration bit corresponding to the idle signal end in the working module exists, selecting the configuration bit corresponding to the idle signal end in the working module as a target configuration bit;

and if the configuration bit corresponding to the idle signal end in the working module does not exist and the configuration bit corresponding to the working signal end which is at random value in the working module in the current mode exists, selecting the working signal end which is at random value in the working module in the current mode as the target configuration bit.

The method comprises the following steps that if at least two configuration bits which accord with a preset rule and belong to the same rule category exist in a configuration chain, one configuration bit is selected from the configuration bits as a target configuration bit, and the rule category comprises a signal end corresponding to an idle module in an FPGA (field programmable gate array), an idle signal end corresponding to a working module and a working signal end corresponding to a working module which is of an arbitrary value in a current mode.

The further technical scheme is that the method also comprises the following steps:

and for the configuration chain without the target parity check result, if the configuration chain does not have the configuration bits meeting the preset rules, the step of generating the initial configuration code stream which is corresponding to the user design of the FPGA and takes the configuration chain as a unit is executed again under the new layout and wiring result.

The further technical scheme is that when the target parity check result is the even check, the data processing is carried out on the initial configuration code stream, and the data processing comprises the following steps:

and respectively performing parity check on each configuration chain in the initial configuration code stream, adding a one-bit parity check result of each configuration chain into the configuration chains, and obtaining the configuration chains of which the parity check results in the reference configuration code stream are even checks, wherein each configuration chain in the reference configuration code stream has one more bit relative to the corresponding configuration chain in the initial configuration code stream.

The further technical scheme is that the method for updating the coverage of the reference configuration code stream stored in the FPGA by using the reference configuration code stream outside the FPGA comprises the following steps:

and rewriting the reference configuration code stream from the outside of the FPGA to perform full-chip reconfiguration.

The further technical scheme is that the method for updating the coverage of the reference configuration code stream stored in the FPGA by using the reference configuration code stream outside the FPGA comprises the following steps:

the control circuit transmits the address of the error configuration chain to the exterior of the FPGA, the address of the error configuration chain is the address of the configuration chain for checking the error, and the configuration chain corresponding to the address of the error configuration chain in the reference configuration code stream is rewritten from the exterior of the FPGA to reconfigure the configuration chain for checking the error.

The further technical proposal is that the control circuit transmits the error configuration chain address to the exterior of the FPGA through the configuration port or the dynamic reconfigurable port.

The control circuit traverses all configuration chains or part of configuration chains according to a preset sequence every time and sends the configuration chains or part of the configuration chains to the checker for checking.

The further technical scheme is that the predetermined sequence during traversal is the address sequence of the configuration chain.

The FPGA further comprises a timer connected with the control circuit, the control circuit traverses a configuration chain stored in the FPGA according to the delay time of the timer and sends the configuration chain into the checker for checking, and an input clock of the timer comes from the exterior of the FPGA or from the interior of the FPGA.

The further technical scheme is that the timer immediately triggers the control circuit to traverse the configuration chain and sends the configuration chain into the checker for checking when receiving the instant enabling signal, and the instant enabling signal is from the exterior of the FPGA or from the user design in the FPGA.

The control circuit is connected with a built-in boundary scan chain of the FPGA, acquires an external control signal of the FPGA through the built-in boundary scan chain, traverses a configuration chain stored in the FPGA and sends the configuration chain to the checker for checking.

The invention has the beneficial effects that:

the application discloses a method for improving FPGA operation reliability based on parity check, which is characterized in that after an initial configuration code stream corresponding to user design is obtained, the initial configuration code stream is processed into a reference configuration code stream with a logic function unchanged but with full even check or full odd check, and then the reference configuration code stream is downloaded into an FPGA, so that in the operation process of the FPGA, the configuration chain can be checked and covered and updated only by using fewer circuits inside the FPGA, the accuracy of the reference configuration code stream stored inside is ensured, and the operation reliability of the FPGA is improved.

Drawings

FIG. 1 is a schematic flow diagram of a method disclosed herein.

Fig. 2 is a schematic flow chart of determining a target configuration bit in a configuration chain in the present application.

Fig. 3 is a schematic diagram of the structure inside the FPGA in the present application.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses a method for improving FPGA operation reliability based on parity check, which comprises the following steps, please refer to FIG. 1:

step 1, generating an initial configuration code stream which corresponds to the user design of the FPGA and takes a configuration chain as a unit. Each configuration chain comprises continuous configuration bits with a predetermined number of bits in the initial configuration code stream, such as 1024 bits or 2048 bits or any custom bit number. The configuration code stream written in by the FPGA mainly comprises two types of packets, wherein the first type of packet designates a configuration block, a starting configuration bit, a length and other related control instructions which are correspondingly stored, and the second type of packet comprises the actual configuration bit content.

And 2, performing data processing on the initial configuration code stream to obtain a reference configuration code stream which takes the configuration chain as a unit and all has a target parity check result, wherein the target parity check result is odd check or even check. The application provides the following two data processing methods:

the first data processing method comprises the following steps: the data processing method can process to obtain a reference configuration code stream with odd check or even check, and the bit number of the obtained reference configuration code stream is equal to that of the initial configuration code stream.

In the initial configuration code stream generated according to the conventional code stream generation rule, part of configuration chains may be odd check and part of configuration chains are even check, in this step, all configuration chains are unified into odd check or unified into even check through data processing, and thus, the reference configuration code stream which takes the configuration chains as a unit and all has the target parity check result is obtained after the data processing is completed.

Specifically, after the data of the target configuration bits meeting the predetermined rule in the configuration chain without the target parity check result is modified to have the target parity check result, and the target configuration bits meeting the predetermined rule are configuration bits that do not affect the logic function implemented by the configuration code stream, that is, after the data of the target configuration bits are adjusted, the check result of the configuration chain changes, but the logic function implemented as a whole remains unchanged, so that the obtained reference configuration code stream has the same logic function as the logic function implemented by the initial configuration code stream.

In one embodiment, when one configuration bit corresponds to a signal terminal in an idle module in the FPGA, an idle signal terminal in a working module, or a working signal terminal in a working module that is an arbitrary value in a current mode, it is determined that the configuration bit meets a predetermined rule and can be selected as a target configuration bit. The idle module is a configurable module which is not used in the user design in the FPGA, and the idle module is not normally connected with an output, so that the value of the configuration bit in the idle module does not influence the logic function and can be selected as a target configuration bit. The working module is a configurable module used in user design in the FPGA, the idle signal end is a signal end which is not used in the user design in the working module, only part of the signal ends are possibly used in the working module, and for the unused idle signal end, the value of the configuration bit does not influence the logic function and can be selected as a target configuration bit. For example, the 6-input lookup table has 64 configuration bits, if the 6-input lookup table is used to implement a 5-input logic function, only 32 configuration bits need to be used, and the remaining 32 configuration bits are idle signal terminals, do not affect the logic function, and can be modified by a selected target configuration bit. The working signal terminal is a signal terminal used in a user design in a working module, when some configurable modules in the FPGA realize a specific function, some configuration bits are just not used in a current mode, and a value of the configuration bits may be 0 or 1, and a value of the configuration bits is generally represented as x (don't care) in a function truth table to indicate that the configuration bits may be arbitrary values, and at this time, modifying the value of the configuration bits does not affect a logic function in the current mode.

In a configuration chain without a target parity result, there may be a plurality of configuration bits that meet a predetermined rule, one of which needs to be selected as a target configuration bit, one of which is randomly selected as a target configuration bit. In another embodiment, the configuration bits are selected from different rule categories in a predetermined order, the predetermined order for the different rule categories comprising, in order from first to last: corresponding to a signal terminal in an idle module in the FPGA, corresponding to an idle signal terminal in a working module, and corresponding to a working signal terminal in the working module that is a random value in a current mode, please refer to fig. 2 specifically:

and for the configuration chain without the target parity check result, if the configuration chain has the configuration bit corresponding to the signal end in the idle module in the FPGA, selecting the configuration bit corresponding to the signal end in the idle module in the FPGA as the target configuration bit. Generally, the design utilization rate of the FPGA is less than 90%, so that there are many idle modules, and most of the cases, the corresponding configuration bits can be found in this step.

And if the configuration bit corresponding to the signal end in the idle module in the FPGA does not exist and the configuration bit corresponding to the idle signal end in the working module exists, selecting the configuration bit corresponding to the idle signal end in the working module as the target configuration bit.

And if the configuration bit corresponding to the idle signal end in the working module does not exist and the configuration bit corresponding to the working signal end which is at random value in the working module in the current mode exists, selecting the working signal end which is at random value in the working module in the current mode as the target configuration bit.

If the configuration chain does not have a configuration bit meeting the preset rule, namely in the sequential judgment process, when the working signal end which is corresponding to the random value in the working module in the current mode does not exist, the step of generating the initial configuration code stream which is corresponding to the user design of the FPGA and takes the configuration chain as a unit is executed again under the new layout and wiring result, and the operation is executed again under the new initial configuration code stream.

In the above process, for each rule class, if there is one configuration bit that meets a predetermined rule and belongs to the rule class in the configuration chain, the configuration bit is taken as a target configuration bit. And if at least two configuration bits which accord with a preset rule and belong to the rule category exist in the configuration chain, selecting one configuration bit from the configuration chain as a target configuration bit. That is, when a plurality of configuration bits corresponding to a signal end in an idle module in the FPGA exist in the configuration chain, one of the configuration bits is selected as a target configuration bit; when determining that the configuration chain does not have a configuration bit corresponding to a signal end in an idle module in the FPGA but has a plurality of configuration bits corresponding to idle signal ends in a working module, selecting one of the configuration bits as a target configuration bit; when it is determined that there is no configuration bit corresponding to the idle signal terminal in the operation module but there are a plurality of configuration bits corresponding to the operation signal terminals in the operation module that are arbitrary values in the current mode, one of them is selected as a target configuration bit.

The second data processing method comprises the following steps: and respectively carrying out parity check on each configuration chain in the initial configuration code stream, and adding a bit of parity check result of each configuration chain into the configuration chains to obtain the configuration chains of which each parity check result in the reference configuration code stream is even check. Each configuration chain in the reference configuration code stream obtained by the data processing method has one more bit relative to the corresponding configuration chain in the initial configuration code stream, and only the reference configuration code stream with even verification can be obtained by processing.

And 3, sequentially writing the reference configuration code stream into the FPGA for storage by taking the configuration chain as a unit. As shown in fig. 3, a checker and a control circuit are integrated inside the FPGA, and the checker may be a parity checker, or when the target parity result is an even check, an even checker may be directly used. The FPGA further comprises a configuration memory, the configuration memory comprises N configuration blocks which are respectively marked as configuration blocks 1-N, the number of the configuration blocks is larger than or equal to the number of the configuration chains, the width of each configuration block is larger than or equal to the width of the configuration chains, and the widths of the configuration blocks can be the same or different and are usually the same. After the reference configuration code stream is sequentially written into the FPGA by taking the configuration chains as a unit, each configuration chain is stored in a corresponding configuration block, and fig. 3 exemplifies that the number of the configuration chains is equal to the number of the configuration blocks, and the configuration chains 1 to N are sequentially stored in the configuration blocks 1 to N. Optionally, the FPGA further includes a configuration cache, and each configuration chain in the reference configuration code stream is written into the FPGA, then written into the configuration cache for caching, and then written into a corresponding configuration block. Optionally, the FPGA further includes a decryption circuit, the configuration code stream written into the FPGA may be an encrypted configuration code stream, and after each configuration chain in the reference configuration code stream is written into the FPGA, the configuration code stream is decrypted by the decryption circuit and then written into the configuration cache for caching.

After all the reference configuration code streams are written in, in the process of normal operation of the FPGA and user design, the control circuit traverses the configuration chain stored in the FPGA every preset time, reads the configuration chain and sends the configuration chain into the checker to check whether a target parity check result exists. Optionally, the control circuit traverses all configuration chains or a part of configuration chains stored in the FPGA according to a predetermined sequence each time and sends the configuration chains or the part of configuration chains to the checker for checking. Optionally, the predetermined order of traversal is an address order of the configuration chain.

When the configuration chain is sent into the checker for checking, if the checker checks that the configuration chain has the target parity check result, the configuration chain is checked successfully, and the next configuration chain is checked continuously. If the checker checks that the configuration chain does not have the target parity check result, it indicates that the configuration chain has a check error, and in this case, the reference configuration code stream stored inside the FPGA needs to be updated by covering with the reference configuration code stream outside the FPGA, and the present application provides two mechanisms for updating by covering:

the first mechanism is to rewrite the reference configuration code stream from the exterior of the FPGA to perform full reconfiguration, that is, when the configuration chain check error exists, the full reconfiguration is immediately performed, and all the reference configuration code streams stored in the interior of the FPGA are subjected to coverage updating. Optionally, the reference configuration code stream is rewritten from outside the FPGA through the configuration port or the dynamically reconfigurable port.

And the control circuit transmits the error configuration chain address to the exterior of the FPGA, wherein the error configuration chain address is the address for checking the error configuration chain, and optionally, the control circuit transmits the error configuration chain address to the exterior of the FPGA through the configuration port or the dynamic reconfigurable port. And rewriting the configuration chain corresponding to the address of the wrong configuration chain in the reference configuration code stream from the outside of the FPGA to reconfigure the configuration chain with the error verification, namely only performing coverage updating on the configuration chain with the error verification currently, and under the condition, continuously verifying the next configuration chain after performing coverage updating on the configuration chain with the error verification.

Optionally, the FPGA further includes a timer connected to the control circuit, the control circuit traverses the configuration chain stored in the FPGA according to the delay time of the timer and sends the configuration chain into the checker for checking, and an input clock of the timer is from outside the FPGA or from inside the FPGA. When the input clock of the timer comes from the inside of the FPGA, in one embodiment, the input clock of the timer comes from a ring oscillator inside the FPGA, and the frequency of the input clock is adjustable. The delay time of the timer can be configured in a self-defined mode according to actual needs, in one embodiment, the delay time of the timer is smaller than design index parameters of the FPGA, and the design index parameters comprise at least one of Mean Time Between Failures (MTBF) and mean time before repair (MTTF), so that self-error correction can be carried out before system faults are preset. In another embodiment, in the process that the timer triggers the control circuit according to the delay time, when the timer receives an instant enable signal, the timer does not continue to calculate the delay time, but immediately triggers the control circuit to traverse the configuration chain and send the configuration chain into the checker for checking, wherein the instant enable signal is from the exterior of the FPGA or from a user design inside the FPGA.

In another embodiment, the control circuit is connected with a built-in boundary scan chain of the FPGA, and the control circuit acquires an external control signal of the FPGA through the built-in boundary scan chain, and traverses a configuration chain stored inside the FPGA according to the external control signal and sends the configuration chain into the checker for checking.