阅读说明：本技术 基于2t1m的忆阻器编程及读取电路结构和电路编程读取方法 (Memristor programming and reading circuit structure based on 2T1M and circuit programming and reading method ) 是由 张粮 童祎 冀峰 蔚仁伟 王瑞 肖建 于 2021-09-18 设计创作，主要内容包括：本发明公开了一种基于2T1M的忆阻器编程及读取电路结构和电路编程读取方法,所述电路结构的基本单元采用相对设置的两个MOS管和忆阻器相连,组成2T1M组件；第一驱动信号组{wl}、第二驱动信号组{wl-}通过连接栅极进行统一控制；通过设置时钟周期clk和ctrol-information,以及输出脉冲信号V-(s)、V-(d),实现电路中的忆阻器的定向编码、和格式化操作；同时在编程电路中设置读取电路结构,实现对忆阻器编程后信号的读取；本发明还公开了相应的电路编程方法和读取方法,同时提供了相应的电路格式化方法,弥补了由于正反相脉冲刺激导致的忆阻器性能差异,使忆阻器电路在编码过程中具备更高的稳定性。(The invention discloses a memristor programming and reading circuit structure based on 2T1M and a circuit programming and reading method, wherein a basic unit of the circuit structure is formed by connecting two MOS (metal oxide semiconductor) tubes which are oppositely arranged with a memristor to form a 2T1M component; the first driving signal group { wl }, the second driving signal group { wl- } are controlled together through the connecting grid; by setting the clock cycles clk and ctrol _ information, and the output pulse signal V s 、V d Realizing directional coding and formatting operation of the memristor in the circuit; meanwhile, a reading circuit structure is arranged in the programming circuit, so that reading of signals after programming of the memristor is realized; the invention also discloses a corresponding circuit programming method and a corresponding circuit reading method, and simultaneously provides a corresponding circuit formatting method, so that the performance difference of the memristor caused by positive and negative phase pulse stimulation is made up, and the memristor circuit has higher stability in the encoding process.)

1. A memristor programming and reading circuit structure based on 2T1M is characterized by comprising a plurality of 2T1M components, an address register address _ reg, a first driving signal group { wl }, a second driving signal group { wl- }; the address registers address _ reg respectively receive input pulse signals V_sWhen in useA clock signal clk and an output signal ctrol _ information of the control register; each 2T1M component comprises two oppositely arranged MOS tubes and a memristor, and the specific connection mode comprises the following two types:

(1) the upper T1 adopts an NMOS tube, the lower T2 adopts a PMOS tube, the non-doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

(2) the upper T1 adopts a PMOS tube, the lower T2 adopts an NMOS tube, the doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

the 2T1M elements are arranged in rows and columns, wherein each row of 2T1M elements shares a first drive sub-signal wl and a second drive sub-signal wl-; the left terminals of T1 and T2 in each column of 2T1M components share an input pulse signal, and the output ends of the memristors are connected to the pulse signal V in common_dAn input terminal of (1);

the read circuit comprises an input signal group { V }_in{ R } load group and output signal group { V }_out}; the 2T1M components of each column share a reading circuit, and the input end of each memristor M in the same column inputs a signal V_inThe output end of each memristor is connected with a load R and then grounded, and an output signal V of each memristor M is read_outAnd summarizing to obtain an output signal group { V_out}。

2. A memristor programming method based on the memristor programming and reading circuit structure of claim 1, characterized by comprising the following steps:

step S1, acquiring the memristor M adopted at V based on a pre-experiment_s-V_dAnd V_d-V_sThe change curve of the resistance value along with the time under the stimulation of two pulses;

step S2, determining a clock signal clk based on the memristor M, and setting a control register output signal ctrol _ \Addressing is inputted to address register address _ reg, a row of 2T1M elements is selected for programming, and input pulse signal V is controlled by address register address _ reg_sAnd V_d(ii) a In particular, the amount of the solvent to be used,

s2.1, when the 2T1M module selects the upper T1 to be NMOS transistor and the lower T2 to be PMOS transistor, the pulse is set in V mode during programming_s-V_dWhen formatting, the mode is set to V_d-V_s；

S2.2, when the 2T1M module selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse is set in the mode of V during programming_d-V_sWhen formatting, the mode is set to V_s-V_d；

Step S3, when encoding is started, the external driving chip controls the first driving signal group { wl }, opens all upper parts { T1} in the 2T1M assembly, controls the second driving signal group { wl- }, closes all lower parts { T2} in the 2T1M assembly; the method for setting the first driving signal group { wl } specifically comprises the following steps:

(1) when the 2T1M component selects the upper T1 to be NMOS transistor and the lower T2 to be PMOS transistor, the pulse signal is set in V mode during programming_s-V_dWhen formatting, the mode is set to V_d-V_s；

S3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max；

S3.2, acquiring time { t } from the minimum resistance state to the target resistance state { M } of the corresponding memristor according to the target resistance state { M } of the memristor needed by a specific certain column;

s3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_maxIn the case of the stimulation of the clock signal clk, the duty ratio of the driving signal wl is adjusted according to the programming time T, and T1 in 2T1M is continuously turned on;

(2) when the 2T1M component selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse signal is set as V in the programming mode_d-V_sWhen formatting, the setting mode isV_s-V_d；

L3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max-；

L3.2, acquiring time { t } of the corresponding memristor from the maximum resistance state to the target resistance state { M } according to the target resistance state { M } of the memristor required by a specific certain column;

l3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_max-Under the stimulation of an internal clock signal clk, adjusting the duty ratio of a driving signal wl in combination with a programming time T to continuously turn on T1 in 2T 1M;

step S4, providing pulse input signal V_sAnd V_dPerforming pulse stimulation on the memristor { M } in the column, and finishing directional programming on the { M };

step S5, repeating the steps L2-L4, and programming the memristors { M } in the 2T1M columns in all the columns;

step S6, after finishing programming, starting a reading circuit to obtain output signals of all 2T1M columns;

step S7, formatting the memristor { M } in the 2T1M structure in the programming circuit.

3. The memristor programming method based on memristor programming and reading circuit structure, according to claim 2, wherein the reading circuit is adopted in the step S6, and the specific method for obtaining the output signals of all 2T1M columns is as follows:

s6.1, after the programming is finished, the driving chip controls the first driving signal group { wl }, the second driving signal group { wl- } to stop working, and the pulse input signal V_sAnd V_dStopping working and disconnecting;

step S6.2 for memristor M_n-mWhere n represents the nth column and m represents the mth row, input signal V_inCorresponding to the output signal V_outThe following were used:

wherein M is_n-mRepresenting the resistance value of the memristor of the nth column and the mth row;

step S6.3, passing { V }_outAnd summarizing memristor output signals of each column by the bus to finish reading.

4. The memristor programming method based on memristor programming and reading circuit structure, according to claim 2, wherein the formatting of the memristor { M } in the 2T1M structure in the programming circuit in the step S7 comprises the following specific steps:

s7.1, the driving chip controls the middle lower part T2 of the element of the line 2T1M to be completely opened by controlling a second driving signal group { wl- }, and controls the middle upper part T1 of the element of the line 2T1M to be completely closed by controlling a first driving signal group { wl- };

s7.2, determining the maximum programming period T of each memristor M_max；

S7.2.1, when the upper T1 adopts NMOS transistor and the lower T2 adopts PMOS transistor, selecting the longest time from the minimum resistance state to the maximum resistance state in all the memristors as the period T_max(ii) a In the period T_maxIn the second driving signal group, { wl- }, pulse signal V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_d-V_sThe pulse signals continuously stimulate the memristors until all memristor resistance states return to the minimum resistance state;

s7.2.2, when the upper T1 adopts PMOS tube and the lower T2 adopts NMOS tube, the longest time from the maximum resistance state to the minimum resistance state in all the memristors is selected as the period T_max-; in the period T_max-in, all second drive signal groups { wl- }, V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_s-V_dThe pulse signals continuously stimulate the memristors until the resistance states of all the memristors return to the maximum resistance state;

s7.2.3 turning off the input pulseSignal V_sAnd V_dThe first drive signal group, { wl }, and the second drive signal group, { wl- }, are turned off and formatting is complete.

Technical Field

The invention relates to the technical field of programmable circuits, in particular to a memristor programming and reading circuit structure based on 2T1M and a circuit programming and reading method.

Background

Unlike transistors which only have high and low resistance states, memristors are ideal semiconductor devices containing abundant resistance states, and a more ideal resistance state form can be achieved in a gradual mode similar to the stimulation-formation of nerve synapses, which has a very important influence on the traditional analog circuit.

Although experimental tests show that the excellent memristor device can keep the original state under the stimulation of low-voltage pulses in recent years, due to the difference of resistance state changes of the laboratory device and the ideal device stimulated by positive and negative phase pulses and the inconvenience of massive application of the memristor circuit in an actual circuit, the actual circuit cannot operate according to the set ideal simulation circuit mode, and therefore a programmable circuit structure which can adapt to the stimulation of the positive and negative phase pulse signals and can keep the memristor resistance state relatively stable needs to be researched.

Disclosure of Invention

The purpose of the invention is as follows: aiming at the problems in the prior art, the invention provides a memristor programming and reading circuit structure based on 2T1M and a circuit programming and reading method, and designs a memristor reading-writing circuit capable of making up the performance difference of the memristor caused by positive and negative phase pulse stimulation, so that the memristor circuit has higher operability in practice, and the reading circuit is designed from the aspect of practice.

The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:

a memristor programming and reading circuit structure based on 2T1M comprises a plurality of 2T1M components, an address register address _ reg, a first driving signal group { wl }, a second driving signal group { wl- }; the address registers address _ reg respectively receive input pulse signals V_sClock signal clk and control register output signal ctrol _ information; each 2T1M component comprises two oppositely arranged MOS tubes and a memristor, and the specific connection mode comprises the following two types:

(1) the upper T1 adopts an NMOS tube, the lower T2 adopts a PMOS tube, the non-doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

(2) the upper T1 adopts a PMOS tube, the lower T2 adopts an NMOS tube, the doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

the 2T1M elements are arranged in rows and columns, wherein each row of 2T1M elements shares a first drive sub-signal wl and a second drive sub-signal wl-; the left terminals of T1 and T2 in each column of 2T1M components share an input pulse signal, and the output ends of the memristors are connected to the pulse signal V in common_dAn input terminal of (1);

the read circuit comprises an input signal group { V }_in{ R } load group and output signal group { V }_out}; the 2T1M components of each column share a reading circuit, and the input end of each memristor M in the same column inputs a signal V_inThe output end of each memristor is connected with a load R and then grounded, and an output signal V of each memristor M is read_outAnd summarizing to obtain an output signal group { V_out}。

A memristor programming method based on the memristor programming and reading circuit structure comprises the following steps:

step S1, acquiring the memristor M adopted at V based on a pre-experiment_s-V_dAnd V_d-V_sThe change curve of the resistance value along with the time under the stimulation of two pulses;

step S2, determining the clock signal clk based on the memristor M, setting the control register output signal ctrol _ initialization and inputting it to the address register address _ reg, selecting a row of 2T1M devices for programming, and controlling the input pulse signal V by the address register address _ reg_sAnd V_d(ii) a In particular, the amount of the solvent to be used,

s2.1, when the 2T1M component selects the upper T1 to adopt the NMOS tube and the lower T2 to adopt the P tubeWhen MOS tube is used, the pulse is set to V in programming mode_s-V_dWhen formatting, the mode is set to V_d-V_s；

S2.2, when the 2T1M module selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse is set in the mode of V during programming_d-V_sWhen formatting, the mode is set to V_s-V_d；

Step S3, when encoding is started, the external driving chip controls the first driving signal group { wl }, opens all upper parts { T1} in the 2T1M assembly, controls the second driving signal group { wl- }, closes all lower parts { T2} in the 2T1M assembly; the method for setting the first driving signal group { wl } specifically comprises the following steps:

(1) when the 2T1M component selects the upper T1 to be NMOS transistor and the lower T2 to be PMOS transistor, the pulse signal is set in V mode during programming_s-V_dWhen formatting, the mode is set to V_d-V_s；

S3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max；

S3.2, acquiring time { t } from the minimum resistance state to the target resistance state { M } of the corresponding memristor according to the target resistance state { M } of the memristor needed by a specific certain column;

s3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_maxIn the case of the stimulation of the clock signal clk, the duty ratio of the driving signal wl is adjusted according to the programming time T, and T1 in 2T1M is continuously turned on;

(2) when the 2T1M component selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse signal is set as V in the programming mode_d-V_sWhen formatting, the mode is set to V_s-V_d；

L3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max-；

L3.2, acquiring time { t } of the corresponding memristor from the maximum resistance state to the target resistance state { M } according to the target resistance state { M } of the memristor required by a specific certain column;

l3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_max-Under the stimulation of an internal clock signal clk, adjusting the duty ratio of a driving signal wl in combination with a programming time T to continuously turn on T1 in 2T 1M;

step S4, providing pulse input signal V_sAnd V_dPerforming pulse stimulation on the memristor { M } in the column, and finishing directional programming on the { M };

step S5, repeating the steps L2-L4, and programming the memristors { M } in the 2T1M columns in all the columns;

step S6, after finishing programming, starting a reading circuit to obtain output signals of all 2T1M columns;

step S7, formatting the memristor { M } in the 2T1M structure in the programming circuit.

Further, the specific method for acquiring the output signals of all the 2T1M columns by using the reading circuit in the step S6 is as follows:

s6.1, after the programming is finished, the driving chip controls the first driving signal group { wl }, the second driving signal group { wl- } to stop working, and the pulse input signal V_sAnd V_dStopping working and disconnecting;

step S6.2 for memristor M_n-mWhere n represents the nth column and m represents the mth row, input signal V_inCorresponding to the output signal V_outThe following were used:

wherein M is_n-mRepresenting the resistance value of the memristor of the nth column and the mth row;

step S6.3, passing { V }_outAnd summarizing memristor output signals of each column by the bus to finish reading.

Further, the step S7 of formatting the memristor { M } in the 2T1M structure in the programming circuit includes:

s7.1, the driving chip controls the middle lower part T2 of the element of the line 2T1M to be completely opened by controlling a second driving signal group { wl- }, and controls the middle upper part T1 of the element of the line 2T1M to be completely closed by controlling a first driving signal group { wl- };

s7.2, determining the maximum programming period T of each memristor M_max；

S7.2.1, when the upper T1 adopts NMOS transistor and the lower T2 adopts PMOS transistor, selecting the longest time from the minimum resistance state to the maximum resistance state in all the memristors as the period T_max(ii) a In the period T_maxIn all second drive signal groups { wl- }, V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_d-V_sThe pulse signals continuously stimulate the memristors until all memristor resistance states return to the minimum resistance state;

s7.2.2, when the upper T1 adopts PMOS tube and the lower T2 adopts NMOS tube, the longest time from the maximum resistance state to the minimum resistance state in all the memristors is selected as the period T_max-; in the period T_max-in, all second drive signal groups { wl- }, V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_s-V_dThe pulse signals continuously stimulate the memristors until the resistance states of all the memristors return to the maximum resistance state;

step S7.2.3, turning off the input pulse signal V_sAnd V_dThe first drive signal group, { wl }, and the second drive signal group, { wl- }, are turned off and formatting is complete.

Has the advantages that:

the invention firstly provides a memristor programming and reading circuit based on 2T1M, designs a novel double-MOS tube structure, can ensure that the memristor still has ideal programming characteristics when an input pulse signal is in an inverted phase, reduces the state difference of the memristor during inverted programming, has higher stability, and ensures that the memristor becomes a circuit more operable.

Meanwhile, the invention also provides a circuit reading method and a formatting method, which are used for effectively acquiring the output signal of the memristor after programming aiming at the circuit after programming is finished, and a special formatting method is adopted, so that all formatting work can be completed by one-time formatting.

Drawings

FIG. 1 is a schematic diagram of a 2T 1M-based memristor programming circuit structure provided by the present invention;

FIG. 2a is a schematic view of a 2T1M module structure when an NMOS transistor is used as the upper T1 and a PMOS transistor is used as the lower T2;

FIG. 2b is a schematic view of the structure of the 2T1M module of the present invention when the upper T1 is PMOS transistor and the lower T2 is NMOS transistor;

FIG. 3 is a memristor V provided by the present invention_s-V_dAnd V_d-V_sThe resistance value changes with time under two kinds of pulse stimulation;

FIG. 4 is a schematic diagram of an array pulse code containing 4 2T1M elements according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a read circuit according to the present invention;

FIG. 6 is a schematic diagram of a column of memristor programming circuit structures including read functionality provided by the present disclosure;

FIG. 7 is a schematic diagram of a 2T 1M-based memristor programming and reading circuit structure provided by the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

The memristor programming circuit structure based on 2T1M is shown in FIG. 1 and comprises a plurality of 2T1M components, an address register address _ reg, a first driving signal group { wl }, and a second driving signal group { wl- }. The address registers address _ reg respectively receive input signals V_sClock signal clk and control register output signal ctrol _ information.

Each 2T1M component designed by the invention comprises two MOS tubes arranged oppositely and a memristor, and the specific connection modes comprise the following two types, which are respectively shown in FIGS. 2a-2 b:

(1) the upper T1 adopts an NMOS tube, the lower T2 adopts a PMOS tube, the non-doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first set of drive signals, { wl }, and the G pole of T2 is connected to the second set of drive signals, { wl- }.

(2) The upper T1 adopts a PMOS tube, the lower T2 adopts an NMOS tube, the doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first set of drive signals, { wl }, and the G pole of T2 is connected to the second set of drive signals, { wl- }.

The memristor M is divided into a doped end and a non-doped end, wherein the non-doped end is used as a positive phase end, the high-level side is connected in the programming process of the invention, the doped end is used as an inverse phase end, and the low-level side is connected in the programming process of the invention. In (1), due to the direction problem of the pulse signal, the T2-PMOS transistor can be conducted only when the S pole is at high level and the D pole is at low level when the driving signal { wl- } is satisfied; under the condition that a corresponding T1-NMOS tube meets a driving signal { wl }, the NMOS tube can be conducted only when a D pole is at a high level and an S pole is at a low level; in (2), due to the direction problem of the pulse signal, the T1-PMOS transistor can be turned on only when the S pole is at high level and the D pole is at low level when the driving signal { wl } is satisfied; under the condition that a corresponding T2-NMOS tube meets a driving signal { wl- }, the NMOS tube can be conducted only when a D pole is at a high level and an S pole is at a low level; therefore, only one MOS transistor is in an operating state and the other MOS transistor is in an off state in the same time periods T1 and T2 in the programming process.

The 2T1M cells are arranged in rows and columns, wherein each row of 2T1M cells shares a first drive sub-signal wl and a second drive sub-signal wl-; the left terminals of T1 and T2 in each column of 2T1M components share an input pulse signal, and the output ends of the memristors are connected to the pulse signal V in common_dTo the input terminal of (1).

Memristor M adopted in the embodiment is an anion doping type memristor, and a cation doping type memristor can be adopted during actual use, and the structural adjustment is as follows:

(1) the upper T1 adopts an NMOS tube, the lower T2 adopts a PMOS tube, the doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

(2) the upper T1 adopts a PMOS tube, the lower T2 adopts an NMOS tube, the non-doping end of the memristor is connected with S poles of T1 and T2, and D poles of T1 and T2 are connected with a pulse signal output end controlled by an address register address _ reg; the G pole of T1 is connected to the first driving signal group { wl }, and the G pole of T2 is connected to the second driving signal group { wl- };

(3) the remaining programming and formatting is maintained.

Reading circuit structure as shown in fig. 5-6, each column 2T1M component shares one reading circuit, and the input end of each memristor M in the same column inputs a signal V_inThe output end of each memristor is connected with a load R and then grounded, and an output signal V of each memristor M is read_out. By extending to each column, a memristor programming circuit structure with a reading circuit can be obtained as shown in FIG. 7.

The memristor programming method is designed for the memristor programming and reading circuit structure based on 2T1M, and specifically comprises the following steps:

step S1, acquiring the memristor M adopted at V based on a pre-experiment_s-V_dAnd V_d-V_sThe resistance values under the two pulse stimuli are shown in the graph of fig. 3 along with the change of the time.

Step S1, acquiring the memristor M adopted at V based on a pre-experiment_s-V_dAnd V_d-V_sThe change curve of the resistance value along with the time under the stimulation of two pulses;

step S2, determining the clock signal clk based on the memristor M, setting the control register output signal ctrol _ initialization and inputting it to the address register address _ reg, selecting a row of 2T1M devices for programming, and controlling the input pulse signal V by the address register address _ reg_sAnd V_d(ii) a In particular, the amount of the solvent to be used,

step S2.1, when the 2T1M component is selectedWhen the upper T1 adopts NMOS transistor and the lower T2 adopts PMOS transistor, the pulse is set in V mode during programming_s-V_dWhen formatting, the mode is set to V_d-V_s。

S2.2, when the 2T1M module selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse is set in the mode of V during programming_d-V_sWhen formatting, the mode is set to V_s-V_d。

Step S3, as shown in fig. 4, when encoding is started, the external driver chip controls the first driving signal group { wl }, opens all upper portions { T1} in the 2T1M module, controls the second driving signal group { wl- }, closes all lower portions { T2} in the 2T1M module; the method for setting the first driving signal group { wl } specifically comprises the following steps:

(1) when the 2T1M component selects the upper T1 to be NMOS transistor and the lower T2 to be PMOS transistor, the pulse signal is set in V mode during programming_s-V_dWhen formatting, the mode is set to V_d-V_s；

S3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max；

S3.2, acquiring time { t } from the minimum resistance state to the target resistance state { M } of the corresponding memristor according to the target resistance state { M } of the memristor needed by a specific certain column;

s3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_maxUnder the stimulation of an internal clock signal clk, adjusting the duty ratio of a driving signal wl in combination with a programming time T to continuously turn on T1 in 2T 1M;

(2) when the 2T1M component selects the upper T1 to be PMOS tube and the lower T2 to be NMOS tube, the pulse signal is set as V in the programming mode_d-V_sWhen formatting, the mode is set to V_s-V_d；

L3.1, acquiring a maximum period T required by the memristor to be programmed in a certain column from a minimum resistance state to a maximum resistance state based on a change curve of the memristor resistance value along with time_max-；

L3.2, acquiring time { t } of the corresponding memristor from the maximum resistance state to the target resistance state { M } according to the target resistance state { M } of the memristor required by a specific certain column;

l3.3, according to the programming time T required by each memristor, in the programming period T of the memristor_max-In the case of the internal clock signal clk stimulation, the duty cycle of the driving signal wl is adjusted in conjunction with the programming time T to continuously turn on T1 in 2T 1M.

Step S4, providing pulse input signal V_sAnd V_dAnd (4) performing pulse stimulation on the memristor { M } in the column, and finishing directional programming on the { M }.

Step S5, repeating the steps L2-L4, and completing programming of the memristor { M } in the 2T1M column of all the columns.

And step S6, after the programming is finished, starting a reading circuit and acquiring output signals of all the 2T1M columns. The specific reading method is as follows:

s6.1, after the programming is finished, the driving chip controls the first driving signal group { wl }, the second driving signal group { wl- } to stop working, and the pulse input signal V_sAnd V_dStopping working and disconnecting;

step S6.2 for memristor M_n-mWhere n represents the nth column and m represents the mth row, input signal V_inCorresponding to the output signal V_outThe following were used:

wherein M is_n-mRepresenting the resistance value of the memristor of the nth column and the mth row;

step S6.3, passing { V }_outAnd summarizing memristor output signals of each column by the bus to finish reading.

Step S7, formatting the memristor { M } in the 2T1M structure in the programming circuit. In particular, the amount of the solvent to be used,

s7.1, the driving chip controls the middle lower part T2 of the element of the line 2T1M to be completely opened by controlling a second driving signal group { wl- }, and controls the middle upper part T1 of the element of the line 2T1M to be completely closed by controlling a first driving signal group { wl- };

s7.2, determining the maximum programming period T of each memristor M_max；

S7.2.1, when the upper T1 adopts NMOS transistor and the lower T2 adopts PMOS transistor, selecting the longest time from the minimum resistance state to the maximum resistance state in all the memristors as the period T_max(ii) a In the period T_maxIn the second driving signal group, { wl- }, pulse signal V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_d-V_sThe pulse signals continuously stimulate the memristors until all memristor resistance states return to the minimum resistance state;

s7.2.2, when the upper T1 adopts PMOS tube and the lower T2 adopts NMOS tube, the longest time from the maximum resistance state to the minimum resistance state in all the memristors is selected as the period T_max-; in the period T_max-in, all second drive signal groups, { wl- }, pulse signals V_sAnd V_dAll input terminals are turned on, all the first driving signal group { wl } stops driving { T1}, and V is selected_s-V_dThe pulse signals continuously stimulate the memristors until the resistance states of all the memristors return to the maximum resistance state;

step S7.2.3, turning off the input pulse signal V_sAnd V_dThe first drive signal group, { wl }, and the second drive signal group, { wl- }, are turned off and formatting is complete.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.