阅读说明：本技术 一种肖特基二极管的制作方法 (Manufacturing method of Schottky diode ) 是由 刘扬 张琦 于 2021-06-30 设计创作，主要内容包括：本发明属于半导体器件技术领域,更具体地,涉及一种肖特基二极管的制作方法。在p型区之间的肖特基接触区域引入介质层,形成MIS结构,在正向偏压下,肖特基结率先导通,同时相较于传统结势垒肖特基二极管,MIS结构耗尽区更窄,因此本发明器件具有更大的有效导通面积,能够降低器件的导通电阻,进而降低导通损耗；而在反向偏压下,MIS结构能够降低肖特基结由于势垒降低效应和隧穿效应等因素而产生的漏电流,从而提高了器件的击穿电压。(The invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a Schottky diode. A dielectric layer is introduced into a Schottky contact region between p-type regions to form an MIS structure, a Schottky junction is firstly conducted under forward bias, and meanwhile, compared with a traditional junction barrier Schottky diode, an MIS structure depletion region is narrower, so that the Schottky barrier diode has a larger effective conduction area, the conduction resistance of the Schottky barrier diode can be reduced, and the conduction loss is further reduced; under reverse bias, the MIS structure can reduce leakage current of Schottky junction caused by barrier lowering effect, tunneling effect and other factors, so as to raise breakdown voltage of the device.)

1. A manufacturing method of a Schottky diode is characterized by comprising the following steps:

s1, epitaxially growing a device drift region (2) on an n-type conductive substrate (1) through MOCVD;

s2, isolating devices through an ICP etching table board;

s3, depositing a mask layer (3) SiO on the drift region (2) of the device₂Removing SiO at the position of the p-type region (4) of the device₂A mask layer (3);

s4, injecting a p-type dopant by adopting an ion injection method, and removing SiO by using a buffered hydrofluoric acid solution after the injection is finished₂A mask layer (3) which activates doping through an annealing process to form a p-type region (4);

s5, exposing a region needing to be formed with a dielectric layer (5) through a photoetching development technology, etching the drift region (2) of the n-type device, growing the dielectric layer (5) after the etching is finished, exposing the region needing to be removed with the dielectric layer (5) through the photoetching development technology, and removing the dielectric layer (5) by using a buffer hydrofluoric acid solution;

s6, evaporating Ti/Al/Ni/Au on the substrate (1) by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode (6);

s7, evaporating Ni/Au on the front surface of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to be used as a diode anode (7).

2. The method of claim 1, wherein the step S2 specifically includes:

s21, coating photoresist on the drift region (2) of the device, and determining a mesa etching region through a photoetching development technology;

s22, etching the area uncovered by the photoresist by ICP with the depth of 0.2-10 μm.

3. The method of claim 1, wherein the step S3 specifically includes:

s31, in SiO₂Coating photoresist on the mask layer (3), and exposing a window needing to form a p-type region (4) by a photoetching development technology;

s32, removing SiO uncovered by the photoresist by using a buffered hydrofluoric acid solution₂And (3) a mask layer.

4. The method of claim 1, wherein the step S5 specifically includes:

s511, coating photoresist on the device formed in the step S4, and opening a window of a region needing to form the dielectric layer (5) through a photoetching development technology;

s512, etching the n-type drift region through ICP, and removing the photoresist after etching is finished;

s513, growing a dielectric layer (5) on the formed device in the step S512, and filling the groove;

s514, coating photoresist, and exposing the area needing to remove the dielectric layer (5) through a photoetching development technology;

and S515, removing the dielectric layer (5) which is not covered by the photoresist by using a buffered hydrofluoric acid solution.

5. The method of claim 4, wherein the dielectric layer (5) in the mesa region is not removed in step S5 to form a field plate structure.

6. The method of claim 5, wherein in step S5, the dielectric layer (5) is directly grown without performing ICP etching, and then the region of the dielectric layer (5) to be removed is exposed by photolithography and development technique, and is easily removed by buffered hydrofluoric acid.

7. The method for manufacturing the Schottky diode according to any one of claims 1 to 6, wherein the substrate (1), the device drift region (2) and the p-type region (4) are made of the same material and are all Si, SiC or GaN; the dielectric layer (5) is made of Al₂O₃、SiN、SiO₂、HfO₂Any of them, the thickness is 10nm to 500 nm.

8. The method for manufacturing the schottky diode according to claim 7, wherein the substrate (1) is an n-type conductive substrate (1), the resistivity of the substrate (1) ranges from 0.005 Ω -cm to 0.1 Ω -cm, and the thickness ranges from 100 μm to 500 μm; the p-type region (4) has a hole concentration of 1 × 10¹⁶cm^-3～1×10¹⁹cm^-3The thickness is 0.1-20 μm.

9. The method for manufacturing the schottky diode as described in claim 7, wherein the device drift region (2) is an unintentionally doped epitaxial layer or an n-type doped epitaxial layer with low dislocation density; the thickness of the drift region (2) of the device is 1-50 μm, and the carrier concentration is 1 x 10¹⁴cm^-3～5×10¹⁷cm^-3。

10. The method for manufacturing the Schottky diode according to claim 7, wherein the material of the diode cathode (6) is any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy, or Ti/Al/Ti/TiN alloy; the anode (7) of the diode is made of one of metal Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a Schottky diode.

Background

Schottky diodes are widely used in power supplies, driving circuits, and other fields because of their characteristics of low turn-on voltage and high switching speed. However, the schottky diode has barrier lowering effect, tunneling effect and other factors under reverse bias voltage, so that the reverse leakage current of the device increases with the increase of the reverse bias voltage, and the larger leakage current further causes the device to have smaller breakdown voltage.

One commonly used device structure is a junction barrier schottky diode in order to increase the breakdown voltage of the schottky diode and reduce leakage current. The n-type drift layer of the junction barrier Schottky diode is provided with p-type regions distributed in a grid shape, the Schottky junction is firstly conducted under forward bias, and a formed pn junction depletion region gradually extends under reverse bias to pinch off a conduction channel, so that the peak electric field at the interface of the Schottky junction is reduced. Therefore, the junction barrier Schottky diode can keep the advantage of low turn-on voltage of the Schottky junction, and can reduce reverse leakage current and improve the breakdown voltage of the device.

As shown in fig. 1, which is a schematic diagram of a junction barrier schottky diode cell structure, simulation of the device structure shows that the electric field intensity along the boundary of schottky contact reaches the highest at the middle position in an n-type channel region between p-type regions, and increases with the increase of reverse bias, as shown in fig. 2. While the reverse leakage current of the schottky junction is related to the electric field strength at the contact interface, a higher electric field strength will result in a larger reverse leakage current and a smaller breakdown voltage of the device.

In the junction barrier Schottky diode, if a larger p-type region interval is adopted, the device can have a larger forward conduction effective area, so that the on-resistance of the device is reduced, and the conduction loss is reduced. However, the larger p-type interval distance can generate a relatively higher electric field on the surface of the Schottky junction, so that larger reverse leakage current is generated, and the breakdown voltage of the device is reduced. If a certain device area is kept, the p-type region interval is reduced, although the surface electric field of the Schottky junction can be reduced, and the reverse leakage current of the device is reduced, the forward conduction effective area of the device is reduced, so that larger on-resistance is generated, and the on-loss of the device is increased. On the other hand, the smaller p-type region spacing also increases the process difficulty of the device.

Disclosure of Invention

The present invention provides a method for manufacturing a schottky diode, which has a low turn-on voltage and a low conduction loss when the device is conducted in the forward direction, and has a low leakage current and a high breakdown voltage when the device is conducted in the reverse direction.

In order to solve the technical problems, the invention adopts the technical scheme that: a manufacturing method of a Schottky diode comprises the following steps:

s1, epitaxially growing a device drift region on an n-type conductive substrate through MOCVD;

s2, isolating devices through an ICP etching table board;

s3, depositing a mask layer SiO on the drift region of the device₂Removing SiO at the position of p-type region to be formed₂A mask layer;

s4, injecting a p-type dopant by adopting an ion injection method, and removing SiO by using a buffered hydrofluoric acid solution after the injection is finished₂The mask layer activates doping through an annealing process to form a p-type region;

s5, exposing a region of the medium layer to be formed through a photoetching development technology, etching a drift region of the n-type device, growing the medium layer after the etching is finished, exposing the region of the medium layer to be removed through the photoetching development technology, and removing the medium layer without photoresist coverage by using a buffered hydrofluoric acid solution;

s6, evaporating Ti/Al/Ni/Au on the substrate by adopting an electron beam evaporation method or a magnetron sputtering method to form an ohmic contact electrode as a diode cathode;

and S7, evaporating Ni/Au on the front surface of the device by adopting an electron beam evaporation method or a magnetron sputtering method to form a Schottky electrode, and selectively leaving the electrode by adopting a stripping method to serve as the anode of the diode.

In one embodiment, the step S2 specifically includes:

s21, coating photoresist on the drift region of the device, and determining a mesa etching region through a photoetching development technology;

s22, etching the area uncovered by the photoresist by ICP with the depth of 0.2-10 μm.

In one embodiment, the step S3 specifically includes:

s31, in SiO₂Coating photoresist on the mask layer, and exposing a window in which a p-type region is required to be formed by a photoetching development technology;

s32, removing SiO uncovered by the photoresist by using a buffered hydrofluoric acid solution₂And (5) masking the layer.

In one embodiment, the step S5 specifically includes:

s511, coating photoresist on the device formed in the step S4, and opening a window of a medium layer region to be formed through a photoetching development technology;

s512, etching the n-type drift region through ICP, and removing the photoresist after etching is finished;

s513, growing a dielectric layer on the formed device in the step S512, and filling the groove;

s514, coating photoresist, and exposing the area needing to remove the dielectric layer through a photoetching development technology;

and S515, removing the dielectric layer which is not covered by the photoresist by using a buffered hydrofluoric acid solution.

In one embodiment, the dielectric layer in the mesa region is not removed in step S5 to form a field plate structure. The electric field concentration effect of the edge of the electrode of the device under reverse bias can be relieved, and the breakdown voltage of the device is improved.

In one embodiment, in the step S5, the ICP etching is not performed to form the groove, the dielectric layer is directly grown, and then the region of the dielectric layer to be removed is exposed by the photolithography and development technique and is removed by using a buffered hydrofluoric acid solution.

In one embodiment, the substrate, the device drift region and the p-type region are made of the same material and are all Si, SiC or GaN; the dielectric layer is made of Al₂O₃、SiN、SiO₂、HfO₂Any of them, the thickness is 10nm to 500 nm.

In one embodiment, the substrate is an n-type conductive substrate, the substrate resistivity ranges from 0.005 Ω -cm to 0.1 Ω -cm, and the thickness ranges from 100 μm to 500 μm; the p-type region has a hole concentration of 1 × 10¹⁶cm^-3～1×10¹⁹cm^-3The thickness is 0.1-20 μm.

In one embodiment, the device drift region is an unintentional doped epitaxial layer or an n-type doped epitaxial layer with low dislocation density; the thickness of the drift region of the device is 1-50 μm, and the carrier concentration is 1 × 10¹⁴cm^-3～5×10¹⁷cm^-3。

In one embodiment, the cathode of the diode is made of any one of Ti/Al/Ni/Au alloy, Ti/Al/Ti/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/TiN alloy; the anode of the diode is made of one of metal Ni, Au, Pt, Pd, Ir, Mo, Al, Ti, TiN, Ta, TaN, ZrN, VN and NbN or a stacked structure thereof.

Compared with the prior art, the beneficial effects are: according to the manufacturing method of the Schottky diode, the dielectric layer is introduced into the Schottky contact region between the p-type regions to form the MIS structure, the Schottky junction is conducted firstly under forward bias, and meanwhile, compared with the traditional junction barrier Schottky diode, the MIS structure depletion region is narrower, so that the Schottky diode has a larger effective conduction area, the conduction resistance of the Schottky diode can be reduced, and the conduction loss is further reduced; under reverse bias, the MIS structure can reduce leakage current of Schottky junction caused by barrier lowering effect, tunneling effect and other factors, so as to raise breakdown voltage of the device.

Drawings

FIG. 1 is a schematic diagram of a structure of a junction barrier Schottky diode analog simulation device.

Fig. 2 is a distribution of electric field strength along the schottky contact interface.

Fig. 3 is a schematic diagram of the current distribution of the device of the present invention and a conventional junction barrier schottky diode under forward bias.

Fig. 4 to 8 are schematic views of processes of the device according to embodiment 1 of the present invention, wherein fig. 8 is a schematic view of an overall structure of the device according to embodiment 1.

Fig. 9 to 10 are schematic views of processes of a device according to embodiment 2 of the present invention, wherein fig. 10 is a schematic view of an overall structure of the device according to embodiment 2.

Fig. 11 to 12 are schematic views of processes of a device according to embodiment 3 of the present invention, wherein fig. 12 is a schematic view of an overall structure of the device according to embodiment 3.

Description of the drawings: 1. a substrate; 2. a device drift region; 3. a mask layer; 4. a p-type region; 5. a dielectric layer; 6. a diode cathode; 7. and an anode of the diode.

Detailed Description

The drawings are for illustration purposes only and are not to be construed as limiting the invention; for the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted. The positional relationships depicted in the drawings are for illustrative purposes only and are not to be construed as limiting the invention.

Example 1:

as shown in fig. 8, is a schematic view of the overall structure of the device of this embodiment, and the structure thereof sequentially includes, from bottom to top: an ohmic contact electrode-diode cathode 6 covering the substrate 1; a substrate 1; n-type low carrier concentration region-device drift region 2; p-type regions 4 staggered in the device drift region 2; a dielectric layer 5 between the drift region 2 of the n-type device and the p-type region; an electrode forming a schottky contact with the device drift region 2-a diode anode 7.

The manufacturing method of the schottky diode provided by the embodiment comprises the following steps:

step 1.1 epitaxial Structure

And (3) extending an n-type conductive device drift region 2 on an n-type low-resistivity substrate 1, wherein the material epitaxial structure is shown in figure 4 after the step is completed.

Step 1.2 device isolation

S21, coating photoresist on the drift region 2 of the n-type conductive device, and exposing a region to be etched after exposure and development;

s22, etching the area which is not covered by the photoresist through ICP;

and S23, removing the photoresist by using acetone.

Step 1.3. preparation of mask layer 3

S31, depositing SiO on the drift region 2 of the device₂As a mask layer 3;

s32, in SiO₂Coating photoresist on the mask layer 3, exposing and developing to form a p-type region 4;

and S33, selectively etching the mask layer 3 which is not covered by the photoresist by using a buffer hydrofluoric acid solution, wherein the structure of the finished device is shown in FIG. 5.

Step 1.4 Selective area doping

S41, injecting a p-type dopant into the area which is not covered by the mask layer 3 by adopting an ion injection method;

s42, removing the photoresist by using acetone;

s43, removing SiO by using buffer hydrofluoric acid solution₂A mask layer 3;

and S44, activating doping through an annealing process to form a p-type region 4, wherein the completed structure is shown in FIG. 6.

Step 1.5. growing a dielectric layer 5

S51, coating photoresist on the device, exposing and developing to expose an area needing to form the dielectric layer 5;

s52, etching the area which is not covered by the photoresist through ICP, and removing the photoresist by using acetone after the etching is finished;

s53, placing the device into a chamber to grow a medium layer 5;

s54, coating photoresist on the dielectric layer 5, exposing and developing to expose an area where the dielectric layer 5 needs to be removed;

s55, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;

s56, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 7.

Step 1.6 electrode Evaporation

S61, evaporating Ti/Al/Ni/Au on the back surface of the device formed in the step S5 to form ohmic contact to serve as a diode cathode 6;

s62, coating photoresist on the front side of the device formed in the step S61, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 of the device, and forming an anode 7 of the diode after stripping;

s63, the process flow of the embodiment 1 is completed, and the final device structure is shown in FIG. 8.

Example 2

Fig. 10 shows a schematic diagram of the overall structure of the device of this embodiment, which is different from embodiment 1 in that the dielectric layer 5 of the mesa region of the device is retained in this embodiment 2, so as to form a field plate structure. The process of this embodiment is similar to that of embodiment 1, and after the growth of the dielectric layer 5 is completed in embodiment 1, the dielectric layer 5 in the mesa region of the device is covered by the photoresist and is not etched by the buffered hydrofluoric acid solution by modifying the lithographic layout, so as to form the structure shown in fig. 9. After the electrodes are evaporated, the overall structure of the device of this example is formed, as shown in fig. 10.

Example 3

Fig. 12 shows an overall structural schematic diagram of the device in this embodiment, and compared with embodiment 2, the difference is that in embodiment 2, a groove is etched in the n-type device drift region 2, and then a dielectric layer 5 is grown to fill the groove, and in this embodiment 3, the dielectric layer 5 is directly grown without etching the groove. After completing the selective region doping in embodiment 2 and forming the p-type region 4, the following steps are performed in this embodiment:

step 3.1. growing a dielectric layer 5

S11, placing the device into a chamber to grow a medium layer 5;

s12, coating photoresist on the dielectric layer 5, exposing and developing to expose an area where the dielectric layer 5 needs to be removed;

s13, selectively etching the dielectric layer 5 which is not covered by the photoresist by using a buffer hydrofluoric acid solution;

s14, removing the photoresist by using acetone, wherein the finished structure is shown in FIG. 11.

Step 3.2 electrode Evaporation

S21, evaporating Ti/Al/Ni/Au on the back surface of the device formed in the step 3.1 to form ohmic contact to serve as a diode cathode 6;

s22, coating photoresist on the front side of the device formed in the step S21, evaporating Ni/Au after exposure and development, forming Schottky contact with the drift region 2 of the device, and forming an anode 7 of the diode after stripping;

s23, the process flow of the embodiment 3 is completed, and the final device structure is shown in FIG. 12.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.