阅读说明：本技术 半导体结构的形成方法 (Method for forming semiconductor structure ) 是由 赵炳贵 于 2020-05-12 设计创作，主要内容包括：一种半导体结构的形成方法,包括：在所述介质层内形成若干第一开口,各所述第一开口底部均暴露出一个第一源漏掺杂区顶部表面；在所述介质层内形成若干第二开口,各所述第二开口底部均暴露出一个第一栅极结构顶部的部分表面；在所述介质层内形成若干第三开口,所述第三开口底部高于所述第一栅极层顶部表面,所述第三开口分别与所述第一开口以及第二开口相连通。所述方法能够减少不同制程之间互相造成影响,使得形成的半导体结构的性能较好。(A method of forming a semiconductor structure, comprising: forming a plurality of first openings in the dielectric layer, wherein the bottom of each first opening is exposed out of the top surface of one first source drain doped region; forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening is exposed out of part of the surface of the top of one first grid structure; and forming a plurality of third openings in the dielectric layer, wherein the bottoms of the third openings are higher than the top surface of the first gate layer, and the third openings are respectively communicated with the first openings and the second openings. The method can reduce the mutual influence between different processes, so that the formed semiconductor structure has better performance.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate comprising a dense region;

forming a plurality of first gate structures positioned on the substrate, a plurality of first source-drain doped regions positioned in the substrate and a dielectric layer positioned on the substrate, wherein the first gate structures are positioned on the dense region, each first gate structure comprises a first gate layer, the substrate on two sides of each first gate structure is respectively provided with a first source-drain doped region, and the dielectric layer is positioned on the surface of each first gate structure and the surface of each first source-drain doped region;

forming a plurality of first openings in the dielectric layer, wherein the bottom of each first opening is exposed out of the top surface of one first source drain doped region;

forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening is exposed out of part of the surface of the top of one first grid structure;

and forming a plurality of third openings in the dielectric layer, wherein the bottoms of the third openings are higher than the top surface of the first gate layer, and the third openings are respectively communicated with the first openings and the second openings.

2. The method of forming a semiconductor structure of claim 1, wherein the second opening is formed after the first opening is formed.

3. The method of forming a semiconductor structure of claim 1, wherein the substrate further comprises a sparse region; the substrate is also provided with a plurality of second grid structures and a plurality of second source-drain doped regions positioned in the substrate, the second grid structures are positioned on the dense region, each second grid structure comprises a second grid layer, and the substrate on two sides of each second grid structure is respectively provided with a second source-drain doped region; the dielectric layer is positioned on the surface of the second grid structure and the surface of the second source-drain doped region.

4. The method of forming a semiconductor structure of claim 3, further comprising: forming a plurality of fourth openings in the dielectric layer, wherein the bottom of each fourth opening is exposed out of the top surface of one second source-drain doped region; forming a plurality of fifth openings in the dielectric layer, wherein the bottom of each fifth opening is exposed out of part of the surface of the top of the second gate structure, and the fourth openings and the fifth openings are separated from each other; and forming a plurality of sixth openings in the dielectric layer, wherein the bottoms of the sixth openings are higher than the top surface of the second gate layer, and the sixth openings are respectively communicated with the fourth openings and the fifth openings.

5. The method of forming a semiconductor structure according to claim 4, wherein the first opening and the fourth opening are formed simultaneously; the second opening and the fifth opening are formed simultaneously; the third opening and the sixth opening are formed simultaneously.

6. The method of forming a semiconductor structure of claim 5, wherein the method of forming the first opening and the fourth opening comprises: forming a first graphical layer on the surface of the dielectric layer, wherein the first graphical layer exposes the surface of the dielectric layer on the first source-drain doped region and the second source-drain doped region; and etching the dielectric layer by taking the first patterning layer as a mask until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, forming the first opening in the dense region, and forming the fourth opening in the sparse region.

7. The method of forming a semiconductor structure of claim 5, wherein the second opening and the fifth opening are formed by a method comprising: forming a second patterning layer on the dielectric layer, wherein the second patterning layer exposes the surface of the dielectric layer on the first grid structure and the second grid structure; and etching the dielectric layer by taking the second patterning layer as a mask until the top surfaces of the first gate structure and the second gate structure are exposed, forming the second opening in the dense area, and forming the fifth opening in the sparse area.

8. The method of forming a semiconductor structure of claim 1, further comprising: after the first opening is formed and before the second opening is formed, a first planarization layer is formed in the first opening and on the surface of the dielectric layer; the second patterned layer is positioned on the surface of the first planarization layer; after the second opening is formed, the first planarization layer is removed.

9. The method of forming a semiconductor structure of claim 8, wherein a material of the first planarizing layer and a material of the dielectric layer are different.

10. The method of forming a semiconductor structure of claim 9, wherein a material of the first planarization layer comprises: a carbon-oxygen containing organic material.

11. The method of forming a semiconductor structure of claim 5, wherein the method of forming the third opening and the sixth opening comprises: forming a third patterned layer on the dielectric layer, wherein the third patterned layer exposes the surface of the dielectric layer between the first opening and the second opening and the surface of the dielectric layer between the fourth opening and the fifth opening; and etching the dielectric layer by taking the third patterning layer as a mask, forming a third opening in the dense area, and forming a sixth opening in the sparse area.

12. The method of forming a semiconductor structure of claim 11, further comprising: after the second opening is formed and before the third opening is formed, forming a second planarization layer on the first opening, the second opening and the surface of the dielectric layer; the third patterned layer is positioned on the surface of the second planarization layer; after the third opening is formed, the second planarization layer is removed.

13. The method of forming a semiconductor structure of claim 12, wherein a material of the second planarization layer and a material of the dielectric layer are different.

14. The method of forming a semiconductor structure of claim 13, wherein a material of the second planarization layer comprises: a carbon-oxygen containing organic material.

15. The method of forming a semiconductor structure of claim 1, wherein an aspect ratio of the third opening ranges from 2: 9 to 8: 3.

16. the method of claim 3, wherein a distance between adjacent first gate structures is less than a distance between adjacent second gate structures.

17. The method of claim 1, wherein the substrate comprises a substrate and a plurality of fins on a surface of the substrate, the first gate structure spans the plurality of fins, and the first gate structure covers a portion of top surfaces and sidewall surfaces of the fins; the first source-drain doped region is located in the fin portions on two sides of the first grid structure.

18. The method of claim 5, wherein the forming of the first patterned layer comprises: an extreme ultraviolet lithography process; the forming process of the second patterning layer comprises the following steps: an extreme ultraviolet lithography process; the forming process of the third patterning layer comprises the following steps: and (4) carrying out an extreme ultraviolet photoetching process.

19. The method of forming a semiconductor structure of claim 1, further comprising: and filling a conductive material in the first opening, the second opening and the third opening to form a conductive structure.

20. The method of forming a semiconductor structure of claim 1, wherein the dielectric layer comprises: the dielectric layer comprises a first dielectric layer, an etching stop layer positioned on the surface of the first dielectric layer, and a second dielectric layer positioned on the surface of the etching stop layer.

21. The method of forming a semiconductor structure of claim 20, wherein the first gate structure further comprises: the first grid dielectric layer is positioned at the bottom of the first grid electrode layer, and the first barrier layer is positioned on the top surface of the first grid dielectric layer and the top surface of the first grid electrode layer.

22. The method for forming the semiconductor structure according to claim 21, wherein the method for forming the first gate structure, the first source-drain doped region, and the dielectric layer comprises: forming a first pseudo gate structure on the substrate; forming a first source drain doped region in the substrate at two sides of the first pseudo gate structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is positioned on the surface of the first pseudo gate structure and the surface of the first source-drain doped region; removing the first pseudo gate structure, and forming a first pseudo gate opening in the first dielectric layer; forming a first gate dielectric layer, a first gate layer positioned on the surface of the first gate dielectric layer and a first barrier layer positioned on the top surface of the first gate dielectric layer and the top surface of the first gate layer in the first dummy gate opening; forming an etching stop layer on the surface of the first barrier layer and the surface of the first dielectric layer; and forming the second dielectric layer on the surface of the etching stop layer.

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a forming method of a semiconductor structure.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are widely used as the most basic semiconductor devices, and the conventional planar devices have weak control capability on channel current, short channel effect is generated, leakage current is caused, and finally the electrical performance of the semiconductor devices is affected.

In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structures are positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source and drain doped regions are positioned in the fin parts at two sides of the grid structure.

However, when the source-drain doped region and the gate structure are electrically connected to a peripheral circuit through a common plug, the performance of the conventional semiconductor structure is poor.

Disclosure of Invention

The invention provides a method for forming a semiconductor structure, which improves the performance of the formed semiconductor structure.

To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a dense region; forming a plurality of first gate structures positioned on the substrate, a plurality of first source-drain doped regions positioned in the substrate and a dielectric layer positioned on the substrate, wherein the first gate structures are positioned on the dense region, each first gate structure comprises a first gate layer, the substrate on two sides of each first gate structure is respectively provided with a first source-drain doped region, and the dielectric layer is positioned on the surface of each first gate structure and the surface of each first source-drain doped region; forming a plurality of first openings in the dielectric layer, wherein the bottom of each first opening is exposed out of the top surface of one first source drain doped region; forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening is exposed out of part of the surface of the top of one first grid structure; and forming a plurality of third openings in the dielectric layer, wherein the bottoms of the third openings are higher than the top surface of the first gate layer, each third opening is positioned between the adjacent first opening and the second opening, and the third openings are respectively communicated with the first openings and the second openings.

Optionally, after the first opening is formed, the second opening is formed.

Optionally, the substrate further comprises a sparse region; the substrate is also provided with a plurality of second grid structures and a plurality of second source-drain doped regions positioned in the substrate, the second grid structures are positioned on the dense region, each second grid structure comprises a second grid layer, and the substrate on two sides of each second grid structure is respectively provided with a second source-drain doped region; the dielectric layer is positioned on the surface of the second grid structure and the surface of the second source-drain doped region.

Optionally, the method further includes: forming a plurality of fourth openings in the dielectric layer, wherein the bottom of each fourth opening is exposed out of the top surface of one second source-drain doped region; forming a plurality of fifth openings in the dielectric layer, wherein the bottom of each fifth opening is exposed out of part of the surface of the top of the second gate structure, and the fourth openings and the fifth openings are separated from each other; and forming a plurality of sixth openings in the dielectric layer, wherein the bottoms of the sixth openings are higher than the top surface of the second gate layer, each sixth opening is positioned between adjacent fourth openings and fifth openings, and the sixth openings are respectively communicated with the fourth openings and the fifth openings.

Optionally, the first opening and the fourth opening are formed at the same time; the second opening and the fifth opening are formed simultaneously; the third opening and the sixth opening are formed simultaneously.

Optionally, the method for forming the first opening and the fourth opening includes: forming a first graphical layer on the surface of the dielectric layer, wherein the first graphical layer exposes the surface of the dielectric layer on the first source-drain doped region and the second source-drain doped region; and etching the dielectric layer by taking the first patterning layer as a mask until the top surfaces of the first source-drain doped region and the second source-drain doped region are exposed, forming the first opening in the dense region, and forming the fourth opening in the sparse region.

Optionally, the method for forming the second opening and the fifth opening includes: forming a second patterning layer on the dielectric layer, wherein the second patterning layer exposes the surface of the dielectric layer on the first grid structure and the second grid structure; and etching the dielectric layer by taking the second patterning layer as a mask until the top surfaces of the first gate structure and the second gate structure are exposed, forming the second opening in the dense area, and forming the fifth opening in the sparse area.

Optionally, the method further includes: after the first opening is formed and before the second opening is formed, a first planarization layer is formed in the first opening and on the surface of the dielectric layer; the second patterned layer is positioned on the surface of the first planarization layer; after the second opening is formed, the first planarization layer is removed.

Optionally, a material of the first planarization layer is different from a material of the dielectric layer.

Optionally, the material of the first planarizing layer includes: a carbon-oxygen containing organic material.

Optionally, the forming method of the third opening and the sixth opening includes: forming a third patterned layer on the dielectric layer, wherein the third patterned layer exposes the surface of the dielectric layer between the first opening and the second opening and the surface of the dielectric layer between the fourth opening and the fifth opening; and etching the dielectric layer by taking the third patterning layer as a mask, forming a third opening in the dense area, and forming a sixth opening in the sparse area.

Optionally, the method further includes: after the second opening is formed and before the third opening is formed, forming a second planarization layer on the first opening, the second opening and the surface of the dielectric layer; the third patterned layer is positioned on the surface of the second planarization layer; after the third opening is formed, the second planarization layer is removed.

Optionally, a material of the second planarization layer is different from a material of the dielectric layer.

Optionally, the material of the second planarization layer includes: a carbon-oxygen containing organic material.

Optionally, the depth-to-width ratio range of the third opening is 2: 9 to 8: 3.

optionally, a distance between adjacent first gate structures is smaller than a distance between adjacent second gate structures.

Optionally, the substrate includes a substrate and a plurality of fin portions located on a surface of the substrate, the first gate structure crosses over the plurality of fin portions, and the first gate structure covers a portion of a top surface and a sidewall surface of the fin portions; the first source-drain doped region is located in the fin portions on two sides of the first grid structure.

Optionally, the forming process of the first patterning layer includes: an extreme ultraviolet lithography process; the forming process of the second patterning layer comprises the following steps: an extreme ultraviolet lithography process; the forming process of the third patterning layer comprises the following steps: and (4) carrying out an extreme ultraviolet photoetching process.

Optionally, the method further includes: and filling a conductive material in the first opening, the second opening and the third opening to form a conductive structure.

Optionally, the dielectric layer includes: the dielectric layer comprises a first dielectric layer, an etching stop layer positioned on the surface of the first dielectric layer, and a second dielectric layer positioned on the surface of the etching stop layer.

Optionally, the first gate structure further includes: the first grid dielectric layer is positioned at the bottom of the first grid electrode layer, and the first barrier layer is positioned on the top surface of the first grid dielectric layer and the top surface of the first grid electrode layer.

Optionally, the method for forming the first gate structure, the first source-drain doped region, and the dielectric layer includes: forming a first pseudo gate structure on the substrate; forming a first source drain doped region in the substrate at two sides of the first pseudo gate structure; forming a first dielectric layer on the substrate, wherein the first dielectric layer is positioned on the surface of the first pseudo gate structure and the surface of the first source-drain doped region; removing the first pseudo gate structure, and forming a first pseudo gate opening in the first dielectric layer; forming a first gate dielectric layer, a first gate layer positioned on the surface of the first gate dielectric layer and a first barrier layer positioned on the top surface of the first gate dielectric layer and the top surface of the first gate layer in the first dummy gate opening; forming an etching stop layer on the surface of the first barrier layer and the surface of the first dielectric layer; and forming the second dielectric layer on the surface of the etching stop layer.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, the first opening exposing the top surface of the first source-drain doped region, the second opening exposing the top surface of the first grid structure and the third opening positioned between the adjacent first opening and the second opening are formed in different processes. The third opening is respectively communicated with the first opening and the second opening, so that the third opening can connect the first opening and the second opening, the subsequent conductive structures formed in the first opening, the second opening and the third opening can be electrically connected with the first grid structure and the first source drain doped region at the same time, and the process requirements are met. Meanwhile, the first opening, the second opening and the third opening are completed in three different etching processes, so that the influence caused by different processes can be reduced, the bottom of the third opening is higher than the top surface of the first grid layer, and the over-etching of a first source drain doped region at the bottom of the first opening in the process of forming the third opening can be avoided, so that the leakage current generated between the first grid structure and the substrate is reduced, and the performance of the formed semiconductor structure is better.

Furthermore, the substrate further comprises a sparse region, a second gate structure is arranged on the sparse region, and second source-drain doped regions are respectively arranged in the substrate on two sides of the second gate structure. The first opening and the fourth opening are formed simultaneously, the second opening and the fifth opening are formed simultaneously, the third opening and the sixth opening are formed simultaneously, the first opening and the fourth opening are formed in the dense area and the sparse area, the second opening, the fifth opening, the third opening and the sixth opening are completed in different processes, and therefore influences on different processes are reduced.

Drawings

FIGS. 1-4 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;

fig. 5 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Detailed Description

First, the reason for the poor performance of the conventional semiconductor structure will be described in detail with reference to the accompanying drawings, in which fig. 1 to 4 are schematic structural diagrams of steps of a conventional semiconductor structure forming method.

Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a dense region a and a sparse region B, the dense region a has a plurality of first gate structures 111, first source-drain doped regions 121 are respectively disposed in the substrate 100 at two sides of the first gate structures 111, the sparse region B has a plurality of second gate structures 112, and second source-drain doped regions 122 are respectively disposed in the substrate 100 at two sides of the second gate structures 112.

Referring to fig. 2, a dielectric layer 130 is formed on the substrate 100, and the dielectric layer 130 is located on the surfaces of the first gate structure 111, the first source-drain doped region 121, the second gate structure 112, and the second source-drain doped region 122.

Referring to fig. 3, a plurality of first openings 141 and second openings 142 are formed in the dielectric layer 130, a top surface of the first source/drain doped region 121 is exposed at the bottom of each first opening 141, and a top surface of the second source/drain doped region 122 is exposed at the bottom of each second opening 142.

Referring to fig. 4, after the first opening 141 and the second opening 142 are formed, a third opening 151 exposing the top surface of the first gate structure 111 and a fourth opening 152 exposing the top surface of the second gate structure 112 are formed in the dielectric layer 130, the third opening 151 is overlapped with a portion of the first opening 141, and the fourth opening 152 is overlapped with a portion of the second opening 142.

In the above method, the third opening 151 is overlapped with a part of the first opening 141, and the fourth opening 152 is overlapped with a part of the second opening 142, so that plugs formed in the first opening 141 and the third opening 151 can be electrically connected to the first source/drain doping region 121 and the first gate structure 111 at the same time, and plugs formed in the second opening 142 and the fourth opening 152 can be electrically connected to the second source/drain doping region 122 and the second gate structure 112 at the same time, thereby meeting specific process requirements.

However, the conventional method for forming the third opening 151 and the fourth opening 152 includes: forming a planarization layer (not shown) on the first and second openings 141 and 142 and the dielectric layer surface 130; forming a patterning layer (not shown) on the planarization layer surface, wherein the patterning layer exposes the planarization layer surface on the first opening 141 and the first gate structure 111 on the dense region a, the dielectric layer 130 between the adjacent first opening 141 and the first gate structure 111, and the planarization layer surface on the second opening 142 and the second gate structure 112 on the sparse region B, the dielectric layer 130 between the adjacent second opening 142 and the second gate structure 112; and etching the dielectric layer 130 and the planarization layer by using the patterning layer as a mask until the top surfaces of the first gate structure 111 and the second gate structure 112 are exposed, forming the third opening 151 in the dense region a, and forming the fourth opening 152 in the sparse region B.

Since the device density of the dense region a is greater than that of the sparse region B, so that the thicknesses of the planarization layers filled in the first opening 141 and the second opening 142 and higher than the surface of the dielectric layer 130 are different between the dense region a and the sparse region B, specifically, the thickness of the planarization layer on the dense region a is less than that of the planarization layer on the sparse region B, and in the process of forming the third opening 151 and the fourth opening 152 by etching the dielectric layer 130 and the planarization layer, in order to satisfy the requirement that the fourth opening 152 located in the sparse region B can expose the top surface of the second gate structure 112, the dense region a with the thinner planarization layer is easily over-etched, further, the first source-drain doped region 121 at the bottom of the first opening 141 is easily damaged by etching, so that a leakage current is generated between the first gate structure 111 and the substrate 100, which affects the power consumption of the device and is not beneficial to the performance of the semiconductor structure.

In order to solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, where a plurality of first openings are formed in a dielectric layer, and a top surface of a first source/drain doped region is exposed at a bottom of each first opening; forming a plurality of second openings in the dielectric layer, wherein the bottom of each second opening is exposed out of part of the surface of the top of one first grid structure; and forming a plurality of third openings in the dielectric layer, wherein the bottoms of the third openings are higher than the top surface of the first gate layer, and the third openings are respectively communicated with the first openings and the second openings. The first opening, the second opening and the third opening are completed in three different etching processes, so that the mutual influence among different processes can be reduced, and the performance of the formed semiconductor structure is better.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 5 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.

Referring to fig. 5, a substrate 200 is provided, wherein the substrate 200 includes a dense region a.

In this embodiment, the substrate 200 further includes: and a sparse region B.

The substrate 200 includes a substrate and a plurality of fins on the surface of the substrate.

In other embodiments, the substrate does not have fins thereon.

In this embodiment, the method for forming the substrate 200 includes: providing an initial substrate (not shown); the initial substrate is provided with a mask layer, and the mask layer exposes part of the surface of the initial substrate; and etching the initial substrate by taking the mask layer as a mask to form a substrate and a fin part positioned on the surface of the substrate.

In this embodiment, the material of the initial substrate is silicon. Correspondingly, the material of the substrate and the fin portion is silicon.

In other embodiments, the material of the initial substrate comprises: germanium, silicon on insulator or germanium on insulator. Accordingly, the material of the substrate comprises: germanium, silicon on insulator or germanium on insulator. The material of the fin portion includes: germanium, silicon on insulator or germanium on insulator.

Referring to fig. 6, a plurality of first gate structures 211 located on the substrate 200, a plurality of first source-drain doped regions 221 located in the substrate 200, and a dielectric layer 230 located on the substrate 200 are formed, where the first gate structures 211 are located on the dense region a, the first gate structures 211 include first gate layers 2111, the substrate 200 at two sides of each first gate structure 211 is provided with first source-drain doped regions 221, and the dielectric layer 230 is located on the surface of the first gate structure 211 and the surface of the first source-drain doped regions 221.

In this embodiment, the semiconductor structure further includes: a plurality of second gate structures 212 located on the substrate 200, and a plurality of second source-drain doped regions 222 located in the substrate 200, where the second gate structures 212 are located on the sparse region B, the second gate structures 212 include a second gate layer 2121, and the substrate 200 at two sides of each of the second gate structures 212 respectively has a second source-drain doped region 222 therein; the dielectric layer 230 is located on the surface of the second gate structure 212 and the surface of the second source/drain doped region 222.

In this embodiment, the substrate 200 includes a substrate and a plurality of fins located on a surface of the substrate, the first gate structure 211 spans the plurality of fins, and the first gate structure 211 covers a portion of top surfaces and sidewall surfaces of the fins; the first source-drain doped region 221 is located in the fin portions on two sides of the first gate structure 211.

The distance between the adjacent first gate structures 211 is smaller than the distance between the adjacent second gate structures 212 and the adjacent first gate structures 211 is smaller than the distance between the adjacent second gate structures 212, so that the density of devices formed on the dense region a is greater than that of devices formed on the sparse region B.

The dielectric layer 230 includes: the dielectric layer structure comprises a first dielectric layer (not marked in the figure), an etching stop layer (not marked in the figure) positioned on the surface of the first dielectric layer, and a second dielectric layer (not marked in the figure) positioned on the surface of the etching stop layer.

Specifically, in this embodiment, the first gate structure 211 further includes: a first gate dielectric layer 2112 located at the bottom of the first gate layer 2111, and a first barrier layer 2113 located at the top surface of the first gate dielectric layer 2112 and the top surface of the first gate layer 2111.

The material of the first gate dielectric layer 2112 includes: a high-K dielectric material, the high-K dielectric material comprising: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. In this embodiment, the first gate dielectric layer 2112 is made of hafnium oxide.

The material of the first gate layer 2111 includes: a metal, the metal comprising: one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride. In this embodiment, the material of the first gate layer 2111 is tungsten.

The material of the first barrier layer 2113 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride. In this embodiment, the material of the first barrier layer 2113 is silicon oxynitride.

The first barrier layer 2113 is used for protecting the surface of the first gate layer 2111, so that the first gate layer 2111 can keep the appearance, and the generation of defects is reduced.

The forming method of the first gate structure 211, the first source-drain doped region 221, and the dielectric layer 230 includes: forming a first dummy gate structure (not shown) on the substrate 200; forming a first source-drain doped region 221 in the substrate 200 at two sides of the first dummy gate structure; forming a first dielectric layer on the substrate 200, wherein the first dielectric layer is located on the surface of the first dummy gate structure and the surface of the first source-drain doped region 221; removing the first pseudo gate structure, and forming a first pseudo gate opening in the first dielectric layer, wherein the first pseudo gate opening is not marked in the figure); forming a first gate dielectric layer 2112, a first gate layer 2111 positioned on the surface of the first gate dielectric layer 2112, and a first barrier layer 2113 positioned on the top surface of the first gate dielectric layer 2112 and the top surface of the first gate layer 2111 in the first dummy gate opening; forming an etching stop layer on the surface of the first barrier layer 2113 and the surface of the first dielectric layer; and forming the second dielectric layer on the surface of the etching stop layer.

The material of the dielectric layer 230 includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride or silicon oxynitride.

In this embodiment, the dielectric layer 230 is made of an oxide layer.

The etching stop layer is used as a stop layer for forming the third opening later.

Specifically, in this embodiment, the second gate structure 212 further includes: a second gate dielectric layer 2122 located on the bottom of the second gate layer 2121, and a second barrier layer 2123 located on the top surface of the second gate dielectric layer 2122 and the top surface of the second gate layer 2121.

The material of the second gate dielectric layer 2122 is the same as that of the first gate dielectric layer 2112, and is not described herein again.

The material of the second gate layer 2121 is the same as that of the first gate layer 2111, and is not described herein again.

The material of the second barrier layer 2123 is the same as that of the first barrier layer 2113, and is not described in detail here.

Referring to fig. 7 and 8, fig. 8 is a schematic cross-sectional view taken along tangential directions X-X1 and Y-Y1 in fig. 7, wherein a plurality of first openings 241 are formed in the dielectric layer 230, and a top surface of the first source/drain doped region 221 is exposed at the bottom of each first opening 241.

In this embodiment, the method for forming a semiconductor structure further includes: a plurality of fourth openings 244 are formed in the dielectric layer 230, and the bottom of each fourth opening 244 exposes a top surface of the second source/drain doped region 222.

The first and fourth openings 241 and 244 are formed at the same time.

The method of forming the first opening 241 and the fourth opening 244 includes: forming a first patterned layer (not shown in the figure) on the surface of the dielectric layer 230, wherein the first patterned layer exposes the surface of the dielectric layer 230 on the first source-drain doped region 221 and the second source-drain doped region 222; and etching the dielectric layer 230 by using the first patterning layer as a mask until the top surfaces of the first source-drain doped region 221 and the second source-drain doped region 222 are exposed, forming the first opening 241 in the dense region a, and forming the fourth opening 244 in the sparse region B.

The process for etching the dielectric layer 230 includes: anisotropic dry etching process.

The forming process of the first patterning layer comprises the following steps: and (4) carrying out an extreme ultraviolet photoetching process.

-the material of the first graphic layer comprises: and (7) photoresist.

In this embodiment, after forming the first opening 241 and the fourth opening 244, the following steps are further included: and removing the first patterning layer.

In this embodiment, the process of removing the first patterning layer is an ashing process.

Referring to fig. 9 and 10, the view directions of fig. 9 and 7 are the same, and the view directions of fig. 10 and 8 are the same, a first planarization layer 250 is formed in the first opening 241 and on the surface of the dielectric layer 230.

The material of the first planarization layer 250 is different from the material of the dielectric layer 230.

The material of the first planarization layer 250 includes: a carbon-oxygen containing organic material.

In this embodiment, the material of the first planarization layer 250 is a bottom anti-reflective material.

The process of forming the first planarization layer 250 includes: and (4) spin coating.

Referring to fig. 11, fig. 11 and fig. 9 are the same in view direction, a plurality of second openings 242 are formed in the dielectric layer 230, and a portion of the surface of the top of the first gate structure 211 is exposed at the bottom of each second opening 242.

In this embodiment, the method for forming a semiconductor structure further includes: a plurality of fifth openings 245 are formed in the dielectric layer 230, a bottom of each fifth opening 245 exposes a portion of a top surface of one second gate structure 212, and the fourth openings 244 and the fifth openings 245 are separated from each other.

The second opening 242 and the fifth opening 245 are formed simultaneously.

The method for forming the second opening 242 and the fifth opening 245 includes: forming a second patterned layer 252 on the dielectric layer 230, wherein the second patterned layer 252 exposes the surfaces of the dielectric layer 230 on the first gate structure 211 and the second gate structure 212; and etching the dielectric layer 230 by using the second patterned layer 252 as a mask until the top surfaces of the first gate structure 211 and the second gate structure 212 are exposed, forming the second opening 242 in the dense region a, and forming the fifth opening 245 in the sparse region B.

Specifically, in this embodiment, the dielectric layer 230 is etched until the top surfaces of the first gate layer 2111 and the second gate layer 2121 are exposed.

The forming process of the second patterned layer 252 includes: and (4) carrying out an extreme ultraviolet photoetching process.

Specifically, the second patterned layer 252 is located on the surface of the first planarization layer 250.

After the second opening 242 is formed, the first planarization layer 250 is removed.

In this embodiment, after the second opening 242 and the fifth opening 245 are formed, the second patterning layer 252 is removed; after removing the second patterned layer 252, the first planarizing layer 250 is removed.

In the present embodiment, the process of removing the second patterning layer 252 and the first planarizing layer 250 is an ashing process.

Referring to fig. 12, the view directions of fig. 12 and fig. 11 are the same, and a second planarization layer 260 is formed on the first opening 241, the second opening 242, and the surface of the dielectric layer 230.

The material of the second planarization layer 260 is different from the material of the dielectric layer 230.

The material of the second planarization layer 260 includes: a carbon-oxygen containing organic material.

In this embodiment, the material of the second planarization layer 260 is a bottom anti-reflective material.

The process of forming the second planarization layer 260 includes: and (4) spin coating.

Referring to fig. 13 and 14, the view directions of fig. 13 and 9 are the same, and the view directions of fig. 14 and 10 are the same, a plurality of third openings 243 are formed in the dielectric layer 230, the bottom of the third openings 243 is higher than the top surface of the first gate layer 2112, and the third openings 243 are respectively communicated with the first openings 241 and the second openings 242.

The depth-to-width ratio range of the third opening 243 is 2: 9 to 8: 3.

the significance of selecting the range is: if the aspect ratio of the third opening 243 is greater than 8: 3, the third opening 243 is too deep, which greatly requires the difficulty of forming the third opening 243 by etching, thereby increasing the difficulty of the process; if the aspect ratio of the third opening 243 is less than 2: 9, the third opening 243 is shallow, and the overlapping portions of the third opening 243, the first opening 241 and the second opening 242 are few, so that the third opening 243 is not communicated with the first opening 241 or the third opening 243 is not communicated with the second opening 242, which is easy to occur, so that a subsequently formed conductive structure cannot be simultaneously electrically connected to the first source/drain doped region 221 and the first gate structure 211, and the formed semiconductor structure has a problem.

In this embodiment, the method for forming a semiconductor structure further includes: and forming a plurality of sixth openings 246 in the dielectric layer 230, wherein the bottoms of the sixth openings 246 are higher than the top surface of the second gate layer 2121, and the sixth openings 246 are respectively communicated with the fourth openings 244 and the fifth openings 245.

The third opening 243 and the sixth opening 246 are formed at the same time.

The method for forming the third opening 243 and the sixth opening 246 includes: forming a third patterned layer 263 on the dielectric layer 230, wherein the third patterned layer 263 exposes the surface of the dielectric layer 230 between the first opening 241 and the second opening 242 and the surface of the dielectric layer 230 between the fourth opening 244 and the fifth opening 245; and etching the dielectric layer 230 by using the third patterning layer 263 as a mask, so as to form the third opening 243 in the dense region a and the sixth opening 246 in the sparse region B.

Specifically, in this embodiment, the dielectric layer 230 is etched until the surface of the etch stop layer is exposed, the third opening 243 is formed in the dense region a, and the sixth opening 246 is formed in the sparse region B.

Specifically, the third patterned layer 263 is located on the surface of the second planarization layer 260.

The formation process of the third patterned layer 263 includes: and (4) carrying out an extreme ultraviolet photoetching process.

The material of the third patterned layer 263 includes: and (7) photoresist.

After the third opening 243 is formed, the second planarization layer 260 is removed.

In this embodiment, after the third opening 243 and the sixth opening 246 are formed, the third patterned layer 263 is removed; after removing the third patterned layer 263, the second planarizing layer 260 is removed.

In this embodiment, the process of removing the third patterning layer 263 and the second planarization layer 260 is an ashing process.

By forming the first opening 241 exposing the top surface of the first source/drain doped region 221, the second opening 242 exposing the top surface of the first gate layer 2111, and the third opening 243 between the adjacent first opening 241 and second opening 242 in different processes. Since the third opening 243 is respectively communicated with the first opening 241 and the second opening 242, the third opening 243 can connect the first opening 241 and the second opening 242, so that the subsequent conductive structures formed in the first opening 241, the second opening 242 and the third opening 243 can be electrically connected with the first gate structure 211 and the first source-drain doped region 221 at the same time, thereby meeting the process requirements. Meanwhile, the first opening 241, the second opening 242 and the third opening 243 are completed in three different etching processes, so that the influence caused by different processes can be reduced, and the bottom of the third opening 243 is higher than the top surface of the first gate layer 2111, so that the over-etching of the first source-drain doped region 221 at the bottom of the first opening 241 in the process of forming the third opening 243 can be avoided, and therefore, the leakage current generated between the first gate structure 211 and the substrate 200 is reduced, and the performance of the formed semiconductor structure is better.

The substrate 200 further includes a sparse region B, the sparse region B has a second gate structure 212, and the substrate 200 on both sides of the second gate structure 212 has second source-drain doped regions 222 therein, respectively. Since the first opening 241 and the fourth opening 244 are formed at the same time, the second opening 242 and the fifth opening 245 are formed at the same time, the third opening 243 and the sixth opening 246 are formed at the same time, and the first opening 241 and the fourth opening 244, the second opening 242 and the fifth opening 245, and the third opening 243 and the sixth opening 246 are formed in the dense region a and the sparse region B in different processes, which is beneficial to reducing the influence on different processes, so that in the process of forming the fifth openings 245 on the dense region a and the sixth openings 246 on the sparse region B, the first source drain doped region 221 at the bottom of the first opening 241 and the second source drain doped region 222 at the bottom of the fourth opening 244 are not over-etched, thereby reducing the leakage current generated between the first gate structure 211 and the substrate 200 and between the second gate structure 212 and the substrate 200, and leading the performance of the formed semiconductor structure to be better.

Referring to fig. 15, a conductive material is filled in the first opening 241, the second opening 242, and the third opening 243 to form a conductive structure 270.

Since the third opening 243 is respectively communicated with the first opening 241 and the second opening 242, the conductive structures 270 located in the third opening 243, the first opening 241 and the second opening 242 can be electrically connected to the first source drain doping region 221 and the first gate structure 221 together, so as to meet the process requirements.

In this embodiment, the method further includes: the fourth opening 244, the fifth opening 245 and the sixth opening 246 are filled with a conductive material to form the conductive structure 270.

In this embodiment, the method for forming the conductive structure 270 includes: forming a conductive material film in the first opening 241, the second opening 242, the third opening 243, the fourth opening 244, the fifth opening 245, the sixth opening 246 and on the surface of the dielectric layer 230; the conductive material film is planarized until the surface of the dielectric layer 230 is exposed, a conductive structure 270 is formed in the first opening 241, the second opening 242 and the third opening 243 on the dense region a, and a conductive structure 270 is formed in the fourth opening 244, the fifth opening 245 and the sixth opening 246 on the sparse region B.

Although the present invention is disclosed above, the present invention is not limited thereto. Since various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, the invention resides in the claims hereinafter appended.