阅读说明：本技术 一种功率器件的制备方法及功率器件 (Preparation method of power device and power device ) 是由 蔡政原 于 2021-07-08 设计创作，主要内容包括：本申请属于半导体器件技术领域,提供了一种功率器件的制备方法及功率器件,首先在衬底上形成外延层,然后对外延层依次进行沟道掺杂和源极掺杂,并对掺杂后的器件进行刻蚀形成沟槽,以在沟槽两侧均形成沟道掺杂区和源极掺杂区；其中,沟道掺杂区位于源极掺杂区与外延层之间,沟槽的深度大于掺杂区的深度,从而在形成沟槽之前完成离子掺杂注入,避免了沟槽刻蚀之后进行离子掺杂所造成的沟道离子掺杂稳定较低、容易导致漏极到源极的漏电等问题。(The application belongs to the technical field of semiconductor devices, and provides a preparation method of a power device and the power device, wherein an epitaxial layer is formed on a substrate, then channel doping and source doping are sequentially carried out on the epitaxial layer, and the doped device is etched to form a groove, so that a channel doping region and a source doping region are formed on two sides of the groove; the channel doping area is located between the source doping area and the epitaxial layer, and the depth of the groove is larger than that of the doping area, so that ion doping injection is completed before the groove is formed, and the problems that the channel ion doping stability is low, the drain electrode is easy to leak electricity to the source electrode and the like caused by ion doping after the groove is etched are solved.)

1. A method for manufacturing a power device, comprising:

forming an epitaxial layer on a substrate;

sequentially carrying out channel doping and source doping on the epitaxial layer;

etching the doped device to form a groove;

the channel doping region is located between the source doping region and the epitaxial layer, and the depth of the groove is larger than that of the doping region.

2. The method of manufacturing a power device according to claim 1, wherein the sequentially performing channel doping and source doping on the epitaxial layer comprises:

implanting a first semiconductor element into the epitaxial layer to form a channel doped region;

injecting a second semiconductor element into the channel doping region to form a source doping region;

the depth of the second semiconductor implantation is smaller than that of the first semiconductor implantation, the first semiconductor element is a P-type element, and the second semiconductor element is an N-type element; or the first semiconductor element is an N-type element and the second semiconductor element is a P-type element.

3. The method of manufacturing a power device according to claim 2, wherein a depth of the second semiconductor implant is less than a depth of the first semiconductor implant.

4. The method for manufacturing a power device according to claim 2, wherein an implantation concentration of the second semiconductor element is larger than an implantation concentration of the first semiconductor element.

5. The method of manufacturing a power device according to claim 1, further comprising:

carrying out oxidation treatment on the groove to form a gate oxide layer;

and filling polysilicon in the groove to form a gate.

6. The method for manufacturing a power device according to claim 5, wherein the oxidizing the trench comprises:

and oxidizing the polycrystalline silicon on the inner surface of the groove by performing thermal oxidation treatment on the groove to form a gate oxide layer.

7. The method for manufacturing a power device according to claim 5, further comprising:

and forming an insulating oxide layer on the polycrystalline silicon.

8. The method for manufacturing a power device according to claim 7, further comprising:

forming a source contact hole by etching;

and carrying out ion implantation on the contact hole.

9. The method of manufacturing a power device according to claim 8, further comprising:

and forming a metal layer on the insulating oxide layer, wherein the metal layer is connected with the source electrode doped region.

10. A power device produced by the method for producing a power device according to any one of claims 1 to 9.

Technical Field

The present disclosure relates to the field of semiconductor devices, and particularly to a method for manufacturing a power device and a power device.

Background

In the related semiconductor technology, the switching loss of the power device is determined by the size of a parasitic capacitor, and the parasitic capacitor can be divided into a gate-source capacitor, a gate-drain capacitor and a source-drain capacitor. The gate-drain capacitance has the largest influence on the switching loss of the device, and can be divided into an oxide layer capacitance and a depletion layer capacitance, wherein the oxide layer capacitance is influenced by the thickness of gate oxide, and the depletion layer capacitance is influenced by the process and the structure of the device. The gate-drain capacitance directly affects the input capacitance and the switching time of the device, and the input capacitance is increased, so that the switching time of the device is prolonged, and the switching loss is increased.

However, in the conventional process steps of the power device, the ion doping step is usually performed after the trench is formed, which has the problems of low stability of the channel ion doping, and easy leakage from the drain to the source.

Disclosure of Invention

The present application aims to provide a method for manufacturing a power device and a power device, and aims to solve the problems of low stability of channel ion doping, easy leakage from a drain to a source, and the like in the process steps of the conventional power device.

The first aspect of the present application provides a method for manufacturing a power device, including:

forming an epitaxial layer on a substrate;

sequentially carrying out channel doping and source doping on the epitaxial layer;

etching the doped device to form a groove;

the channel doping region is located between the source doping region and the epitaxial layer, and the depth of the groove is larger than that of the doping region.

In one embodiment, the sequentially performing channel doping and source doping on the epitaxial layer includes:

implanting a first semiconductor element into the epitaxial layer to form a channel doped region;

injecting a second semiconductor element into the channel doping region to form a source doping region;

the depth of the second semiconductor implantation is smaller than that of the first semiconductor implantation, the first semiconductor element is a P-type element, and the second semiconductor element is an N-type element; or the first semiconductor element is an N-type element and the second semiconductor element is a P-type element.

In one embodiment, the depth of the second semiconductor implant is less than the depth of the first semiconductor implant.

In one embodiment, the implantation concentration of the second semiconductor element is greater than the implantation concentration of the first semiconductor element.

In one embodiment, the preparation method further comprises:

carrying out oxidation treatment on the groove to form a gate oxide layer;

and filling polysilicon in the groove to form a gate.

In one embodiment, the oxidizing the trench includes:

and oxidizing the polycrystalline silicon on the inner surface of the groove by performing thermal oxidation treatment on the groove to form a gate oxide layer.

In one embodiment, the preparation method further comprises:

and forming an insulating oxide layer on the polycrystalline silicon.

In one embodiment, the preparation method further comprises:

forming a source contact hole by etching;

and carrying out ion implantation on the contact hole.

In one embodiment, the preparation method further comprises:

and forming a metal layer on the insulating oxide layer, wherein the metal layer is connected with the source electrode doped region.

The second aspect of the embodiments of the present application further provides a power device, which is prepared by the preparation method of the power device according to any one of the embodiments.

According to the preparation method of the power device and the power device, firstly, an epitaxial layer is formed on a substrate, then channel doping and source doping are sequentially carried out on the epitaxial layer, the doped device is etched to form a groove, and a channel doping area and a source doping area are formed on two sides of the groove; the channel doping area is located between the source doping area and the epitaxial layer, and the depth of the groove is larger than that of the doping area, so that ion doping injection is completed before the groove is formed, and the problems that the channel ion doping stability is low, the drain electrode is easy to leak electricity to the source electrode and the like caused by ion doping after the groove is etched are solved.

Drawings

Fig. 1 is a schematic flow chart of a method for manufacturing a power device according to an embodiment of the present disclosure.

Fig. 2 is a schematic structural diagram of an epitaxial layer 200 formed on a substrate 100 according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a doped region formed on the epitaxial layer 200 according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a trench 400 formed in the epitaxial layer 200 according to an embodiment of the present disclosure;

fig. 5 is a schematic flowchart of step S20 provided in the embodiment of the present application;

fig. 6 is a schematic flow chart of another manufacturing method of a power device provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram of a gate oxide layer 410 formed on the inner wall of the trench 400 according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram illustrating the formation of an insulating oxide layer 500 on the polysilicon filled in the trench 400 according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of a power device after forming a contact hole 600 and a metal layer 700 according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "comprises" and "comprising," and any variations thereof, in the description and claims of this application and the drawings described above, are intended to cover non-exclusive inclusions. For example, a process, method, or system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. Furthermore, the terms "first," "second," and "third," etc. are used to distinguish between different objects and are not used to describe a particular order.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. Furthermore, the terms "first", "second", and "third", etc. are used for distinguishing between different objects and not for describing a particular order, but are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.

In the conventional process steps of the power device, an ion doping step is usually performed after the trench is formed, which has the problems of low stability of channel ion doping, easy leakage from the drain to the source, and the like.

In order to solve the technical problem, in the embodiment of the application, the trench etching step is performed after the ion doping step is performed, so that the problems of poor control stability of the channel length and the channel ion doping region and easy electric leakage in the traditional process are solved.

Specifically, the embodiment of the present application provides a method for manufacturing a power device, and referring to fig. 1, the method in the embodiment includes steps S10 to S30.

In step S10, an epitaxial layer is formed on a substrate.

Referring to fig. 2, by forming an epitaxial layer 200 on a substrate 100, the epitaxial layer 200 may be prepared by means of epitaxial growth.

In step S20, the epitaxial layer is sequentially subjected to channel doping and source doping.

Referring to fig. 3, the epitaxial layer 200 is sequentially channel-doped and source-doped to form doped regions, which include a channel doped region 310 and a source doped region 320, wherein the channel doping and the source doping are implanted with different elements and concentrations.

In step S30, etching the doped device to form a trench; the channel doping region is located between the source doping region and the epitaxial layer, and the depth of the groove is larger than that of the doping region.

Referring to fig. 4, a trench 400 is formed on the device in fig. 3 by an etching process, the channel doped region 310 and the source doped region 320 are divided into two parts, the channel doped region 310 and the source doped region 320 are formed on both sides of the trench 400, and the etching depth of the trench 400 is greater than the depth of the doped region.

In this embodiment, first, an epitaxial layer 200 is formed on a substrate 100, then channel doping and source doping are sequentially performed on the epitaxial layer 200, and the doped device is etched to form a trench 400, so as to form a channel doped region 310 and a source doped region 320 on both sides of the trench 400; the channel doping region 310 is located between the source doping region 320 and the epitaxial layer 200, and the depth of the trench 400 is greater than that of the doping region, so that ion doping implantation is completed before the trench 400 is formed, the problems of low channel ion doping stability, easy drain-to-source leakage and the like caused by ion doping after the trench 400 is etched are solved, and the process control of a channel ion implantation region and the channel length is improved.

In one embodiment, referring to fig. 5, in step S20, the epitaxial layer is sequentially channel-doped and source-doped, including step S21 and step S22.

In step S21, a first semiconductor element is implanted into the epitaxial layer to form a channel doping region.

In step S22, performing second semiconductor element implantation on the channel doped region to form a source doped region; the depth of the second semiconductor implantation is smaller than that of the first semiconductor implantation, the first semiconductor element is a P-type element, and the second semiconductor element is an N-type element; or the first semiconductor element is an N-type element and the second semiconductor element is a P-type element.

In this embodiment, after ion implantation is performed on the epitaxial layer 200, annealing treatment needs to be performed on the epitaxial layer, and the annealing treatment step may be performed after two ion implantations are completed, or may be performed after each ion implantation is completed.

The two ion implantations are different in element, and after the two ion implantations, the channel doped region 310 and the source doped region 320 form a PN junction, that is, if the N-type element-based ions are implanted in step S21, the P-type element-based ions are implanted in step S22.

In one embodiment, the P-type element includes elements of groups IIIA to 0 of the periodic table, for example, the P-type element includes boron (B), aluminum (Al), gallium (Ga), indium (In), and the like.

In one embodiment, the N-type elements include group VA elements and group VIA elements, for example, the N-type elements include nitrogen (N), phosphorus (P), arsenic (As), and the like.

In one embodiment, the depth of the second semiconductor implant is less than the depth of the first semiconductor implant.

In a specific application, the depth of the ions implanted in step S22 may be set according to the user' S requirement, and the implantation depth is less than the depth of the ions implanted in step S21, for example, the depth of the ions implanted in step S22 may be one third or one half of the depth of the ions implanted in step S21.

In one embodiment, the implantation concentration of the second semiconductor element is greater than the implantation concentration of the first semiconductor element.

In the present embodiment, since the ions implanted in step S22 are used to form the source region, the concentration of the implanted ions needs to be much greater than that of the ions implanted in step S21.

In one embodiment, referring to fig. 6, the preparation method further includes step S40 and step S50.

In step S40, the trench is oxidized to form a gate oxide layer.

Referring to fig. 7, a gate oxide layer 410 may be formed on the inner wall of the trench by thermal oxidation or oxide deposition.

In one embodiment, the thickness of the gate oxide layer 410 is between 0.01 microns and 10 microns.

In step S50, polysilicon is filled in the trench to form a gate.

Referring to fig. 7, a gate 420 is formed in the trench 400 by polysilicon filling.

In one embodiment, in step S40, the trench is subjected to an oxidation process, including: and oxidizing the polycrystalline silicon on the inner surface of the groove by performing thermal oxidation treatment on the groove to form a gate oxide layer.

As described with reference to fig. 7, the gate oxide layer 410 is formed in the trench 400 by a thermal oxidation process to oxidize the polysilicon on the inner surface of the trench 400.

In the specific application, since the gate oxide layer 410 is grown after the source ion implantation step, the growth temperature of the gate oxide layer 410 needs to be controlled during the growth process to prevent the source ions with high doping concentration from diffusing into the gate oxide layer 410, thereby affecting the quality of the gate oxide layer 410.

In one embodiment, referring to fig. 6, the preparation method further includes step S60. In step S60, an insulating oxide layer is formed on the polysilicon.

Referring to fig. 8, an insulating oxide layer 500 is formed on the polysilicon filled in the trench 400 for isolating the source doped region, the gate and the metal layer.

In one embodiment, the insulating oxide layer 500 is between 0.01 microns and 10 microns thick.

In one embodiment, referring to fig. 6, the preparation method further includes step S70 and step S80.

In step S70, a source contact hole is formed by etching.

In step S80, ion implantation is performed on the contact hole.

Referring to fig. 9, a contact hole 600 is formed by etching a channel doping region, and an annealing process is performed after ion implantation to the contact hole 600.

In one embodiment, referring to fig. 6, the preparation method further includes step S90.

In step S90, a metal layer is formed on the insulating oxide layer, and the metal layer is connected to the source doped region.

Referring to fig. 9, a metal layer 700 is formed on the insulating oxide layer 500 and connected to the doped region through the contact hole 600.

In an embodiment, since the ion implantation of the doped region is performed before the etching step of the trench 400, all annealing conditions, such as temperature, time, and gas, after the etching step of the trench 400 must be adjusted to avoid the problem that the channel length of the finally formed channel is not as long as expected, which may result in insufficient breakdown voltage or large on-resistance of the device.

The embodiment of the application also provides a power device, and the power device is prepared by the preparation method of the power device according to any one of the embodiments.

The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.