阅读说明：本技术 在载体衬底上制备碳化硅和氮化物结构 (Preparation of silicon carbide and nitride structures on carrier substrates ) 是由 S·J·怀特利 D·亚普 E·H·陈 D·M·金 T·D·拉德 于 2021-05-12 设计创作，主要内容包括：用于形成半导体结构的方法、装置和系统。将位于在碳化硅衬底上形成的一组第III族氮化物层上的第一氧化物层与位于载体衬底上的第一氧化物层结合以形成位于载体衬底和所述组第III族氮化物层之间的氧化物层。碳化硅衬底具有掺杂层。使用光电化学蚀刻工艺蚀刻具有掺杂层的碳化硅衬底,其中掺杂层的掺杂水平使得掺杂层被除去并且碳化硅衬底中的碳化硅层保持未被蚀刻。使用碳化硅层和所述组第III族氮化物层形成半导体结构。(Methods, apparatus, and systems for forming semiconductor structures. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a first oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. A silicon carbide substrate having a doped layer is etched using a photoelectrochemical etching process wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.)

1. A method for forming a semiconductor structure, the method comprising:

(2600) forming a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) comprises a doped layer (106, 904, 1302), and wherein the doped layer (106, 904, 1302) has a doping level such that the doped layer (106, 904, 1302) is etched using a photoelectrochemical etch process while other portions of the silicon carbide substrate (100, 1003) remain unetched;

(2602) forming a first oxide layer (402, 912) on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003);

(2604) bonding the first oxide layer (402, 912) with a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312);

(2606) grinding the silicon carbide substrate (100, 1003);

(2608) stopping lapping when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached;

(2610) etching the silicon carbide substrate (100, 1003) using the photoelectrochemical etch process such that the doped layer (106, 904, 1302) is removed and a silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains when the partially doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed; and

(2612) forming the semiconductor structure using the silicon carbide device layer (100, 906) and the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

2. The method of claim 1, wherein combining the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) occurs after etching the silicon carbide substrate (100, 1003).

3. The method of any of the preceding claims, wherein combining the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1802, 2002, 2102, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1802, and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2212, 2310, 2312) is performed after etching the group III nitride layer in the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2212, 2310, 2312).

4. The method of any of claims 1-2, wherein combining the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed prior to etching the silicon carbide substrate (100, 1003).

5. The method of any of claims 1-2, wherein combining the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises:

(2700) contacting a first surface of a first oxide layer (402, 912) with a second surface of a first oxide layer (504, 1002), wherein an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

(2702) annealing the first oxide layer (402, 912) and the first oxide layer (504, 1002) while directly contacting the first surface with the second surface to form an oxide layer (600, 1100, 1312, 1604, 1804) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III-nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

6. The method of any of claims 1-2, wherein etching the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that the doped layer (106, 904, 1302) is removed and a silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains when the partially doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed comprises:

etching one of a silicon face and a carbon face of the silicon carbide substrate (100, 1003) using the photoelectrochemical etching process such that when the partially doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains.

7. The method of any of claims 1-2, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of the silicon carbide device layer (100, 906) on a wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance, and/or wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory that uses a point defect within the silicon carbide device layer (100, 906).

8. The method of any of claims 1-2, wherein the silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate, and/or wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

9. A method for forming a semiconductor structure, the method comprising:

(2800) combining a first oxide layer (402, 912) located on a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1312, 1100, 1604, 2104, 1310, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the set of group III nitride layers (200, 908, 910, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 2304);

(2082) etching the silicon carbide substrate (100, 1003) with the doped layer (106, 904, 1302) using a photoelectrochemical etch process, wherein a doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and a silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched; and

(2804) forming the semiconductor structure using the silicon carbide device layer (100, 906) and the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

10. The method of claim 9, further comprising:

(2606) grinding the silicon carbide substrate (100, 1003) prior to etching the silicon carbide substrate (100, 1003);

(2608) stopping lapping of the silicon carbide substrate (100, 1003) when a portion of a doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached before etching the silicon carbide substrate (100, 1003);

(2600) forming the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003); and/or

(2602) Forming a first oxide layer (402, 912) on the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

11. The method of any of claims 9-10, wherein combining a first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 2004, 1314, 1802, 2002, 2102, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 1310, 1606, 6, 2006, 2106, 1802212, 2310, 2312) located between the carrier substrate (500, 1312, 1604, 2004, 2204, 2302) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 2006, 2314, 2302) is performed after etching the silicon carbide substrate (100, 1003).

12. The method according to any of claims 9-10, wherein combining a first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1802, 2002, 2102, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is performed after etching the group III nitride layer in the group III nitride layer (200, 908, 910, 1310, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

13. The method of any of claims 9-10, wherein combining a first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 2210, 1604, 1804, 1314, 2104, 1314, 1802, 1310, 1606, 6, 2006, 2106, 180, 2212, 2310, 2312) located between the carrier substrate (500, 1000, 2104, 1602, 1314, 1802, 2002, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 2006, 2106, 180, 1804, 2212, 2310, 2312) is performed prior to etching the silicon carbide substrate (100, 1003).

14. The method of any of claims 9-10, wherein combining a first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with a first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 2210, 1604, 1804, 2004, 1314, 1802, 1310, 1606, 6, 2006, 2106, 180, 2212, 2310, 2312) located between the carrier substrate (500, 1000, 2104, 1602, 1802, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 2006, 2106, 180, 2212, 2310, 2312) comprises:

(2700) contacting a first surface of the first oxide layer (402, 912) with a second surface of the first oxide layer (504, 1002), wherein an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

(2702) annealing the first oxide layer (402, 912) and the first oxide layer (504, 1002) while directly contacting the first surface with the second surface to form the oxide layer (600, 1100, 1312, 1604, 1804) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III-nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

15. The method of any of claims 9-10, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of a silicon carbide device layer (100, 906) on a wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory that uses point defects within the silicon carbide device layer (100, 906), wherein the silicon carbide device layer (100, 906) and the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers, wherein the carrier substrate (500, 906) is a thin film layer, 1000. 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an alumina substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate, and/or wherein the group III nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

Technical Field

The present disclosure relates generally to semiconductors, and in particular, to methods for forming semiconductor structures, and in particular, to forming silicon carbide and nitride structures on carrier substrates.

Background

Silicon carbide and group III nitrides, such as gallium nitride, are ideal semiconductors for signal processing and quantum applications. These materials have wide bandgaps greater than 3eV and larger nonlinear optical coefficients than other materials currently used for low-loss photonics and on-chip nonlinear optics, such as silicon, silicon dioxide, and silicon nitride materials.

Silicon carbide (SiC) is a semiconductor material containing silicon and carbon. Silicon carbide may be used in devices for quantum information processing, as well as other purposes. For example, color centers in a silicon carbide structure may be used to provide an optical reading indicative of its electron spin state. Each color center is a qubit in quantum computing. The state of a qubit can be a logical "0", a logical "1", or a superposition of the two states. For example, color centers can be incorporated into photonic devices, such as microcavities for waveguide elements.

Fabricating devices on silicon carbide structures can be challenging. For example, devices formed using thin films with silicon carbide and group III nitrides may be more difficult to fabricate than desired than other materials such as silicon. Thin film devices include one or more thin film layers, where the thickness of the thin film layers may be on the order of nanometers to several microns.

The quality of thin film devices using silicon carbide and group III nitrides formed on wafers may not be as good as desired compared to materials such as silicon. Accordingly, it is desirable to have a method and apparatus that takes into account at least some of the issues discussed above, as well as other possible issues. For example, it would be desirable to have a method and apparatus that overcomes the technical problems associated with forming silicon carbide and group III nitride structures having desirable qualities.

Disclosure of Invention

Embodiments of the present disclosure provide a method for forming a semiconductor structure. A set of group III nitride layers is formed on a silicon carbide substrate. The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate remain unetched. A first oxide layer is formed on the group III nitride layer. The group III-nitride layer is located between the first oxide layer and the silicon carbide substrate. The first oxide layer is combined with a second oxide layer on the carrier substrate to form an oxide layer between the carrier substrate and the group III nitride layer. And grinding the silicon carbide substrate. The lapping is stopped when a portion of the doped layer in the silicon carbide substrate achieves exposure. The silicon carbide substrate is etched using a photoelectrochemical etch such that when the portion of the doped layer in the silicon carbide substrate is exposed, the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

Another embodiment of the present disclosure provides a method for forming a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. A silicon carbide substrate having a doped layer is etched using a photoelectrochemical etching process wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

Yet another embodiment of the present disclosure provides a product management system including a manufacturing device and a control system. A control system controls the fabrication equipment to combine a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. A silicon carbide substrate having a doped layer is etched using a photoelectrochemical etch process. The doping layer has a doping level such that the doping layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

The features and functions may be achieved independently in various embodiments of the present disclosure or may be combined in yet other embodiments in which further details may be seen with reference to the following description and drawings.

Drawings

The novel features believed characteristic of the illustrative embodiments are set forth in the appended claims. The illustrative embodiments, however, as well as a preferred mode of use, further objectives and features thereof, will best be understood by reference to the following detailed description of an illustrative embodiment of the present disclosure when read in conjunction with the accompanying drawings, wherein:

FIG. 1 is an illustration of a cross-sectional view of a silicon carbide substrate in accordance with an illustrative embodiment;

FIG. 2 is an illustration of a cross-sectional view of a set of group III-nitride layers on a silicon carbide substrate in accordance with an illustrative embodiment;

FIG. 3 is an illustration of a cross-sectional view of a structure formed using a set of group III nitride layers in accordance with an illustrative embodiment;

FIG. 4 is an illustration of a cross-sectional view of silicon dioxide deposited on a silicon carbide substrate capping structure formed on a bonding side of a silicon carbide substrate in accordance with an illustrative embodiment;

FIG. 5 is an illustration of a cross-sectional view of a carrier substrate in accordance with an illustrative embodiment;

FIG. 6 is an illustration of a cross-sectional view of a silicon carbide substrate bonded to a carrier substrate in accordance with an illustrative embodiment;

FIG. 7 is a diagram showing a cross-sectional view of a portion of a silicon carbide substrate being removed in accordance with an illustrative embodiment;

FIG. 8 is an illustration of a cross-sectional view of a silicon carbide device layer in accordance with an illustrative embodiment;

FIG. 9 is an illustration of a cross-sectional view of a substrate in accordance with an illustrative embodiment;

FIG. 10 is an illustration of a cross-sectional view of bonding a workpiece to a carrier substrate in accordance with an illustrative embodiment;

FIG. 11 is an illustration showing a cross-sectional view of removing silicon carbide material from a silicon carbide substrate in accordance with an illustrative embodiment;

FIG. 12 is an illustration of a cross-sectional view of a silicon carbide material etched to reach a silicon carbide device layer in accordance with an illustrative embodiment;

FIG. 13 is an illustration of a cross-sectional view of a workpiece, according to an illustrative embodiment;

FIG. 14 is an illustration of a cross-sectional view of removal of silicon carbide material in accordance with an illustrative embodiment;

FIG. 15 is an illustration of a cross-sectional view of a doped layer within reach of a silicon carbide device layer (in reach of), in accordance with an illustrative embodiment;

FIG. 16 is an illustration of a waveguide coupled optical resonator and filter in accordance with an illustrative example;

FIG. 17 is an illustration of a cross-sectional view of a waveguide coupled optical resonator and filter in accordance with an illustrative embodiment;

FIG. 18 is an illustration of an integrated optical waveguide including a quantum memory in accordance with an illustrative example;

FIG. 19 is an illustration of a cross-sectional view of an integrated optical waveguide including a waveguide-coupled quantum memory in accordance with an illustrative embodiment;

FIG. 20 is a cross-sectional view of a waveguide in accordance with an illustrative embodiment;

FIG. 21 is another cross-sectional view of a waveguide in accordance with an illustrative embodiment;

FIG. 22 is yet another cross-sectional view of a waveguide in accordance with an illustrative embodiment;

FIG. 23 is yet another cross-sectional view of a waveguide in accordance with an illustrative embodiment;

FIG. 24 is another example of a silicon carbide substrate having a set of group III nitride layers in accordance with an illustrative embodiment;

FIG. 25 is an illustration of a flow chart of a method for forming a semiconductor structure in accordance with an illustrative embodiment;

FIG. 26 is an illustration of a flow chart of a method for forming a semiconductor structure in accordance with an illustrative embodiment;

FIG. 27 is an illustration of a flowchart of a method for joining components in accordance with an illustrative embodiment;

FIG. 28 is an illustration of a flowchart of a method for forming a semiconductor structure in accordance with an illustrative embodiment; and

FIG. 29 is an illustration of a block diagram of a product management system in accordance with an illustrative embodiment.

Detailed Description

The illustrative embodiments recognize and take into account one or more different considerations. For example, the illustrative embodiments recognize and take into account that currently used techniques may produce polycrystalline films of non-uniform silicon carbide on a wafer. In addition, the illustrative embodiments recognize and take into account that when current techniques are used to achieve the desired thickness for thin film devices, material damage can occur in the silicon carbide film, resulting in undesirable optical absorption or scattering.

Furthermore, the illustrative embodiments recognize and take into account that current techniques for fabricating silicon carbide (SiC) nanophotonics are primarily limited to 3C — SiC (cubic crystal structure) epitaxially grown on silicon (Si). Illustrative embodiments recognize and take into account, though, that SiC and Si/SiO₂Chemical etching selectivity between, 3C-SiC is easily in Si or silicon dioxide (SiO)₂) Undercutting is performed but 3C-SiC devices may suffer from undesirable optical losses resulting from dislocations at the Si-SiC growth interface, residual doping, high film strain and interface defects.

Illustrative embodiments recognize and take into account that to mitigate interface defects, 3C-SiC may be transferred to another substrate and the previous interface may be etched away. However, the illustrative embodiments recognize and take into account that 3C-SiC contains high non-uniform strain due to lattice mismatch with Si substrates. In contrast to 3C-SiC films grown on Si substrates, the illustrative embodiments recognize and take into account that single crystal bulk and homoepitaxially grown 4H-SiC and 6H-SiC (hexagonal crystal structure) contain lower crystal strain and lower growth residual doping. Thus, the illustrative embodiments recognize and take into account that the 4H-SiC platform has great potential for photonics and other related fields. Illustrative embodiments recognize and take into account that the homoepitaxial growth of 4H-SiC on silicon carbide substrates produces crystalline materials with very few lattice defects, photonics has also investigated hexagonal SiC polymorphs of silicon carbide, such as 4H-. Illustrative embodiments recognize and take into account that existing methods of isolating 4H-SiC thin films are limited given that the material is grown on bulk 4H-SiC substrates, making chemical etching of the base substrates currently in use impossible.

Illustrative embodiments recognize and take into account that thin films of hexagonal silicon carbide are suitable for photonics applications, while allowing for flexible pattern design and stacked layers. Thus, illustrative embodiments provide methods, apparatus, and systems for forming structures with desired film thickness uniformity while reducing damage or defects using silicon carbide and nitrides, such as group III nitrides. In one illustrative example, a method forms a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. A silicon carbide substrate having a doped layer is etched using a photoelectrochemical etching process wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. The semiconductor structure may be formed using the silicon carbide layer and the group III nitride layer.

One or more illustrative examples enable the fabrication of semiconductor structures using silicon carbide as a platform to provide photonic functionality. The semiconductor structure includes at least one of an optical waveguide and an optical resonator. The functions of these structures include being splitters, directional couplers, grating couplers, microrings for filters, microdisks for filters, nonlinear optical converters, light emitters and other types of functions. The illustrative examples enable the fabrication of these and other types of structures using wafer-level silicon carbide films while maintaining low optical loss.

As used herein, when the phrase "at least one of" is used with a list of items, it means that different combinations of one or more of the listed items can be used, and only one of each of the items in the list may be required. In other words, "at least one of" means that any combination of items and number of items can be used from the list, but not all items in the list are required. The item may be a particular object \ thing or category.

For example, and without limitation, "at least one of item a, item B, or item C" can include item a, item a and item B, or item B. The instance can also include item a, item B, and item C, or item B and item C. Of course, any combination of these items may be present. In some illustrative examples, "at least one" may be, for example, but not limited to, two items a; an item B; and ten items C; four items B and seven items C; or other suitable combination.

Detailed embodiments of the claimed structures and methods are disclosed herein. However, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. In addition, each example given in connection with the various embodiments is intended to be illustrative, and not restrictive.

Furthermore, the figures are not necessarily to scale, as some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure.

For the purposes of the following description, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the illustrative examples in the disclosure as oriented in the drawings. The term "positioned on" means that a first element, such as a first structure, is present on a second element, such as a second structure, with intervening elements, such as interface structures, e.g., interface layers, may be present between the first and second elements.

In the present disclosure, when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, the element may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on," "directly over" or "directly on and directly contacting" another element, there are no intervening elements present, and the element is in contact with the other element.

The methods, steps, and structures described below do not form a complete process flow for manufacturing integrated circuits. The present disclosure may be practiced in conjunction with integrated circuit fabrication techniques currently used in the art and only so many commonly practiced process steps are included as are necessary to understand the various examples of the present disclosure. The figures represent cross-sections of a portion of an integrated circuit during fabrication and are not drawn to scale, but are instead drawn to illustrate different illustrative features of the disclosure.

In an illustrative example, a method for fabricating a semiconductor structure may utilize two or more layers of silicon carbide having different doping types. In the illustrative example, a silicon carbide layer is epitaxially grown on a base silicon carbide substrate in wafer form. The silicon carbide layer or layers may be doped by implantation. The silicon carbide layer with the base silicon carbide substrate may be collectively referred to as a silicon carbide substrate. Further, an epitaxial group III nitride layer may be grown over the topmost silicon carbide layer in the silicon carbide substrate.

In addition, one or more optional layers of an epitaxial group III nitride layer may be present or grown on the first group III nitride layer. Examples of group III nitride layers that may be used include, for example, aluminum nitride (AlN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), and other group III nitrides.

In an illustrative example, the feature can be at least one of patterned and etched into or deposited on the group III nitride layer. The top of the structure may be covered with a lower index insulator such as an oxide layer formed of silicon dioxide. The oxide layer is a silicon dioxide layer deposited on a carrier substrate, also in wafer form. In the illustrative example, two wafers are bonded together.

In an illustrative example, the initial base silicon carbide substrate may be at least partially removed by grinding. In these depicted examples, the abrading may be at least one of mechanical abrading, polishing, or Chemical Mechanical Polishing (CMP). Mechanical grinding of silicon carbide substrates may produce silicon carbide layers that may have non-uniform thicknesses. When grinding is performed over distances measured in centimeters, uniformity may be low.

A Photoelectrochemical (PEC) etch may then be performed to selectively remove the exposed non-uniform silicon carbide layer until the etch-stop silicon carbide layer is reached. In this example, the photoelectrochemical etch may be performed from a carbon face or a silicon face of a silicon carbide substrate. Silicon carbide is a crystalline material and may have a silicon face or a carbon face depending on the direction. The silicon carbide layer serves as an etch stop layer compared to silicon carbide materials removed using a Photoelectrochemical (PEC) etch, and may be at least one of semi-insulating or differently doped polarity.

In an illustrative example, the resulting set of silicon carbide layers on the set of group III nitride layers may be made thinner than 1 μm, and in some cases, may be thinner than 50nm, using the techniques in the illustrative example.

In an illustrative example, an additional planarization step may be used. For example, mechanical or chemical mechanical polishing can be performed after at least one of material growth of the silicon carbide layer substrate or Photoelectrochemical (PEC) etching. These methods may be performed to reduce roughness at various interfaces.

Referring now to fig. 1-8, an illustration of a cross-section in a method of forming a semiconductor structure is depicted in accordance with an illustrative embodiment. In fig. 1, an illustration of a cross-sectional view of a silicon carbide substrate is depicted in accordance with an illustrative embodiment. As depicted, the silicon carbide (SiC) substrate 100 may be in the form of a wafer. For example, the silicon carbide substrate 100 may be a hexagonal silicon carbide wafer. In this example, the silicon carbide material may be, for example, a 4H or 6H crystal polytype. As depicted, in this example, the silicon carbide material has a non-centrosymmetric and polar crystal structure. As depicted, the wafer may, for example, have an area of 25 square centimeters or more.

In this illustrative example, a silicon carbide substrate 100 has a bonding surface 102 and an etched surface 104. More specifically, the etched surface 104 may be a carbon surface or a silicon surface of the silicon carbide substrate 100. In this example, the bonding surface 102 is the surface on which additional material for the semiconductor structure is formed.

In addition, the silicon carbide substrate 100 has a doped layer 106. Doping to form doped layer 106 may be performed using any currently available doping technique, including at least one of diffusion or ion implantation. The doped layer 106 may be a layer having a thickness of from about 50 nanometers to several tens of micrometers.

In this illustrative example, doped layer 106 may be a p-type layer or an n-type silicon carbide layer. The doping concentration is such that the doped layer 106 can be etched using a photoelectrochemical etch process. In this illustrative example, the doping is such that the doped layer 106 is etched by a photoelectrochemical etching process, while other portions of the silicon carbide substrate 100 below the doped layer 106 and in direct contact with the doped layer 106 remain unetched.

Turning next to fig. 2, an illustration of a cross-sectional view of a set of group III nitride layers on a silicon carbide substrate is depicted in accordance with an illustrative embodiment. In an illustrative example, the same reference numbers may be used in multiple figures. This reuse of reference numbers in different figures indicates that the same elements are used in different figures.

As depicted, in this example, a set of group III nitride layers 200 is grown on the bonding side 102 of the silicon carbide substrate 100. The set of group III nitride layers 200 may be grown using currently available techniques for forming nitride layers.

As used herein, a "set" when used in relation to an item means one or more items. For example, a "set of group III nitride layers 200" is one or more of the group III nitride layers 200. As depicted, the set of group III nitride layers 200 can be thin film layers where each of these thin film layers is from a fraction of a nanometer to several micrometers in thickness. For example, the thin film layer may be less than one micron.

In this illustrative example, the set of group III nitride layers 200 includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium aluminum gallium nitride (InAlGaN), or other suitable group III nitride. In this example, the group III nitridesLayer 200 comprises an AlN layer at least 10 nanometers thick. Further AlN, GaN or Al_xGa_1-xAn N layer may optionally be grown on top of this layer. These additional layers may be, for example, nanometer to several hundred microns thick. In this example, the number 'x' represents the material stoichiometric Al: ga ratio, and 'x' may have a value between 0 and 1.

Turning next to fig. 3, an illustration of a cross-sectional view of a structure formed using a set of group III nitride layers is depicted in accordance with an illustrative embodiment. As depicted, a first metal 300 and a second metal 302 are formed on a set of group III nitride layers 200. The first metal 300 and the second metal 302 may be formed using currently known techniques including industry standard photolithography and deposition techniques.

In addition, the set of group III-nitride layers 200 may be patterned and etched using currently known techniques, such as defining a hard mask, etching the group III-nitride material, and removing the hard mask. In this example, the patterning in the etch forms a first opening 304 and a second opening 306 in the set of group III nitride layers 200 to expose the bonding surface 102.

Referring now to FIG. 4, an illustration of a cross-sectional view of silicon dioxide deposited on a structure overlying a silicon carbide substrate formed on a bonding side of the silicon carbide substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, the first oxide layer 400 is silicon dioxide deposited on the first metal 300, the second metal 302, the set of group III nitride layers 200, and the bonding surface 102 exposed in the first opening 304 and the second opening 306 of the set of group III nitride layers 200. The deposition of silicon dioxide to form the first oxide layer 400 may be performed using known techniques such as plasma enhanced chemical vapor deposition, sputtering, or another suitable known technique for forming the first oxide layer 400.

As depicted, the first oxide layer 400 has a first surface 402. In this example, the first surface 402 may be processed using Chemical Mechanical Polishing (CMP) to improve planarity and reduce surface roughness. In addition, the first surface 402 of the first oxide layer 400 may be treated or activated to a hydrophilic surface.

Turning now to fig. 5, an illustration of a cross-sectional view of a carrier substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, the carrier substrate 500 may take many different forms. For example, the carrier substrate 500 may be one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, a gallium nitride substrate, and other suitable substrates.

As depicted, the carrier substrate 500 has a second oxide layer 502 with a second surface 504. In this example, the second oxide layer 502 is composed of silicon dioxide. Second surface 504 may also be chemically mechanically polished and treated or activated to a hydrophilic surface.

In an illustrative example, the silicon carbide substrate 100 in fig. 4 and the carrier substrate 500 in fig. 5 may be bonded to each other. In this illustrative example, carrier substrate 500 is a substrate for a semiconductor structure. Silicon carbide substrate 100, on the other hand, comprises a silicon carbide material that becomes a set of silicon carbide device layers used to form a semiconductor structure.

As depicted, the first surface 402 of the first oxide layer 400 on the interface 102 on the silicon carbide substrate 100 in fig. 4 may be placed in contact with the second surface 504 of the second oxide layer 502 in fig. 5. Van der waals bonding occurs through contact between first surface 402 of first oxide layer 400 and second surface 504 of second oxide layer 502. These substrates, which are bonded to each other by the oxide layer, may be annealed. The anneal may be performed at a temperature of at least 150 ℃ to enhance the bond formed between the oxide layers of the two substrates.

Referring now to fig. 6, an illustration of a cross-sectional view of a silicon carbide substrate bonded to a carrier substrate is depicted in accordance with an illustrative embodiment. In this illustrative example, the silicon carbide substrate 100 and the carrier substrate 500 are bonded to each other to form an oxide layer 600. The carrier substrate 500 is a substrate for a semiconductor structure to be formed. Oxide layer 600 is a dielectric layer for a semiconductor structure. In other illustrative examples, other types of dielectrics may be used to form the dielectric layer in addition to oxide layer 600 or in place of oxide layer 600.

Referring now to FIG. 7, an illustration showing a cross-sectional view of a portion of a silicon carbide substrate removed is depicted in accordance with an illustrative embodiment. As depicted, the silicon carbide substrate 100 is thinned. This thinning may be performed in stages. For example, the silicon carbide substrate 100 may be ground starting from the etched surface 104 until reaching the doped layer 106 in the silicon carbide substrate 100. In the example depicted here, the polish is a mechanical polish that removes most of the silicon carbide substrate 100 down to the doped layer 106. In this illustrative example, the milling may stop at doped layer 106 or extend into doped layer 106.

Referring now to fig. 8, an illustration of a cross-sectional view of a silicon carbide device layer is depicted in accordance with an illustrative embodiment. Additional thinning may be performed using a Photoelectrochemical (PEC) etch process when reaching the doped layer 106. As depicted, a photo-electrochemical (PEC) etch is performed on the side of the silicon carbide substrate 100 having the etched face 104, which is not performed using currently available techniques.

This method may be used to remove doped layer 106. The doping is selected so that other portions of the silicon carbide substrate 100 below the doped layer 106 are not removed by the photoelectrochemical etch process. Thus, doped layer 106 in silicon carbide substrate 100 acts as a sacrificial layer.

The portion of the silicon carbide substrate 100 below the doped layer 106 remains as the silicon carbide device layer 800. The silicon carbide device layer 800 is an example of a set of silicon carbide layers. In other illustrative examples, multiple silicon carbide layers may be present for forming a semiconductor structure. These further semiconductor carbide layers may have different doping levels distinguishing these layers.

In this illustrative example, the silicon carbide device layer 800 is a thin film layer. In this illustrative example, the silicon carbide device layer 800 has a thickness of about 10 nanometers to several micrometers. In some illustrative examples, the silicon carbide device layer 800 is between about 50 nanometers and about 500 nanometers. Further, a workpiece comprising the silicon carbide device layer 800, the set of group III nitride layers 200, and the oxide layer 600 may be used to perform processing on the carrier substrate 500 to fabricate one or more semiconductor structures.

By using the doped layer 106 and the photoelectrochemical etching process, the silicon carbide device layer 800 may have a higher quality level than other currently used techniques. For example, the silicon carbide device layer 800 may be a polycrystalline film having a desired uniformity across the wafer. In addition, the silicon carbide device layer 800 may have reduced inconsistencies or defects, which results in reduced undesirable optical absorption or scattering. Furthermore, in the illustrative example, in addition to producing the desired film thickness uniformity, the method can also result in the desired epitaxial growth of the desired quality. For example, using the steps in the illustrative example, thickness variations of less than 50nm may occur across a 100mm wafer.

The illustrations of methods for forming semiconductor structures in fig. 1-8 are examples of one manner in which the illustrative embodiments may be practiced. The examples presented in these figures are not meant to limit the manner in which other illustrative examples may be implemented. For example, in another illustrative example, at least one of the group ill-nitride layer 200, the first metal 300, or the second metal 302 may be omitted.

Turning next to fig. 9-12, an illustration of cross-sectional views in a method of forming a semiconductor structure is depicted in accordance with an illustrative embodiment. Referring initially to FIG. 9, an illustration of a cross-sectional view of a substrate is depicted in accordance with an illustrative embodiment. As depicted, silicon carbide substrate 900 includes a base substrate 902, a doped layer 904, and a silicon carbide device layer 906.

As depicted, base substrate 902 is a bulk 4H-SiC wafer having a degree of wafer normal miscut (normal miscut) axially offset from the (0001) crystal direction by 4 degrees or other small angles. Doped layer 904 is the first layer grown as an epitaxial layer of doped 4H-SiC and is a sacrificial portion of silicon carbide substrate 900. In this example, 4H-SiC is deposited at a desired thickness and doping specification to form the silicon carbide device layer 906 in the silicon carbide substrate 900.

In addition, a set of group III nitride layers, aluminum nitride (AlN) layer 908 and gallium nitride (GaN) layer 910 are grown on the silicon carbide device layer 906. In this example, the aluminum nitride layer 908 is an epitaxially grown undoped AlN buffer layer. Gallium nitride layer 910 may be formed to a desired specification using Metal Organic Chemical Vapor Deposition (MOCVD) or Molecular Beam Epitaxy (MBE). The doping of the gallium nitride layer 910 may be selected according to the application at the growth stage.

As depicted, a first oxide layer 912 is deposited on the gallium nitride layer 910. In this example, silicon dioxide (SiO) may be deposited using methods such as Plasma Enhanced Chemical Vapor Deposition (PECVD), sputtering, or atomic layer deposition₂) To form a first oxide layer 912. In this illustrative example, the growth of the various layers proceeds in the direction of arrow 914. These different layers form the workpiece 916.

Referring now to fig. 10, an illustration of a cross-sectional view for bonding a workpiece to a carrier substrate is depicted in accordance with an illustrative embodiment. As depicted, the workpiece 916 is flipped over compared to the view of the workpiece 916 in fig. 9. The workpiece 916 can then be bonded with the carrier substrate 1000 having the second oxide layer 1002. In this example, a bonding surface 1001 and an etched surface 1003 are shown. As depicted, the etched face 1003 may be a silicon face or a carbon face of the silicon carbide substrate 900.

In this illustrative example, the carrier substrate 1000 may be silicon carbide, silicon dioxide, aluminum oxide, or other suitable material. As depicted, the second oxide layer 1002 is formed using thermal oxidation, plasma enhanced chemical vapor deposition (PEVCD), sputtering, atomic scale deposition, or other suitable methods.

In this illustrative example, bonding may be through contact between the oxide layers. In this example, after contacting, the annealing is performed at a temperature of about 200 ℃.

In fig. 11, an illustration of a cross-sectional view of removal of silicon carbide material from a silicon carbide substrate is depicted in accordance with an illustrative embodiment. In this figure, a first oxide layer 912 and a second oxide layer 1002 are bonded to each other to form an oxide layer 1100.

As depicted, the silicon carbide substrate 900 is thinned by mechanical grinding and may be polished by Chemical Mechanical Polishing (CMP) as shown in section 1102. Portion 1102 represents the silicon carbide material that has been removed. As shown, in this example, the removal extends into doped layer 904.

In this example, mechanical polishing is used to remove a portion, but not all, of doped layer 904. In some cases, mechanical grinding and polishing may be suitable, for example, on a length scale (scale) from microns to millimeters. However, because of the larger length scales that exist and the thin film thicknesses that are desired across the wafer, and further, the forces and stresses of such material removal may introduce undesirable inconsistencies, such as lattice defects, dislocations, and crystal strain.

In this illustrative example, the mechanical polishing is stopped when the polishing extends into doped layer 904. For example, mechanical polishing may be stopped when doped layer 904 is still about a few microns thick.

Turning to fig. 12, an illustration of a cross-sectional view of a silicon carbide material etched to reach a silicon carbide device layer is depicted in accordance with an illustrative embodiment. As depicted, in this cross-sectional view, the remaining portion of doped layer 904 is removed using a photoelectrochemical etch process, as shown in portion 1200. The etch exposes the silicon carbide device layer 906 without removing material from the silicon carbide device layer 906. The dopant and doping level in the doped layer 904 are selected such that the doped layer 904 can be etched without removing material from the silicon carbide device layer 906.

Utilizing photo-electrochemical etching, a dopant type selective etch may be performed in which doped layer 904 is removed to expose silicon carbide device layer 906. In this illustrative example, the silicon carbide device layer 906 may have desirable characteristics such as a clean crystal surface and a lower defect density than when mechanical grinding is used.

In this illustrative example, the photoelectrochemical etching process may be performed while the doped layer 904 is in contact with a solution such as dilute potassium hydroxide or hydrofluoric acid and water.

Further, illumination of the carrier substrate 1000 with different layers may be performed using optical wavelength illumination having photon energies corresponding to above the bandgap of the silicon carbide. In the depicted example, the light source contains a wavelength shorter than 390nm for 4H-SiC, since the bandgap of the light source is about 3.2 eV. A voltage bias may be applied between a contact on one of the doped layers of the sample and a platinum electrode in the aqueous solution. The etch selectivity of the p-type, n-type, and intrinsic materials can be tuned and optimized by controlling the magnitude and direction of the dc voltage bias. Since photoelectrochemical etching involves wet chemistry and is selective according to the type of doping, the end result of thin films of silicon carbide and group III nitride has the desired uniformity and planarity across the wafer. This result is in contrast to currently available techniques such as smart cut, which uses ion implantation to create an amorphous layer at a defined depth. In an illustrative example, the photoelectrochemical etch avoids the introduction of new point defects or dopants into the silicon carbide and group III nitride films.

13-15 are cross-sectional views of a workpiece etched using photoelectrochemical etching according to an illustrative embodiment. Referring to FIG. 13, an illustration of a cross-sectional view of a workpiece is depicted in accordance with an illustrative embodiment. As depicted, workpiece 1300 is the result of bonding a silicon carbide substrate to a carrier substrate, wherein the bond is formed between oxide layers on both substrates.

In this illustrative example, workpiece 1300 includes a silicon substrate 1301 that includes a doped layer 1302, a doped silicon carbide device layer 1304, a silicon carbide device layer 1306, an aluminum nitride (AlN) layer 1308, a gallium nitride (GaN) layer 1310, an oxide layer 1312, and a carrier substrate 1314. In this example, doped layer 1302 is the top layer and is not located in other layers in silicon substrate 1301, as depicted in other previous examples. The workpiece 1300 has a bonding surface 1305 and an etched surface 1303. As depicted, the etched face 1303 may be a silicon face or a carbon face.

As depicted, doped layer 1302 is an n-type layer. In other illustrative examples, doped layer 1302 may be a p-type layer. The doping difference is selected to avoid etching of the doped silicon carbide device layer 1304. In other words, the doping level and doping type of the doped silicon carbide device layer 1304 may be selected such that the layer acts as an etch stop for the photoelectrochemical etch process.

In the depicted example, doped layer 1302 is a sacrificial layer that can be etched using a photoelectrochemical etch process. Doping level and doping of doped layer 1302The silicon carbide device layer 1304 has a sufficiently different doping type, density, or both, and the doped silicon carbide device layer 1304 has a doping type and level that define an etch stop layer. In this example, when doped layer 1302 is greater than 1x10¹⁸ cm^-3Has a concentration of at least 1x10, and the doped silicon carbide device layer 1304 has¹⁸ cm^-3And the opposite dopant type to doped layer 1302, etch selectivity may be maximized.

In this illustrative example, the dopant type for the doped layer 1302 is n-type, while the dopant type for the doped silicon carbide device layer 1304 is p-type. If the doped silicon carbide device layer 1304 requires a different type of dopant, such as a p-type dopant, the type of dopant used in the doped layer 1302 may be changed to an n-type dopant.

In another illustrative example, the sacrificial, doped layer 1302 and etch stop, doped silicon carbide device layer 1304 are doped to about 1x10¹⁷ cm^-3Or higher. At 1x10¹⁷ cm^-3And higher doping levels, the etch rate of silicon carbide may depend on the voltage bias present during photoelectrochemical etching. The etch rate begins to vary more with the doping concentration and is a factor in imparting photoelectrochemical etch selectivity based on the doping type.

Further, the doped silicon carbide device layer 1304 may be, for example, about 100 nanometers or greater in thickness. The silicon device layer below the doped silicon carbide device layer 1304 may be of any desired thickness formed by growth. For example, the layers may be about 50 nanometers to 200 microns thick and have customizable doping concentrations. The nitride layer, such as the AlN layer and the GaN layer, may each have a thickness suitable for a particular semiconductor device.

In this illustrative example, a voltage bias may be applied to the surface of doped layer 1302 through ohmic contacts. Further, the surface of the silicon carbide layer is contacted with an aqueous solution of potassium hydroxide and exposed to light above the band gap energy. In this example, the light may have a wavelength shorter than 390 nanometers.

Turning to fig. 14, an illustration of a cross-sectional view of removal of silicon carbide material is depicted in accordance with an illustrative embodiment. In this illustrative example, substrate thinning is performed by grinding and polishing to remove the silicon carbide material from doped layer 1302, as seen by section 1400 representing the removed silicon carbide material. The polishing can be mechanical polishing, chemical mechanical polishing, or a combination of both. As can be seen in this example, a portion of doped layer 1302 remains after grinding and chemical mechanical polishing.

In fig. 15, an illustration of a cross-sectional view of a doped layer within reach of a silicon carbide device layer is depicted in accordance with an illustrative embodiment. In this illustrative example, the doped layer 1302 is etched using a photoelectrochemical etch process to reach the doped silicon carbide device layer 1304, in this example the doped silicon carbide device layer 1304 is an etch stop layer. Portion 1500 shows the silicon carbide material removed.

Thus, the methods illustrated in fig. 1-15 enable the formation of silicon carbide layers for use in devices having desired characteristics. For example, the silicon carbide device layer may be formed on a wafer scale to provide a desired uniformity of layer thickness. In addition, the silicon carbide device layer may be formed with a reduced level of material damage such that undesirable optical absorption or scattering may be avoided. By these methods, the desired quality of the silicon carbide layer using the device can be obtained on larger dimensions such as wafers compared to the prior art.

Turning next to fig. 16, an illustration of a waveguide-coupled optical resonator and filter is depicted in accordance with an illustrative example. As depicted, waveguide-coupled optical resonator and filter 1600 is a semiconductor device formed on a carrier substrate 1602 with an oxide layer 1604, an aluminum nitride layer 1606, and a silicon carbide layer 1608. The carrier substrate 1602 with the oxide layer 1604, the aluminum nitride layer 1606, and the silicon carbide layer 1608 can be formed using the methods illustrated in fig. 1-8, 9-12, and 13-15.

In this illustrative example, aluminum nitride layer 1606 is in direct contact with silicon carbide layer 1608. In other examples, one or more other layers may be located between the aluminum nitride layer 1606 and the silicon carbide layer 1608.

In this example, the waveguide coupled optical resonator and filter 1600 has three components. As depicted, waveguide coupled optical resonator and filter 1600 includes linear waveguide 1601, linear waveguide 1603, and ring waveguide 1605. In this example, the waveguide coupled optical resonator and filter 1600 may filter selected wavelengths of the light. For example, light traveling through linear waveguide 1601 may enter annular waveguide 1605. The ring waveguide 1605 may deliver light of a selected wavelength or wavelengths to the linear waveguide 1603, which linear waveguide 1603 acts as a filter to deliver light from the linear waveguide 1601 to the linear waveguide 1603.

Referring to FIG. 17, an illustration of a cross-sectional view of a waveguide coupled optical resonator and filter is depicted in accordance with an illustrative embodiment. In this figure, a cross-sectional view of a waveguide coupled optical resonator and filter 1600 taken along line 17-17 in figure 16 is shown. In this example, the oxide layers are bonded to form oxide layer 1604. Thereafter, the aluminum nitride layer 1606 and silicon carbide layer 1608 may be etched to form a structure forming the linear waveguide 1601, the linear waveguide 1603, and the ring waveguide 1605.

Referring to FIG. 18, an illustration of an integrated optical waveguide including quantum memory is depicted in accordance with an illustrative example. As depicted, the quantum memory device 1800 is a semiconductor device formed on a carrier substrate 1802 having an oxide layer 1804, an aluminum nitride region 1806, and a silicon carbide region 1808. In this example, the carrier substrate 1802 having the oxide layer 1804, the aluminum nitride region 1806, and the silicon carbide region 1808 may be formed using the methods illustrated in fig. 1-8, 9-12, and 13-15.

As depicted, aluminum nitride region 1806 has sides 1801 and 1803. Silicon carbide region 1808 has sides 1805 and 1807.

In this example, the quantum memory device 1800 includes a quantum memory 1810 and an integrated optical waveguide 1811. Quantum memory 1810 is coupled to an integrated optical waveguide 1811. Quantum memory 1810 may be formed from defects in a silicon carbide material in silicon carbide region 1808. The defects may be, for example, point defects selected from the group consisting of double vacancies, silicon single vacancies, other vacancy complexes, transition metal ions, or rare earth ions in the silicon carbide region 1808. Quantum memory 1810 may emit photons 1812 depending on the electron spin associated with the defect or color center, and the state in which the photons may be entangled with the electron spin state. Photons 1812 emitted from quantum memory 1810 may travel into integrated optical waveguide 1811.

Referring to FIG. 19, an illustration of a cross-sectional view of an integrated optical waveguide including a quantum memory is depicted in accordance with an illustrative embodiment. In this figure, a cross-sectional view of quantum memory device 1800 taken along line 19-19 in fig. 18 is shown.

Turning to fig. 20-23, illustrations of fabricated waveguide structures are depicted in accordance with one or more illustrative embodiments. These depicted waveguide structures may be formed using the methods illustrated in fig. 1-8, 9-12, and 13-15. These waveguides may also be used in place of the optical waveguide structures depicted in fig. 16 and 18, the cross-sections of which are illustrated in fig. 17 and 19.

Referring to fig. 20, a cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, waveguide 2000 is an example of a strip waveguide that may be formed in the illustrative examples.

In the depicted example, the waveguide 2000 is formed on a carrier substrate 2002. An oxide layer 2004 is located on the carrier substrate 2002. An aluminum nitride layer 2006 is located on the oxide layer 2004 and a silicon carbide region 2008 is located on the aluminum nitride layer 2006. As shown in this figure, silicon carbide region 2008 has been patterned and etched to form waveguide 2000.

As used herein, a region is a layer that does not extend indefinitely. In this example, the regions have defined sides. As depicted, silicon carbide region 2008 has a side 2001 and a side 2003.

Cladding 2010 covers silicon carbide region 2008 and aluminum nitride layer 2006. In this example, cladding 2010 is in direct contact with silicon carbide region 2008 and aluminum nitride layer 2006. The coating 2010 may include a material selected from at least one of air, vacuum, resist, polymer, silicon nitride, silicon dioxide, or some other material. In other words, in some illustrative examples, cladding 2010 may include more than one type of material. In this example, cladding 2010 has a refractive index that is lower than the refractive index of silicon carbide region 2008.

In this illustrative example, the carrier substrate 2002 has a thickness of about 100 μm. In this example, oxide layer 2004 has a thickness of about 3.0 μm. The aluminum nitride layer 2006 has a thickness of about 200nm, and the silicon carbide region 2008 has a thickness of about 300nm and a width of about 1.0 μm. The cladding 2010 has a thickness of about 500nm to about 5.0 μm.

In this illustrative example, the silicon carbide layer may be etched to form silicon carbide regions 2008 while aluminum nitride layer 2006 is not etched. The etching may be performed after the bonding.

The cross-section of the structure of waveguide 2000 depicted in fig. 20 may be used to form a component of a semiconductor structure. For example, the silicon carbide region 2008 may be replicated to form four regions. The two outer regions may each be part of a linear waveguide and the two inner regions may be for a ring waveguide.

Turning next to FIG. 21, another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As depicted, waveguide 2100 is an example of a rib waveguide that may be formed in the illustrative examples.

In this illustrative example, the waveguide 2100 is formed on a carrier substrate 2102. An oxide layer 2104 is located on a carrier substrate 2102. An aluminum nitride layer 2106 is located on the oxide layer 2104, and a silicon carbide layer 2108 is located on the aluminum nitride layer 2106. In addition, rib region 2110 is a silicon carbide region extending from silicon carbide layer 2108. As shown in this figure, the silicon carbide layer 2108 has been patterned and etched to form a waveguide 2100 in the form of a rib waveguide having a rib-shaped region 2110.

Waveguide 2100 also has cladding 2112 covering silicon carbide layer 2108 and rib region 2110. In this example, the coating 2112 is in direct contact with these components. Cladding 2112 has a lower index of refraction than silicon carbide layer 2108 and rib region 2110.

In this illustrative example, the carrier substrate 2102 has a thickness of about 100 μm. In this example, oxide layer 2004 has a thickness of about 3.0 μm.

The aluminum nitride layer 2106 has a thickness of about 200 nm. The silicon carbide layer 2108 has a thickness of about 100 nm. The rib-shaped region 2110 extending from the silicon carbide layer 2008 has a thickness of about 200nm and a width of about 1.0 μm. The coating 2112 has a thickness of about 500nm to about 5.0 μm.

In fig. 22, yet another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, the waveguide 2200 is an example of a buried ridge waveguide structure.

In the depicted example, the waveguide 2200 is formed on a carrier substrate 2202. An oxide layer 2204 is located on the carrier substrate 2202. Gallium nitride region 2212 is located on oxide layer 2204 within cavity 2208 in oxide layer 2204. Aluminum nitride regions 2210 are located on gallium nitride regions 2212 within cavities 2208 in oxide layer 2204. Aluminum nitride region 2210 and gallium nitride region 2212 are examples of a set of group III-nitride regions that may be buried in cavity 2208.

A region is a layer that has defined sides and may be located within another material. In this example, gallium nitride region 2212 has sides 2201 and 2203 in cavity 2208 in oxide layer 2204. Aluminum nitride region 2210 has sides 2205 and sides 2207 in cavity 2208 in oxide layer 2204.

In this example, a silicon carbide layer 2214 is located on the oxide layer 2204 and the aluminum nitride regions 2210. As shown in this figure, the waveguide 2200 is formed by the silicon carbide layer 2214, the aluminum nitride region 2210, and the gallium nitride region 2212 in the cavity 2208 of the oxide layer 2204. Aluminum nitride regions 2210 and gallium nitride regions 2212 form ridges 2220 buried in oxide layer 2204. At least one of the aluminum nitride region 2210 or the gallium nitride region 2212 has a refractive index higher than that of the oxide layer 2204.

As depicted, waveguide 2200 has cladding 2222 covering silicon carbide layer 2214. In this illustrative example, cladding 2222 is in direct contact with silicon carbide layer 2214. The refractive index of the cladding 2222 is lower than the refractive index of the silicon carbide layer 2214.

In this illustrative example, carrier substrate 2202 has a thickness of about 100 μm. In this example, oxide layer 2204 has a thickness of about 3.3 μm. The aluminum nitride layer 2210 has a thickness of about 100nm, and the gallium nitride layer 2212 has a thickness of about 200 nm. The two layers in the cavity 2208 have a width of about 1.0 μm. As depicted, silicon carbide layer 2214 has a thickness of about 200 nm. The coating 2222 has a thickness of about 500nm to about 5.0 μm.

In this example, the aluminum nitride layer and gallium nitride regions are etched to form aluminum nitride regions 2210 and gallium nitride regions 2212. A first oxide layer is formed to bury aluminum nitride region 2210 and gallium nitride region 2212. This first oxide layer is then bonded to a second oxide layer on the carrier substrate 2202. The first oxide layer and the second oxide layer may then be combined to form oxide layer 2204.

In this illustrative example, the semiconductor structure depicted in FIG. 22 may be fabricated using the operations depicted in the illustrative example. For example, the group III nitride layer may be patterned and etched prior to depositing the oxide and wafer bonding. The waveguide structure may be integrated with a lateral (horizontal) diode and doped for active electronics and a depletion layer in the silicon carbide layer 2214. The doped regions may be fabricated by mask implantation followed by annealing, or the substrate (SiC and GaN) may be doped during growth, followed by patterning and etching, or a combination thereof. Application of an electric field to these materials across a p-n junction or between metal contacts can be used to tune the resonant frequency of an optical resonator or the light emission frequency of an embedded single photon emitter.

Referring now to FIG. 23, yet another cross-sectional view of a waveguide is depicted in accordance with an illustrative embodiment. As illustrated, the waveguide 2300 is another example of a buried optical waveguide structure.

In the depicted example, the waveguide 2300 is formed on a carrier substrate 2302. An oxide layer 2304 is located on carrier substrate 2302. A gallium nitride region 2312 is located on the oxide layer 2304 within the cavity 2308 in the oxide layer 2304. An aluminum nitride region 2310 is located on gallium nitride region 2312 within cavity 2308 in oxide layer 2304. Aluminum nitride region 2310 has side 2301 and side 2303. Gallium nitride region 2312 has side 2305 and side 2307. As depicted, aluminum nitride regions 2310 and gallium nitride regions 2312 form ridges 2317 that are buried within cavities 2308 in oxide layer 2304.

In this example, a silicon carbide layer 2314 is located on the oxide layer 2304 and the aluminum nitride region 2310. In addition, a ribbed region 2316 extends from the silicon carbide layer 2314. As shown in this figure, the ribbed region 2316 is a portion of silicon carbide extending from the silicon carbide layer 2314 and may be referred to as a silicon carbide region. As depicted, silicon carbide layer 2314, rib region 2316, aluminum nitride region 2310, and gallium nitride region 2312 within cavity 2308 of oxide layer 2304 form waveguide 2300.

As depicted, the waveguide 2300 has a cladding 2322 that covers the silicon carbide layer 2314 and the ribbed region 2316. As depicted, the cladding 2222 is in direct contact with the silicon carbide layer 2214 and the ribbed region 2316. Cladding 2222 has a lower index of refraction than silicon carbide layer 2214 and rib regions 2316.

In this illustrative example, carrier substrate 2302 has a thickness of about 100 μm. In this example, oxide layer 2304 has a thickness of about 3.3 μm. Aluminum nitride region 2310 has a thickness of about 100nm and gallium nitride region 2312 has a thickness of about 200 nm. These two regions in cavity 2308 have a width of about 1.0 μm. As depicted, silicon carbide layer 2214 has a thickness of about 100 nm. The ribbed region 2316 has a width of about 1.0 μm and a thickness of about 200 nm. Cladding 2322 has a thickness of about 500nm to about 5.0 μm.

The illustrations of the waveguide structures in fig. 20-23 are provided as examples of one type of semiconductor structure that can be fabricated according to one or more illustrative examples. These illustrations are not meant to limit the manner in which other illustrative examples may be implemented.

For example, the thicknesses of the layers and regions illustrated are examples of thicknesses that may be used for thin film implementations. These thicknesses are not meant to limit the thicknesses that may be used in other illustrative examples.

In addition, the number and type of group III nitride layers and regions may be different from those illustrated in fig. 20-23. For example, indium nitride (InN) layers and indium aluminum gallium nitride (InAlGaN) layers may be used in addition to or instead of the depicted aluminum nitride (AlN) and gallium nitride (GaN) layers.

As another example, other types of semiconductor structures may be fabricated in addition to or in place of waveguide structures. For example, the semiconductor structure may include at least one of a superconducting single photon detector, a light emitter, a quantum memory using point defects within a silicon carbide device layer, or other suitable type of component in the semiconductor structure.

Other examples of semiconductor structures having one or more silicon carbide device layers and one or more group III nitride layers that may be fabricated using the operations in one or more illustrative examples include microelectromechanical systems and photonic components, including waveguide-coupled four-port and two-port ring resonators or filters. In still other illustrative examples, the superconducting material may be deposited in a manner that allows the superconducting nanowire single photon detector and logic components to operate with photonic, electrical, and mechanical components at low temperatures.

As another example, for a slot waveguide, the optical mode of the vacuum outside the lower index cladding or substrate can be selected by etching two ridges closely spaced together. The spacing may be, for example, less than a few hundred nanometers. As another example, the oxide (SiO) in the selective regions may be patterned by photolithography and then chemically etched away₂) The suspended waveguide is fabricated from a material stack similar to that depicted in these figures, which will produce an optical spatial mode that will expand more into air or vacuum than into an oxide layer.

Referring next to fig. 24, another example of a silicon carbide substrate having a set of group III nitride layers is depicted in accordance with an illustrative embodiment. In this illustrative example, workpiece 2400 is an example of a layer that may be formed and bonded to a carrier substrate, such as carrier substrate 500 in fig. 5.

In this example, the silicon carbide substrate 2402 in the workpiece 2400 includes a base substrate 2404, a p-type silicon carbide layer 2406, an n-type silicon carbide layer 2408, an undoped silicon carbide layer 2410, and a p-type silicon carbide layer 2412. As depicted, the p-type silicon carbide layer 2406 is a sacrificial layer for performing photoelectrochemical etching. Other silicon carbide layers are examples of silicon carbide device layers that may be used to form semiconductor structures. In this example, the n-type silicon carbide layer 2408 may also serve as an etch stop layer in addition to serving as a device layer.

In this illustrative example, base substrate 2404 has a thickness of about 350 μm. As depicted, the sacrificial layer, p-type silicon carbide layer 2406, has a thickness of about 5 μm. In this example, n-type silicon carbide layer 2408 has a thickness of about 0.1 μm; the undoped silicon carbide layer 2410 has a thickness of about 0.2 μm; and the p-type silicon carbide layer 2412 has a thickness of about 0.1 μm.

As depicted, a group III nitride layer is grown on the p-type silicon carbide layer 2412 in the silicon carbide substrate 2402. These group III nitride layers include an undoped aluminum nitride layer 2414 and an undoped gallium nitride layer 2416. In this illustrative example, the undoped aluminum nitride layer 2414 has a thickness of about 0.1 μm, and the undoped gallium nitride layer 2416 has a thickness of about 0.4 μm.

In the depicted example, an oxide layer 2418 is deposited on the undoped gallium nitride layer 2416. In this example, oxide layer 2418 has a thickness of about 0.2 μm.

Using workpiece 2400, thin films of silicon carbide and group III nitride can be stacked on a material with a lower refractive index (n), such as SiO₂On top of (e.g. SiO respectively)₂Is about 1.4, the n of single crystal AlN/GaN is 2.1/2.3 and the n of 4H-SiC is 2.6. As a result, optical modes in the photonic device may stay within at least one of the silicon carbide or group III nitride layers without radiating or losing optical energy into the underlying bulk substrate material.

Further, the silicon carbide layer in the group III nitride layer depicted in workpiece 2400 may be used to create a p-i-n junction within the silicon carbide material. In this example, the use of the undoped aluminum nitride layer 2414 may be beneficial compared to an exposed surface of SiC or a direct interface between silicon carbide and oxide, and may result in fewer unpassivated interface states (particularly at low temperatures). In illustrative examples, the use of one or more additional group III nitride layers is optional.

An illustration of workpiece 2400 is provided as an example of one manner in which a silicon carbide substrate having a set of group III nitride layers can be implemented. This description is not meant to limit the manner in which other illustrative examples may be implemented.

For example, other illustrative examples may have other numbers of layers and silicon carbide substrates. In some illustrative examples, the layer adjacent to the sacrificial layer may be an undoped layer, rather than a layer having an opposite doping type as the sacrificial layer. In yet another illustrative example, three, five, or some other number of group III nitride layers may be employed. Further, example thicknesses of these layers are provided as examples of thicknesses that may be used with thin film layers. Other thicknesses may be used in other examples.

Turning next to FIG. 25, an illustration of a flowchart of a method for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The method begins by combining a first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers (operation 2500). The silicon carbide substrate has a doped layer.

The method etches a silicon carbide substrate having a doped layer using a photoelectrochemical etch process (operation 2502). The doping layer has a doping level such that the doping layer is removed and the silicon carbide device layer in the silicon carbide substrate remains unetched. In operation 2502, the doped layer is a sacrificial layer that enables formation of a silicon carbide device layer on a substrate, such as a wafer, having at least one of a desired thickness uniformity of the silicon carbide device layer or a desired level of optical performance. In operation 2502, a photoelectrochemical etch is performed on an etched surface, which may be a silicon surface of a silicon carbide material or, for example, a carbon surface of a silicon carbide material. The photoelectrochemical etching may also be performed on the etched surface which is the silicon surface of the silicon carbide material.

The method forms a semiconductor structure using the silicon carbide device layer and the group III nitride layer (operation 2504). After which the method terminates. In this example, the silicon carbide device layer and the group III nitride layer may be thin film layers. The semiconductor structure is selected from at least one of an optical waveguide using point defects within the silicon carbide device layer, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, a photon emitting quantum memory, or some other suitable structure. The semiconductor structure may include a plurality of components. For example, the semiconductor structure may include multiple waveguides of the same type or different types. As another example, a semiconductor structure may include one or more waveguides and quantum memories. These and other components may be selected to provide a desired function or functions of the semiconductor structure.

Referring next to FIG. 26, an illustration of a flowchart of a method for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The method begins by forming a set of group III nitride layers on a silicon carbide substrate (operation 2600). The silicon carbide substrate includes a doped layer. The doped layer has a doping level such that the doped layer is etched using a photoelectrochemical etching process while other portions of the silicon carbide substrate remain unetched. In other illustrative examples, the forming of the set of group III nitride layers may include etching the set of group III nitride layers to form the structure.

The method forms a first oxide layer on the set of group III nitride layers, wherein the set of group III nitride layers is between the first oxide layer and the silicon carbide substrate (operation 2602). The method combines the first oxide layer with a second oxide layer on the carrier substrate to form an oxide layer between the carrier substrate and the group III nitride layer (operation 2604).

The method grinds the silicon carbide substrate (operation 2606). The method stops lapping when a portion of the doped layer in the silicon carbide substrate is exposed (operation 2608). In operation 2608, a portion of the doped exposed layer may be the top of the doped layer or some portion of the doped layer.

The method etches the silicon carbide substrate using a photoelectrochemical etch such that the doped layer is removed and the silicon carbide device layer in the silicon carbide substrate is retained when the portion of the doped layer in the silicon carbide substrate is exposed (operation 2610).

The method forms a semiconductor structure using the silicon carbide device layer and the group III nitride layer (operation 2612). After which the method terminates.

Turning next to FIG. 27, an illustration of a bonded component is depicted in accordance with an illustrative embodiment. The flowchart in FIG. 27 is an example of one implementation for performing operation 2500 in FIG. 25 and operation 2604 in FIG. 26.

The method begins by contacting a first surface of a first oxide layer with a second surface of a second oxide layer (operation 2700). In operation 2700, an intermolecular interaction occurs between the first oxide layer and the second oxide layer. These intermolecular interactions include, for example, at least one of van der waals forces, hydrogen bonding, or strong covalent bonding.

The method anneals the first oxide layer and the second oxide layer while the first surface is in direct contact with the second surface to form an oxide layer between the carrier substrate and the set of group III nitride layers (operation 2702). In this example, the anneal in operation 2702 is optional. After which the method terminates.

Turning to FIG. 28, an illustration of a flowchart of a method for forming a semiconductor structure is depicted in accordance with an illustrative embodiment. The method begins by bonding a first oxide layer located on a silicon carbide substrate with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the silicon carbide substrate (operation 2800).

In operation 2800, a silicon carbide substrate has a doped layer. Further, in one illustrative example, the first oxide layer is in direct contact with the silicon carbide substrate. In another illustrative example, a set of intervening layers, such as a set of group III nitride layers, is located between the first silicon layer and the silicon carbide substrate.

The method etches a silicon carbide substrate having a doped layer using a photoelectrochemical etch process (operation 2802). In operation 2802, the doping level of the doped layer is such that the doped layer is removed and the silicon carbide device layer in the silicon carbide substrate remains unetched.

The method forms a semiconductor structure using a silicon carbide device layer (operation 2804). Other materials may also be used to form the semiconductor structure in operation 2804. For example, the group III layer or region may be formed in this operation. Also, at least one of a cap layer, a metal layer, or a metal region may also be formed to form the semiconductor structure in operation 2804.

The flowcharts and block diagrams in the different depicted embodiments illustrate the architecture, functionality, and operation of some possible implementations of apparatus and methods in the illustrative embodiments. In this regard, each block in the flowchart or block diagrams may represent at least one of a module, segment, function, or portion of an operation or step. For example, one or more blocks may be implemented as instructions in program code, hardware, or a combination of program code and hardware to control a manufacturing facility for manufacturing semiconductor structures. When implemented in hardware, the hardware may take the form of, for example, an integrated circuit fabricated or configured to perform one or more of the operations in the flowchart or block diagram. When implemented as a combination of program code and hardware, the implementation can be in the form of firmware. Each block in the flowchart or block diagrams may be implemented using a dedicated hardware system that performs the different operations or a combination of dedicated hardware and program code executed by dedicated hardware to operate a manufacturing apparatus to manufacture the semiconductor structure.

In some alternative implementations of the illustrative embodiments, one or more functions noted in the block may occur out of the order noted in the figures. For example, in some cases, two blocks shown in succession may be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Also, other blocks may be added in addition to the illustrated blocks in the flowchart or block diagrams.

For example, the bonding performed in operation 2604 is shown as being performed prior to etching the silicon carbide substrate in operation 2610. In other illustrative examples, the incorporation in operation 2604 may occur after the etching occurs in operation 2610. As another example, other dielectrics having desired characteristics, such as a desired dielectric constant, may be used in place of or in addition to the silicon dioxide shown and described in the figures.

Turning now to FIG. 29, an illustration of a block diagram of a product management system is depicted in accordance with an illustrative embodiment. Product management system 2900 is a physical hardware system. In this illustrative example, product management system 2900 includes at least one of a manufacturing system 2902 or a maintenance system 2904.

Manufacturing system 2902 is configured to manufacture products. As depicted, manufacturing system 2902 includes manufacturing apparatus 2906. The fabrication apparatus 2906 includes at least one of a processing apparatus 2908 or an assembly apparatus 2910.

The processing apparatus 2908 is an apparatus for manufacturing a part for forming a product. The tooling apparatus 2908 may be used to manufacture at least one of a metal part, a composite part, a semiconductor, a circuit, a fastener, a rib, a skin panel, a spar, an antenna, or other suitable type of part.

For example, the processing apparatus 2908 may include a machine and a tool. These machines and tools may be at least one of drills, hydraulic presses, furnaces, molds, composite tape laying machines, vacuum systems, lathes, or other suitable types of equipment.

With respect to fabricating semiconductor components, the processing apparatus 2908 may include at least one of an epitaxial reactor, an oxidation system, a diffusion system, an etcher, a cleaner, a bonder, a saw, a wafer saw, an ion implanter, a physical vapor deposition system, a chemical vapor deposition system, a photolithography system, an electron beam lithography system, a plasma etcher, a die attach machine, a wire bonder, a die attach system, a molding apparatus, a hermetic seal machine, an electrical tester, an oven, a soak oven, a UV-cure machine, or other suitable type of apparatus that may be used to fabricate semiconductor structures.

Assembly device 2910 is a device used to assemble parts to form a product such as a chip, an integrated circuit, a computer, an aircraft, or some other product. The assembly device 2910 may also include machinery and tools. The machines and tools may be at least one of a robotic arm, a crawler, a fastener mounting system, a track-based drilling system, or a robot.

In this illustrative example, maintenance system 2904 includes a maintenance device 2912. Maintenance device 2912 may include any device needed to perform maintenance on a product. The maintenance device 2912 may include tools for performing various operations on the parts of the product. These operations may include at least one of disassembling parts, refurbishing parts, inspecting parts, reworking parts, manufacturing replacement parts, or other operations for performing maintenance on the product. These operations may be for routine maintenance, inspection, upgrades, refurbishment, or other types of maintenance operations.

In an illustrative example, maintenance device 2912 may include an ultrasonic inspection device, an X-ray imaging system, a vision system, a drill bit, a crawler, and other suitable devices. In some cases, the maintenance device 2912 may include a tooling device 2908, an assembly device 2910, or both, to produce and assemble parts needed for maintenance.

The product management system 2900 also includes a control system 2914. The control system 2914 is a hardware system, and may also include software or other types of components. The control system 2914 is configured to control the operation of at least one of the manufacturing system 2902 or the maintenance system 2904. In particular, the control system 2914 may control the operation of at least one of the processing device 2908, the assembly device 2910, or the maintenance device 2912.

The hardware in the control system 2914 may be implemented using hardware that may include computers, circuits, networks, and other types of devices. This control may take the form of direct control of manufacturing apparatus 2906. For example, robots, computer controlled machines, and other equipment may be controlled by control system 2914. In other illustrative examples, control system 2914 may manage operations performed by human operator 2916 in the manufacture of a product or in the performance of maintenance. For example, the control system 2914 may assign tasks, provide instructions, display models, or perform other operations to manage the operations performed by the human operator 2916. In these illustrative examples, the various steps described and illustrated for fabricating semiconductor structures using silicon carbide and group III nitride layers may be implemented using control system 2914.

In various illustrative examples, a human operator 2916 may operate at least one of the manufacturing device 2906, the maintenance device 2912, or the control system 2914 to interact with. This interaction may occur to fabricate semiconductor structures and other components of products, such as semiconductor devices or components for products such as aircraft, spacecraft, communication systems, microelectromechanical systems, photonic devices, or superconducting single photon detectors.

Thus, the illustrative examples provide methods, apparatus, and systems for fabricating semiconductor structures. In one illustrative example, a method forms a semiconductor structure. A first oxide layer located on a set of group III nitride layers formed on a silicon carbide substrate is combined with a second oxide layer located on a carrier substrate to form an oxide layer located between the carrier substrate and the set of group III nitride layers. The silicon carbide substrate has a doped layer. A silicon carbide substrate having a doped layer is etched using a photoelectrochemical etching process, wherein the doping level of the doped layer is such that the doped layer is removed and the silicon carbide layer in the silicon carbide substrate remains unetched. A semiconductor structure is formed using the silicon carbide layer and the group III nitride layer.

Furthermore, the method in the illustrative example is suitable for processing large area wafers, e.g., 10cm in area²Or a larger wafer. The illustrative examples are compatible with currently used methods for these types of wafers to produce low loss, high thickness uniformity silicon carbide and group III nitride based crystal structures on low index insulators. This enables the production of active and passive integrated photonic and electronic products from silicon carbide and group III nitrides.

For example, illustrative examples may include a combination of: wafer bonding and then grinding/polishing or chemical mechanical polishing to thin the silicon carbide substrate followed by photoelectrochemical etching from the carbon face of the silicon carbide substrate. The photoelectrochemical etch used in the examples listed flattens the silicon carbide layer to a clean crystal interface by taking advantage of its material selective etch characteristics, resulting in a uniform silicon carbide film thickness.

To facilitate photoelectrochemical etching, an electrode may be attached to another doped layer of the silicon carbide layer located below the surface to be etched or the doped layer to be etched, and a second electrode may be placed in the etching solution. Performing photoelectrochemical etching in this manner provides a different method of producing silicon carbide on insulating films than the techniques currently used. Furthermore, the methods in the illustrative examples can be used to produce sub-micron thick films of silicon carbide and group III nitrides in a manner that preserves the doped layers (e.g., p-i-n junctions) and structures below the exposed silicon carbide surface.

In the illustrative example, the final reconstruction (reconstruction) may take many different forms. For example, but not limiting of, the semiconductor structure may be selected from at least one of an optical waveguide using point defects within a silicon carbide device layer, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory. In other words, the semiconductor structure may include one or more of these devices, and may include multiple devices of the same type.

The description of the different illustrative embodiments has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments in the form disclosed. The different illustrative examples describe components that perform actions or operations. In an illustrative embodiment, a component may be configured to perform the described actions or operations. For example, the structure of a component may have a configuration or design that provides the component with the ability to perform the actions or operations described in the illustrative examples that are believed to be performed by the component. Furthermore, to the extent that the terms "includes," "including," "has," "contains," and variants thereof are used herein, these terms are intended to be inclusive in a manner similar to the term "comprising" as an open transition word without precluding any additional or other elements.

Further, the present disclosure includes embodiments according to the following clauses:

clause 1. a method for forming a semiconductor structure, the method comprising:

(2600) forming a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) comprises a doped layer (106, 904, 1302), and wherein the doped layer (106, 904, 1302) has a doping level such that the doped layer (106, 904, 1302) is etched using a photoelectrochemical etch process while other portions of the silicon carbide substrate (100, 1003) remain unetched;

(2602) forming a first oxide layer (402, 912) on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003);

(2604) bonding the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 2402), between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 2104, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) (600, 1100, 1312, 1604, 1804, 2004, 2204, 2304);

(2606) grinding the silicon carbide substrate (100, 1003);

(2608) stopping the milling when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached;

(2610) etching the silicon carbide substrate (100, 1003) using a photoelectrochemical etch process such that the doped layer (106, 904, 1302) is removed when the portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains; and

(2612) a semiconductor structure is formed using a silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 2. the method of clause 1, wherein combining the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1804, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) occurs after etching the silicon carbide substrate (100, 1003).

Clause 3. the method of any of the preceding clauses, wherein bonding the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1804, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1806, 2006, 2106, 2212, 2310, 2312) occurs after etching the group III nitride layer in the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2212, 2310, 2312).

Clause 4. the method of any of the preceding clauses, wherein bonding the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form the oxide layer (600, 1100, 1312, 1604, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) occurs prior to etching the silicon carbide substrate (100, 1003).

Clause 5. the method of any of the preceding clauses, wherein bonding the first oxide layer (402, 912) with the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 1602, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises:

(2700) contacting a first surface of a first oxide layer (402, 912) with a second surface of the first oxide layer (504, 1002), wherein an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

annealing (2702) the first oxide layer (402, 912) and the first oxide layer (504, 1002) while bringing the first surface into direct contact with the second surface to form an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III nitride layer (200, 908, 910, 1308, 1606, 1310, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 6. the method of any of the preceding clauses, wherein etching the silicon carbide substrate (100, 1003) using a photoelectrochemical etching process such that when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains, comprises:

one of a silicon face and a carbon face of the silicon carbide substrate (100, 1003) is etched using a photoelectrochemical etch process such that when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is exposed, the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains.

Clause 7. the method of any of the preceding clauses, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of a silicon carbide device layer (100, 906) on the wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance.

Clause 8. the method of clause 1, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using a point defect within the silicon carbide device layer (100, 906).

Clause 9. the method of any of the preceding clauses, wherein the silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

Clause 10. the method of clause 1, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

Clause 11. the method of any of the preceding clauses, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

Clause 12. a method for forming a semiconductor structure, the method comprising:

(2800) combining a first oxide layer (402, 912) located on a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 2102, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 908, 904);

(2082) etching a silicon carbide substrate (100, 1003) having a doped layer (106, 904, 1302) using a photoelectrochemical etch process, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched; and

(2804) the semiconductor structure is formed using a silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 13. the method of clause 12, further comprising:

(2606) grinding a silicon carbide substrate (100, 1003) prior to etching the silicon carbide substrate (100, 1003); and

(2608) before etching a silicon carbide substrate (100, 1003), grinding of the silicon carbide substrate (100, 1003) is stopped when a portion of a doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached.

Clause 14. the method of any one of clauses 12-13, further comprising:

(2600) forming the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on a silicon carbide substrate (100, 1003); and

(2602) forming a first oxide layer (402, 912) on the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

Clause 15. the method of any one of clauses 12-14, wherein combining the first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1312, 1604, 1804, 2004, 2104, 1806, 2006, 2106, 2210, 2212, 2310, 2312) located between the carrier substrate (500, 1000, 1314, 1802, 1602, 1806, 2006, 2106, 2210, 2212, 2312) is performed after etching the silicon carbide substrate (100, 1003).

Clause 16. the method of any of clauses 12-15, wherein bonding a first oxide layer (402, 912) to the first oxide layer (504, 1002) on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1802, 2002, 2102, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) occurs after etching the group III nitride layer in the set of group III nitride layers (200, 908, 910, 1310, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 17. the method of any one of clauses 12-16, wherein combining the first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1312, 1604, 1804, 2004, 2104, 1806, 2006, 2106, 2210, 2212, 2310, 2312) located between the carrier substrate (500, 1000, 1314, 1802, 1314, 1602, 1806, 2006, 2106, 2210, 2212, 2312) is performed prior to etching the silicon carbide substrate (100, 1003).

Clause 18. the method of any of clauses 12-17, wherein combining the first oxide layer (402, 912) located on the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on the silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1312, 1604, 1804, 2004, 2104, 2204, 2304) located between the carrier substrate (500, 1000, 1314, 1602, 1802, 1602, 2202, 2302, 2402) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises:

(2700) contacting a first surface of a first oxide layer (402, 912) with a second surface of the first oxide layer (504, 1002), wherein an intermolecular interaction occurs between the first oxide layer (402, 912) and the first oxide layer (504, 1002); and

(2702) annealing the first oxide layer (402, 912) and the first oxide layer (504, 1002) while directly contacting the first surface with the second surface to form an oxide layer (600, 1100, 1312, 1604, 1804) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) and the group III-nitride layer (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 19. the method of any of clauses 12-18, wherein the doped layer (106, 904, 1302) is a sacrificial layer that enables formation of a silicon carbide device layer (100, 906) on the wafer, the silicon carbide device layer (100, 906) having at least one of a desired thickness uniformity or a desired level of optical performance.

Clause 20. the method of any of clauses 12-19, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using a point defect within the silicon carbide device layer (100, 906).

Clause 21. the method of any one of clauses 12-20, wherein the silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

Clause 22. the method of any one of clauses 12-21, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an alumina substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

Clause 23. the method of any one of clauses 12-22, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

Clause 24. a method for forming a semiconductor structure, the method comprising:

(2800) combining a first oxide layer (402, 912) on a silicon carbide substrate (100, 1003) with a first oxide layer (504, 1002) on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1100, 1312, 1604, 1804, 1802, 2002, 2102, 2202, 2302, 2402) between the carrier substrate (500, 1000, 1314, 1602, 1802, 2104, 2204, 2304) and the silicon carbide substrate (100, 1003), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904, 1302);

(2802) etching the silicon carbide substrate (100, 1003) with the doped layer (106, 904, 1302) using a photoelectrochemical etch process, wherein a doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched; and

(2804) forming a semiconductor structure using the silicon carbide device layer (100, 906).

Clause 25. the method of clause 24, wherein etching the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) using a photoelectrochemical etch process comprises:

the carbon face of the silicon carbide substrate (100, 1003) having the doped layer (106, 904, 1302) is etched using a photoelectrochemical etch process, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched.

Clause 26. the method of any one of clauses 24-25, wherein the first oxide layer (402, 912) is in direct contact with the silicon carbide substrate (100, 1003).

Clause 27. the method of any one of clauses 24-26, wherein a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

Clause 28. a product management system (2900), comprising:

a manufacturing device (2914); and

a control system, wherein the control system controls a manufacturing device (2914) to:

combining a first oxide layer (402, 912) located on a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) formed on a silicon carbide substrate (100, 1003) with the first oxide layer (504, 1002) located on a carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) to form an oxide layer (600, 1312, 1100, 1604, 2104, 1310, 2202, 2302, 2402) located between the carrier substrate (500, 1000, 1314, 1602, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) and the set of group III nitride layers (200, 908, 910, 1308, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the silicon carbide substrate (100, 1003) has a doped layer (106, 904);

etching a silicon carbide substrate (100, 1003) having a doped layer (106, 904, 1302) using a photoelectrochemical etch process, wherein the doping level of the doped layer (106, 904, 1302) is such that the doped layer (106, 904, 1302) is removed and the silicon carbide device layer (100, 906) in the silicon carbide substrate (100, 1003) remains unetched; and

a semiconductor structure is formed using a silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 29. the product management system (2900) of clause 28, wherein the control system controls the manufacturing device (2914) to further include:

grinding the silicon carbide substrate (100, 1003) prior to etching the silicon carbide substrate (100, 1003); and

stopping the lapping of the silicon carbide substrate (100, 1003) when a portion of the doped layer (106, 904, 1302) in the silicon carbide substrate (100, 1003) is reached prior to etching the silicon carbide substrate (100, 1003).

Clause 30. the product management system (2900) of any of clauses 28-29, wherein the control system controls a manufacturing device (2914) to:

forming the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the silicon carbide substrate (100, 1003); and

forming a first oxide layer (402, 912) on the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312), wherein the set of group III-nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the first oxide layer (402, 912) and the silicon carbide substrate (100, 1003).

Clause 31. the product management system (2900) of any of clauses 28-30, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, an optical resonator, or a photon emitting quantum memory using a point defect within the silicon carbide device layer (100, 906).

Clause 32. the product management system (2900) of any of clauses 28-31, wherein the silicon carbide device layer (100, 906) and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

Clause 33. the product management system (2900) of any of clauses 28-32, wherein the carrier substrate (500, 1000, 1314, 1602, 1802, 2002, 2102, 2202, 2302, 2402) is one of a silicon carbide substrate (100, 1003), a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

Clause 34. the product management system (2900) of any of clauses 28-33, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) includes at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

Clause 41, a semiconductor structure, comprising:

a substrate (500, 1000, 1314, 1602, 1802);

an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on the substrate (500, 1000, 1314, 1602, 1802);

a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304); and

a set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on the set of group III nitride layers (200).

Clause 42. the semiconductor structure of clause 41, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) is a set of group III nitride regions (2210, 2212).

Clause 43. the semiconductor structure of clause 42, wherein the set of group III-nitride regions (2210, 2212) is buried within a cavity (2208) in the oxide layer (600).

Clause 44. the semiconductor structure of clause 43, further comprising:

a cladding layer (2222) on the set of silicon carbide layers (2214), wherein the refractive index of the cladding layer (2222) is lower than the refractive index of the set of silicon carbide layers (2224).

Clause 45. the semiconductor structure of any one of clauses 41-44, wherein the set of silicon carbide layers (100, 906, 1306) is a set of silicon carbide regions (2008, 2110, 2316).

Clause 46. the semiconductor structure of clause 45, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) is a set of group III nitride regions.

Clause 47. the semiconductor structure of clause 46, further comprising:

defects in the silicon carbide material in the set of silicon carbide layers (1808).

Clause 48. the semiconductor structure of clause 47, wherein the defect is one of a vacancy double, a silicon vacancy, an additional vacancy complex, a transition metal ion, and a rare earth ion.

Clause 49. the semiconductor structure of clause 45, wherein the set of silicon carbide regions (2008, 2110, 2316) form a waveguide.

Clause 50 the semiconductor structure of clause 49, further comprising:

a cladding (2010, 2112, 2322) on the set of silicon carbide regions (2008, 2110, 2316), wherein a refractive index of the cladding (2010, 2112, 2322) is lower than a refractive index of the set of silicon carbide regions (2008, 2110, 2316).

Clause 51 the semiconductor structure of clause 50, wherein the capping layer (2010, 2112, 2322) comprises a material selected from at least one of air, vacuum, resist, polymer, silicon dioxide, or silicon nitride.

Clause 52. the semiconductor structure of clause 51, wherein the set of silicon carbide layers (100, 906, 1306) includes a silicon carbide layer (2108, 2314) and a silicon carbide region (2110, 2316) extending from the silicon carbide layer (2108).

Clause 53 the semiconductor structure of clause 52, further comprising:

a cladding (2112, 2322) on the silicon carbide layer (2108) and the silicon carbide region (2110, 2316), wherein the refractive index of the cladding (2112, 2322) is lower than the refractive index of the silicon carbide layer (2108) and the silicon carbide region (2008, 2316).

Clause 54. the semiconductor structure of clause 51, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is in direct contact with the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

Clause 55. the semiconductor structure of clause 51, wherein the set of silicon carbide layers is in direct contact with the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312).

Clause 56 the semiconductor structure of clause 51, wherein the substrate (500, 1000, 1314, 1602, 1802) is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

Clause 57. the semiconductor structure of clause 51, wherein the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) comprises at least one of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and indium aluminum gallium nitride (InAlGaN).

Clause 58 the semiconductor structure of clause 51, wherein the set of silicon carbide layers and the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) are thin film layers.

Clause 59 the semiconductor structure of clause 51, wherein the semiconductor structure is selected from at least one of an optical waveguide, a slot waveguide, a ridge waveguide, a rib waveguide, a buried optical waveguide, a suspended waveguide, or an optical resonator.

Clause 60. a semiconductor structure, comprising:

a substrate (500, 1000, 1314, 1602, 1802);

an oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) on a substrate (500, 1000, 1314, 1602, 1802); and

a set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on a substrate (500, 1000, 1314, 1602, 1802).

Clause 61. the semiconductor structure of clause 60, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) on the substrate (500, 1000, 1314, 1602, 1802) is in direct contact with the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304).

Clause 62. the semiconductor structure of any one of clauses 60-61, further comprising:

a set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) on the oxide layer (600), such that the set of group III nitride layers (200, 908, 910, 1308, 1310, 1606, 1806, 2006, 2106, 2210, 2212, 2310, 2312) is located between the oxide layer (600, 1100, 1312, 1604, 1804, 2004, 2104, 2204, 2304) and the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314).

Clause 63. the semiconductor structure of any one of clauses 60-62, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a set of silicon carbide regions (2008, 2110, 2316).

Clause 64. the semiconductor structure of any one of clauses 60-63, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) includes a silicon carbide layer (2108, 2314) and a silicon carbide region (2110, 2316) extending from the silicon carbide layer.

Clause 65. the semiconductor structure of clause 64, further comprising:

a cladding (2112, 2322) on the silicon carbide layer (2108) and the silicon carbide region (2110, 2316), wherein the refractive index of the cladding (2112, 2322) is lower than the refractive index of the silicon carbide layer (2108, 2314) and the silicon carbide region (2110, 2316).

Clause 66. the semiconductor structure of clause 65, wherein the capping layer (2112, 2322) comprises a material selected from at least one of air, vacuum, resist, polymer, silicon dioxide, or silicon nitride.

Clause 67. the semiconductor structure of any one of clauses 60-66, wherein the set of silicon carbide layers (100, 906, 1306, 2008, 2108, 2214, 2314) is a set of thin film layers.

The semiconductor structure of claim 60, wherein the substrate (500, 1000, 1314, 1602, 1802) is one of a silicon carbide substrate, a silicon substrate, an aluminum oxide substrate, a gallium oxide substrate, a silicon dioxide substrate, an aluminum nitride substrate, and a gallium nitride substrate.

Many modifications and variations will be apparent to those of ordinary skill in the art. Moreover, different illustrative embodiments may provide different features than other desirable embodiments. The embodiment or embodiments selected are chosen and described in order to best explain the principles of the embodiments, the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.