阅读说明：本技术 一种接受任意电容负载的推挽快速响应ldo (Push-pull quick response LDO (low dropout regulator) capable of receiving any capacitive load ) 是由 陈松 于 2021-08-20 设计创作，主要内容包括：一种接受任意电容负载的推挽快速响应LDO,所述LDO包括依次连接的跨导电路、推挽电流放大级电路、增益级电路和驱动级电路,以及连接于所述推挽电流放大级电路的输入端和所述驱动级电路的输出端之间的第一反馈电容。本申请能够接受任意电容负载,通用性强,稳定性高；且具有优秀的瞬态响应和超低的静态功耗；并能够以非常紧凑和简单的结构来实现。(The LDO comprises a transconductance circuit, a push-pull current amplification stage circuit, a gain stage circuit, a driving stage circuit and a first feedback capacitor, wherein the transconductance circuit, the push-pull current amplification stage circuit, the gain stage circuit and the driving stage circuit are sequentially connected, and the first feedback capacitor is connected between the input end of the push-pull current amplification stage circuit and the output end of the driving stage circuit. The method and the device can accept any capacitance load, and have strong universality and high stability; the transient response is excellent, and the static power consumption is ultralow; and can be realized in a very compact and simple structure.)

1. The push-pull fast response LDO capable of receiving any capacitive load is characterized by comprising a transconductance circuit, a push-pull current amplification stage circuit, a gain stage circuit, a driving stage circuit and a first feedback capacitor, wherein the transconductance circuit, the push-pull current amplification stage circuit, the gain stage circuit and the driving stage circuit are sequentially connected, and the first feedback capacitor is connected between the input end of the push-pull current amplification stage circuit and the output end of the driving stage circuit.

2. The LDO of claim 1, wherein the LDO further comprises a second feedback capacitor connected between the gain stage circuit and the output of the driver stage circuit.

3. The LDO of claim 2, wherein the LDO further comprises a third feedback capacitor connected between the output of the gain stage circuit and the output of the driver stage circuit.

4. The LDO of claim 3, wherein the third feedback capacitor is further connected in series with a resistor Rz, wherein the resistor Rz provides a zero.

5. The LDO of claim 1, wherein the push-pull current amplification stage circuit comprises a push-current amplification stage circuit and a pull-current amplification stage circuit connected in parallel, wherein outputs of the transconductance circuit are connected to inputs of the push-current amplification stage circuit and the pull-current amplification stage circuit, respectively, and wherein outputs of the push-current amplification stage circuit and the pull-current amplification stage circuit are commonly input to the gain stage circuit.

6. The LDO of any of claims 1-5, wherein the LDO is an off-chip capacitor LDO, or wherein the LDO is an off-chip capacitor.

7. A push-pull fast response LDO accepting any capacitive load, comprising PMOS transistors MP1, MP2, MP3 and NMOS transistors MN4, MN5, MN6, MN 7; the gate of the PMOS transistor MP1 is connected to the reference voltage V_refThe gate of the PMOS transistor MP2 is connected to the feedback voltage V_fbThe source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are connected with the drain of a PMOS transistor MP3, and the source of the PMOS transistor MP3 is connected with a power tube MP 17; the drain electrode of the PMOS transistor MP1 and the drain electrode of the PMOS transistor MP2 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN4 and the drain electrode of an NMOS transistor MN5, the source electrode of the NMOS transistor MN4 and the source electrode of the NMOS transistor MN5 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN6 and the drain electrode of an NMOS transistor MN7, and the source electrode of the NMOS transistor MN6 and the source electrode of an NMOS transistor MN7 are grounded; a node N1 is arranged between the drain electrode of the PMOS transistor MP1 and the drain electrode of the NMOS transistor MN 4; a node N2 is arranged between the drain electrode of the PMOS transistor MP2 and the drain electrode of the NMOS transistor MN 5; the node N1 is connected with the node N2, a resistor R1 is connected between the node N1 and the node N2, a node N3 is arranged between the node N1 and the resistor R1, and the node N3 is connected with the output voltage V through a first feedback capacitor Cc1_OUT(ii) a The gate of the NMOS transistor MN6 is connected to the gate of the NMOS transistor MN7, and a node between the gate connection lines is connected to the node N3.

8. The LDO circuit of claim 7, further comprising a PMOS transistor MP9, a PMOS transistor MP10, an NMOS transistor MN11, an NMOS transistor MN12 connected in sequence; the PMOS transistor MP13, the PMOS transistor MP14, the NMOS transistor MN15 and the NMOS transistor MN16 are connected in sequence; the gate of the NMOS transistor MN12 is connected to the node N1; the gate of the NMOS transistor MN16 is connected to the node N2.

9. The LDO circuit of claim 8, wherein the LDO circuit further comprises a second feedback capacitor and a third feedback capacitor, the second feedback capacitor comprises a first sub-feedback capacitor Cc2p and a second sub-feedback capacitor Cc2n, one end of the first sub-feedback capacitor Cc2p is connected between the drain of the PMOS transistor MP13 and the source of the PMOS transistor MP14, and the other end of the first sub-feedback capacitor Cc2p is connected to an output voltage V_OUT(ii) a One end of the second sub-feedback capacitor Cc2n is connected between the source of the NMOS transistor MN15 and the drain of the NMOS transistor MN16, and the other end of the second sub-feedback capacitor Cc2n is connected to the output voltage V_OUT(ii) a One end of the third feedback capacitor Cc3 is connected in series with a resistor Rz, one end of the resistor Rz not connected with the third feedback capacitor Cc3 is connected to a node O2 between the drain of the PMOS transistor MP14 and the drain of the NMOS transistor MN15, and the other end of the third feedback capacitor Cc3 is connected to the output voltage V_OUT。

10. The LDO of claim 8, wherein the LDO further comprises an Iboost branch comprising at least a plurality of PMOS transistors and a plurality of NMOS transistors connected in series.

Technical Field

The invention relates to the technical field of integrated circuits, in particular to the field of CMOS analog integrated circuit design, and specifically relates to a circuit design of a push-pull quick response Low dropout Regulator (LDO for short) receiving any capacitive load.

Background

In the current development of the integrated circuit industry, a power management chip plays an extremely important role and can provide stable voltage for the rest circuits of the system. LDO is called for short for low dropout linear regulator chip belongs to power management chip, and its apparent advantage has: the power supply module is simple in structure, fast in response, low in output noise, low in static power consumption, small in circuit scale and the like, and therefore is an almost necessary key power supply module in a digital-analog hybrid chip.

The output pole and the dominant pole of the error amplifier are too close to each other under heavy load conditions of the ordinary LDO, so that the circuit is easy to be unstable. The conventional solution is to connect an external off-chip capacitor, and the design of the LDO connected with the external off-chip capacitor is relatively simple and mature, however, this design needs external discrete components, resulting in a reduction in the circuit integration level. Therefore, in recent years, the design of a non-off-chip capacitor LDO (Cap-less LDO) has become a hot spot of research at home and abroad.

The LDO without the off-chip capacitor integrates the capacitor in the LDO circuit, and in the actual circuit design, the LDO without the off-chip capacitor is more difficult and diversified, and mainly has the following aspects:

1. because the capacitor of the LDO without the off-chip capacitor is integrated in the chip, when the LDO is applied to chips with different scales, the LDO needs to be capable of accepting load capacitors in different chips and has good LDO loop stability because the size of the load capacitor in the chip is uncertain (the typical load capacitor in the chip is usually between 100pF and 1 uF);

2. when the load current changes rapidly (the typical load current change speed is 0 to +/-200 mA in 1 us), the LDO needs to have as high a transient response speed as possible so that the output thereof can be rapidly stabilized within an acceptable voltage ripple range, and the maximum change of the output voltage at this time should not exceed +/-10%;

3. at 0 load, LDO static power consumption requirements need to guarantee Iq <30 uA.

However, the LDO in the prior art cannot meet the requirements of the above aspects, so the application provides a push-pull fast response LDO that accepts any capacitive load, and the LDO can meet the requirements of the above aspects at the same time to overcome the technical problems in the prior art.

Disclosure of Invention

In order to overcome the defects of the prior art, the application provides a push-pull quick response low dropout regulator receiving any capacitance load, and the technical scheme of the invention is as follows:

the LDO comprises a transconductance circuit, a push-pull current amplification stage circuit, a gain stage circuit, a driving stage circuit and a first feedback capacitor, wherein the transconductance circuit, the push-pull current amplification stage circuit, the gain stage circuit and the driving stage circuit are sequentially connected, and the first feedback capacitor is connected between the input end of the push-pull current amplification stage circuit and the output end of the driving stage circuit.

The LDO further comprises a second feedback capacitor connected between the gain stage circuit and the output end of the driver stage circuit.

The LDO further comprises a third feedback capacitor connected between the output end of the gain stage circuit and the output end of the driver stage circuit.

The third feedback capacitor is also connected with a resistor Rz in series, and the resistor Rz provides a zero point.

The push-pull current amplification stage circuit comprises a push-current amplification stage circuit and a pull-up current amplification stage circuit which are connected in parallel, the output of the transconductance circuit is respectively connected to the input of the push-current amplification stage circuit and the input of the pull-up current amplification stage circuit, and the output of the push-current amplification stage circuit and the output of the pull-up current amplification stage circuit are jointly input to the gain stage circuit.

The LDO is a LDO without an off-chip capacitor, or the LDO is externally connected with an off-chip capacitor.

The LDO comprises PMOS transistors MP1, MP2, MP3 and NMOS transistors MN4, MN5, MN6 and MN 7; the gate of the PMOS transistor MP1 is connected to the reference voltage V_refThe gate of the PMOS transistor MP2 is connected to the feedback voltage V_fbThe source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are connected with the drain of a PMOS transistor MP3, and the source of the PMOS transistor MP3 is connected with a power tube MP 17; the drain electrode of the PMOS transistor MP1 and the drain electrode of the PMOS transistor MP2 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN4 and the drain electrode of an NMOS transistor MN5, the source electrode of the NMOS transistor MN4 and the source electrode of the NMOS transistor MN5 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN6 and the drain electrode of an NMOS transistor MN7, and the source electrode of the NMOS transistor MN6 and the source electrode of an NMOS transistor MN7 are grounded; a node N1 is arranged between the drain electrode of the PMOS transistor MP1 and the drain electrode of the NMOS transistor MN 4; a node N2 is arranged between the drain electrode of the PMOS transistor MP2 and the drain electrode of the NMOS transistor MN 5; the node N1 is connected with the node N2, a resistor R1 is connected between the node N1 and the node N2, a node N3 is arranged between the node N1 and the resistor R1, and the node N3 is connected with the output voltage V through a first feedback capacitor Cc1_OUT(ii) a The gate of the NMOS transistor MN6 is connected to the gate of the NMOS transistor MN7, and a node between the gate connection lines is connected to the node N3.

The LDO circuit further comprises a PMOS transistor MP9, a PMOS transistor MP10, an NMOS transistor MN11 and an NMOS transistor MN12 which are connected in sequence; the PMOS transistor MP13, the PMOS transistor MP14, the NMOS transistor MN15 and the NMOS transistor MN16 are connected in sequence; the gate of the NMOS transistor MN12 is connected to the node N1; the gate of the NMOS transistor MN16 is connected to the node N2.

The LDO circuit further comprises a second feedback capacitor and a third feedback capacitor, the second feedback capacitor comprises a first sub-feedback capacitor Cc2p and a second sub-feedback capacitor Cc2n, one end of the first sub-feedback capacitor Cc2p is connected between the drain of the PMOS transistor MP13 and the source of the PMOS transistor MP14, and the other end of the first sub-feedback capacitor Cc2p is connected to an output voltage V_OUT(ii) a One end of the second sub-feedback capacitor Cc2n is connected between the source of the NMOS transistor MN15 and the drain of the NMOS transistor MN16, and the other end of the second sub-feedback capacitor Cc2n is connected to the output voltage V_OUT(ii) a One end of the third feedback capacitor Cc3 is connected in series with a resistor Rz, one end of the resistor Rz not connected with the third feedback capacitor Cc3 is connected to a node O2 between the drain of the PMOS transistor MP14 and the drain of the NMOS transistor MN15, and the other end of the third feedback capacitor Cc3 is connected to the output voltage V_OUT。

The LDO further comprises an Iboost branch circuit, wherein the Iboost branch circuit at least comprises a plurality of PMOS transistors and a plurality of NMOS transistors which are connected in sequence.

The method and the device can accept any capacitance load, and have strong universality and high stability; the transient response is excellent, and the static power consumption is ultralow; and can be realized in a very compact and simple structure, other advantageous effects of the present application can be obtained from the specific embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic connection diagram of a push-pull fast response LDO circuit accepting an arbitrary capacitive load according to a first embodiment of the present application;

FIG. 2 is a circuit diagram of a push-pull fast response LDO circuit accepting an arbitrary capacitive load according to a second embodiment of the present application;

FIG. 3 shows simulation results of LDOs of the second embodiment of the present application without external capacitors;

fig. 4 is a circuit diagram of an improved push-pull fast response LDO circuit accepting an arbitrary capacitive load according to a third embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that in the description of the present application, the terms "first", "second", etc. are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings.

First embodiment

Referring to fig. 1, fig. 1 is a schematic connection diagram of a push-pull fast response LDO circuit accepting an arbitrary capacitive load according to the present application. As shown in fig. 1, the LDO includes a transconductance circuit, a push-pull current amplifier circuit, a gain circuit, a driver circuit, a first feedback capacitor connected between an input terminal of the push-pull current amplifier circuit and an output terminal of the driver circuit, a second feedback capacitor connected between the gain circuit and the output terminal of the driver circuit, and a third feedback capacitor connected between the output terminal of the gain circuit and the output terminal of the driver circuit, which are connected in sequence.

The push-pull current amplification stage circuit comprises a push-pull current amplification stage circuit and a pull-pull current amplification stage circuit. One end of the transconductance circuit is respectively connected with the push current amplification stage circuit and the pull current amplification stage circuit. The output of the push current amplifier stage circuit and the output of the pull current amplifier stage circuit are connected to the gain stage circuit together.

One end of the transconductance circuit, which is not connected with the push-pull current amplification stage circuit, is connected with a reference voltage V_refAnd receiving a feedback voltageV_fb. And one end of the driving stage circuit, which is not connected with the gain stage circuit, is connected with the output voltage. And a resistor and a capacitor which are connected in parallel are also connected between the output end of the driving stage circuit and the ground.

The LDO comprises a three-stage amplifier, and the transconductance circuit and the push-pull current amplification stage circuit form a first-stage amplifier structure of the LDO; the gain stage circuit forms a second stage amplifier structure of the LDO, and the driver stage circuit forms a third stage amplifier structure of the LDO.

In the prior art, due to circuit structure or stability limitation, a push-pull amplifier stage circuit and a feedback capacitor are not arranged in a feed-forward path of an LDO main amplifier or not arranged in the feed-forward path of the LDO main amplifier. The feedback access point positions of the push-pull amplifier stage circuit and the first feedback capacitor are arranged in the feed-forward path of the main amplifier, so that the power consumption of the circuit can be greatly reduced, the circuit structure is simple, and the complex circuit structure in the prior art is avoided. In practical application, no matter which direction the output voltage changes rapidly, the voltage of feedback passes through first feedback electric capacity extremely push away current amplifier stage circuit with it constitutes to pull current amplifier stage circuit push away amplifier stage circuit, the homoenergetic turns on or closes fast the power tube of driver stage circuit makes quick response to the change of output voltage for the LDO of this application has the higher transient response speed than prior art. In addition, the first feedback capacitor is a Nested-Miller feedback capacitor which is used for improving the loop stability and the transient response speed of the LDO circuit. Further, this application still increases second feedback electric capacity and third feedback electric capacity in the LDO circuit, first feedback electric capacity second feedback electric capacity and third feedback electric capacity form Nested-Miller feedback electric capacity network, and the three constitutes Nested-Miller compensation, through first feedback electric capacity, second feedback electric capacity and third feedback electric capacity, guaranteed that the LDO circuit all has good loop stability and transient response speed under any load capacitance, and can provide the feedback steady output of big signal.

Second embodiment

Further, fig. 2 provides a specific LDO circuit diagram corresponding to the LDO connection diagram shown in fig. 1. Those skilled in the art can understand that, under the condition of conforming to the LDO connection diagram shown in fig. 1, the structures of the circuit components, such as the transconductance circuit, the push-pull current amplification stage circuit, the gain stage circuit, the driving stage circuit, and the number of capacitors, may be changed accordingly.

Referring to fig. 2, the LDO includes PMOS transistors MP1, MP2, MP3, MP8, and NMOS transistors MN4, MN5, MN6, MN 7. The gate of the PMOS transistor MP1 is connected to the reference voltage V_refThe gate of the PMOS transistor MP2 is connected to the feedback voltage V_fbThe source of the PMOS transistor MP1 and the source of the PMOS transistor MP2 are connected to the drain of the PMOS transistor MP 3. The drain electrode of the PMOS transistor MP1 and the drain electrode of the PMOS transistor MP2 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN4 and the drain electrode of an NMOS transistor MN5, the source electrode of the NMOS transistor MN4 and the source electrode of the NMOS transistor MN5 are respectively and correspondingly connected with the drain electrode of an NMOS transistor MN6 and the drain electrode of an NMOS transistor MN7, and the grid electrode of the NMOS transistor MN6 is connected with the grid electrode of an NMOS transistor MN 7. The gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP 8.

The LDO circuit further comprises a PMOS transistor MP9, a PMOS transistor MP10, an NMOS transistor MN11 and an NMOS transistor MN12 which are connected in sequence; and a PMOS transistor MP13, a PMOS transistor MP14, an NMOS transistor MN15, and an NMOS transistor MN16 connected in this order. Wherein the drain of the PMOS transistor MP9 is connected to the source of the PMOS transistor MP10, the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN11, and the source of the NMOS transistor MN11 is connected to the drain of the NMOS transistor MN 12; and the drain of the PMOS transistor MP13 is connected to the source of the PMOS transistor MP14, the drain of the PMOS transistor MP14 is connected to the drain of the NMOS transistor MN15, and the source of the NMOS transistor MN15 is connected to the drain of the NMOS transistor MN 16.

The gate of the PMOS transistor MP9 is connected with the gate of the PMOS transistor MP 13; the gate of the PMOS transistor MP9 is also connected to the drain of the PMOS transistor MP 10; the gate of the PMOS transistor MP10 and the gate of the PMOS transistor MP14Connecting the poles; the gate of the NMOS transistor MN11, the gate of the NMOS transistor MN4, the gate of the NMOS transistor MN5 and the gate of the NMOS transistor MN15 are connected; the gate of the NMOS transistor MN12 is connected to a node N1 between the drain of the PMOS transistor MP1 and the drain of the NMOS transistor MN 4; the gate of the NMOS transistor MN16 is connected to a node N2 between the drain of the PMOS transistor MP2 and the drain of the NMOS transistor MN 5; a node N1 is connected with a node N2, a resistor R1 is connected between the two, a resistor R1 is used for controlling the gain, and a node N3 between a node N1 and a resistor R1 is connected with the output voltage V through a first feedback capacitor Cc1_OUT. The node N3 is also connected between the gate of the NMOS transistor MN6 and the gate of NMOS transistor MN 7.

The drain of the PMOS transistor MP8 is connected to a current source, which is grounded.

The source of the NMOS transistor MN12, the source of the NMOS transistor MN6, the source of the NMOS transistor MN7 and the source of the NMOS transistor MN16 are all grounded. The drain of the PMOS transistor MP8 is also connected to the gate. The source of the PMOS transistor MP8, the source of the PMOS transistor MP9, the source of the PMOS transistor MP3, and the source of the PMOS transistor MP13 are all connected to the power transistor MP 17.

The second feedback capacitance includes a first sub-feedback capacitance Cc2p and a second sub-feedback capacitance Cc2 n. Wherein one end of the first sub-feedback capacitor Cc2p is connected between the drain of the PMOS transistor MP13 and the source of the PMOS transistor MP 14. One end of the second sub-feedback capacitor Cc2n is connected between the source of the NMOS transistor MN15 and the drain of the NMOS transistor MN 16.

One end of the third feedback capacitor Cc3 is connected in series with a resistor Rz that is used to provide a zero. One end of the resistor Rz, which is not connected to the third feedback capacitor Cc3, is connected to a node O2 between the drain of the PMOS transistor MP14 and the drain of the NMOS transistor MN 15.

A power transistor MP17, the other end of the first sub-feedback capacitor Cc2p, the other end of the third feedback capacitor Cc3, one end of the first feedback capacitor Cc1 not connected to the node N3, and the other end of the second sub-feedback capacitor Cc2NAre connected and are all connected to an output voltage V_OUT。

The second sub-feedback capacitor Cc2n is connected with the output voltage V_OUTThe other end of the variable resistor is also connected with one end of a variable resistor, and the other end of the variable resistor is grounded.

The gate of the power transistor MP17 is connected between the resistor Rz and the node O2.

The PMOS transistor MP13 and the NMOS transistor MN16 are used to provide the main dc gain. The PMOS transistor MP17 is a power transistor for providing a load current.

In the circuit, when large-signal push-pull feedback is realized, when the load current suddenly increases, the current is coupled to the transimpedance amplifier formed by the resistor R1 and the NMOS transistor MN7 through the first feedback capacitor Cc1, and is amplified through the NMOS transistor MN16, so that the discharge speed of the node O2 is increased, and the power tube is quickly turned on.

When the load current suddenly becomes small, the current is coupled to a current multiplier consisting of an NMOS transistor MN6, an NMOS transistor MN12, a PMOS transistor MP9 and a PMOS transistor MP13 through the first feedback capacitor Cc1, the charging speed of a node O2 is increased, and the power tube is quickly turned off.

Fig. 3 shows simulation results of the LDO circuit according to the second embodiment, and it can be seen from fig. 3 that the LDO circuit has a transient response speed and loop stability that are significantly better than those of the prior art when the load current suddenly changes.

This application is when load current sudden change, can make LDO circuit's output more stable, the great output of alleviating LDO circuit changes the upper and lower sudden change that arouses along with the load, the loop stability of LDO circuit has been improved, and above-mentioned LDO circuit has faster transient response speed and lower consumption relative prior art, fine solution LDO among the prior art be difficult to have the problem of super low-power consumption, quick transient response, circuit stability under different loads concurrently.

Third embodiment

Referring to fig. 4, in fig. 4, an Iboost (current amplification) branch is added to the LDO circuit shown in fig. 2, and only the added circuit portion is described below, and the rest of the circuit portion same as that in fig. 2 can be referred to the description of the second embodiment. The Iboost branch comprises a PMOS transistor MP18, a PMOS transistor MP19, an NMOS transistor MN20 and an NMOS transistor MN21 which are connected in sequence; and a PMOS transistor MP22, a PMOS transistor MP23, an NMOS transistor MN24, and an NMOS transistor MN25 connected in this order. Wherein the drain of the PMOS transistor MP18 is connected to the source of the PMOS transistor MP19, the drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN20, and the source of the NMOS transistor MN20 is connected to the drain of the NMOS transistor MN 21; and the drain of the PMOS transistor MP22 is connected to the source of the PMOS transistor MP23, the drain of the PMOS transistor MP23 is connected to the drain of the NMOS transistor MN24, and the source of the NMOS transistor MN24 is connected to the drain of the NMOS transistor MN 25.

The source of the PMOS transistor MP18 and the source of the PMOS transistor MP22 are both connected to the power transistor MP 17.

The gate of the PMOS transistor MP18, the gate of the PMOS transistor MP3, and the gate of the PMOS transistor MP8 are connected.

The gate of the PMOS transistor MP19 is connected to the reference voltage V_ref。

The gates of the NMOS transistor MN24, the NMOS transistor MN20, the NMOS transistor MN15, the NMOS transistor MN5, the NMOS transistor MN4 and the NMOS transistor MN11 are mutually connected.

The gates of the NMOS transistor MN21 and the NMOS transistor MN25 are connected to each other.

A node on the gate connection line of the NMOS transistors MN21, MN25 is also connected between the drain of the PMOS transistor MP19 and the drain of the NMOS transistor MN 20.

The gate of the PMOS transistor MP22, the gate of the PMOS transistor MP13, and the gate of the PMOS transistor MP9 are connected.

The gate of the PMOS transistor MP23, the gate of the PMOS transistor MP14, and the gate of the PMOS transistor MP10 are connected.

The source of the NMOS transistor MN21 and the source of the NMOS transistor MN25 are both grounded.

The first sub-feedback capacitor Cc2p is not connected with the output voltage V_OUTIs connected between the drain of the PMOS transistor MP22 and the source of the PMOS transistor MP 23.

One end of the resistor Rz, which is not connected to the third feedback capacitor Cc3, is connected between the drain of the PMOS transistor MP23 and the drain of the NMOS transistor MN 24.

The second sub-feedback capacitor Cc2n is not connected with the output voltage V_OUTIs connected between the source of the NMOS transistor MN24 and the drain of NMOS transistor MN 25.

The drain of the PMOS transistor MP14 is also connected to the drain of the PMOS transistor MP 23.

Compared with the LDO circuit structure shown in fig. 2, after the Iboost branch is added in fig. 4, the amplification factor of the PMOS transistor MP9 and the current mirror of the PMOS transistor MP22 is increased, so that the charging capability of the node O2 is enhanced, and the overshoot phenomenon of the input voltage when the load current suddenly changes can be further reduced. In addition, the transient response speed of the circuit and the stability of the LDO circuit can be further enhanced after the Iboost branch circuit is added.

Compared with the prior art, the LDO circuit provided by the application can accept any capacitance load, and is strong in universality and high in stability; the transient response is excellent, and the static power consumption is ultralow; and can be realized with a very compact and simple structure, having great application value.

Through the above description of the embodiments, those skilled in the art will clearly understand that the present application can be implemented by hardware, and also by software plus a necessary general hardware platform.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.