阅读说明：本技术 存储器装置复位和初始化期间的功率管理 (Power management during reset and initialization of memory devices ) 是由 于亮 J·帕里 于 2021-05-17 设计创作，主要内容包括：本申请的实施例涉及存储器装置复位和初始化期间的功率管理。一种用于将第一命令发送到存储器子系统的多个存储器裸片中的第一存储器裸片的系统,所述第一命令为执行初始化过程；所述系统从所述第一存储器裸片读取第一位值,所述第一位值指示所述第一存储器裸片正在执行所述初始化过程的峰值电流阶段。所述系统从所述第一存储器裸片读取第二位值,所述第二位值指示所述第一存储器裸片正在执行所述初始化过程的安全阶段。响应于读取所述第二位值,将执行所述初始化过程的第二命令发送到第二存储器裸片。(Embodiments of the present application relate to power management during memory device reset and initialization. A system for sending a first command to a first memory die of a plurality of memory dies of a memory subsystem, the first command to perform an initialization process; the system reads a first bit value from the first memory die, the first bit value indicating that the first memory die is performing a peak current phase of the initialization process. The system reads a second bit value from the first memory die, the second bit value indicating that the first memory die is performing a secure phase of the initialization process. In response to reading the second bit value, sending a second command to a second memory die to perform the initialization process.)

1. A method, comprising:

sending, by a processing device, a first command to a first memory die of a plurality of memory dies of a memory subsystem, the first command to perform an initialization process on the first memory die;

reading a first bit value indicating that the first memory die is performing a peak current phase of the initialization process;

reading a second bit value indicating that the first memory die is performing a secure phase of the initialization process; and

in response to reading the second bit value, sending a second command to a second memory die of the plurality of memory dies of the memory subsystem, the second command to perform the initialization process on the second memory die.

2. The method of claim 1, wherein the first memory die sets a status register bit to one of the first bit value or the second bit value.

3. The method of claim 1, wherein the peak current phase comprises one or more peak current events having a current level that exceeds a threshold current level.

4. The method of claim 1, wherein a level of current consumed by the first memory die during the secure phase is less than a threshold current level.

5. The method of claim 1, wherein the second memory die performs the initialization process in response to the second command.

6. The method of claim 1, wherein the peak current phase is identified during a characterization phase associated with the first memory die.

7. The method of claim 1, further comprising:

determining, by a parameter detector, a measured parameter value associated with the execution of the phase of the initialization process by the first memory die; and

identifying the phase as the peak current phase in view of the measured parameter value satisfying a condition with respect to a threshold parameter level.

8. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

sending a first command to at least one memory die of a set of memory dies coupled via a shared ready busy RB output channel, the first command to perform an initialization process on the at least one memory die;

reading a first value associated with the shared RB output channel indicating that the at least one memory die is performing a peak current phase of the initialization process;

reading a second value associated with the shared RB output channel indicating that the set of memory dies is performing a secure phase of the initialization process; and

in response to reading the second value, a second command to perform the initialization process is sent to a next memory die.

9. The non-transitory computer-readable medium of claim 8, wherein the first value represents a composite ready busy value corresponding to the set of memory dies.

10. The non-transitory computer-readable medium of claim 8, wherein the at least one memory die sets an RB value to one of the first bit value or the second bit value.

11. The non-transitory computer-readable medium of claim 8, wherein a current level consumed during the secure phase of the initialization process is less than a threshold current level.

12. The non-transitory computer-readable medium of claim 8, wherein the next memory die initiates execution of the initialization process in response to the second command.

13. The non-transitory computer-readable medium of claim 8, the operations further comprising:

determining, by a parameter detector, a measured parameter value associated with the performance of the phase of the initialization process; and

identifying the phase as the peak current phase in view of the measured parameter value satisfying a condition with respect to a threshold parameter level.

14. A system, comprising:

a memory device; and

a processing device operably coupled with the memory device to perform operations comprising:

sending a first command to a first memory die of a plurality of memory dies of a memory subsystem, the first command to perform an initialization process on the first memory die;

reading a first bit value indicating that the first memory die is performing a peak current phase of the initialization process;

reading a second bit value indicating that the first memory die is performing a secure phase of the initialization process; and

in response to reading the second bit value, sending a second command to a second memory die of the plurality of memory dies of the memory subsystem, the second command to perform the initialization process on the second memory die.

15. The system of claim 14, wherein the first memory die sets a status register bit to one of the first bit value or the second bit value.

16. The system of claim 14, wherein the peak current phase comprises one or more peak current events having a current level that exceeds a threshold current level.

17. The system of claim 14, wherein a level of current consumed by the first memory die during the secure phase is less than a threshold current level.

18. The system of claim 14, wherein the second memory die initiates execution of the initialization process in response to the second command.

19. The system of claim 14, wherein the peak current phase is identified during a characterization phase associated with the first memory die.

20. The system of claim 14, the operations further comprising:

determining, by a parameter detector, a measured parameter value associated with the execution of the phase of the initialization process by the first memory die; and

identifying the phase as the peak current phase in view of the measured parameter value satisfying a condition with respect to a threshold parameter level.

Technical Field

Embodiments of the present disclosure relate generally to memory subsystems and, more particularly, to power management during memory device reset and initialization.

Background

The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory subsystem to store data at and retrieve data from a memory device.

Disclosure of Invention

According to one embodiment, a method is provided. The method comprises the following steps: sending, by a processing device, a first command to a first memory die of a plurality of memory dies of a memory subsystem, the first command to perform an initialization process on the first memory die; reading a first bit value indicating that the first memory die is performing a peak current phase of the initialization process; reading a second bit value indicating that the first memory die is performing a secure phase of the initialization process; and in response to reading the second bit value, sending a second command to a second memory die of the plurality of memory dies of the memory subsystem, the second command to perform the initialization process on the second memory die.

According to another embodiment, a non-transitory computer-readable medium is provided. The non-transitory computer-readable medium comprises instructions that, when executed by a processing device, cause the processing device to perform operations comprising: sending a first command to at least one memory die of a set of memory dies coupled via a shared Ready Busy (RB) output channel, the first command to perform an initialization process on the at least one memory die; reading a first value associated with the shared RB output channel indicating that the at least one memory die is performing a peak current phase of the initialization process; reading a second value associated with the shared RB output channel indicating that the set of memory dies is performing a secure phase of the initialization process; and in response to reading the second value, sending a second command to a next memory die to perform the initialization process.

According to another embodiment, a system is provided. The system comprises: a memory device; and processing means operatively coupled with the memory means to perform operations comprising: sending a first command to a first memory die of a plurality of memory dies of a memory subsystem, the first command to perform an initialization process on the first memory die; reading a first bit value indicating that the first memory die is performing a peak current phase of the initialization process; reading a second bit value indicating that the first memory die is performing a secure phase of the initialization process; and in response to reading the second bit value, sending a second command to a second memory die of the plurality of memory dies of the memory subsystem, the second command to perform the initialization process on the second memory die.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

FIG. 1 illustrates an example computing system including a memory subsystem, according to some embodiments of the present disclosure.

FIG. 2 is a flow diagram of an example method for managing execution of an initialization process by multiple memory dies of a memory subsystem, according to some embodiments.

FIG. 3 illustrates an example system including an initialization management component configured to send initialization commands to a plurality of memory dies in view of phase bit values, in accordance with some embodiments.

FIG. 4 illustrates the setting of phase bit values corresponding to phases of an initialization process performed by multiple memory dies, in accordance with some embodiments.

FIG. 5 illustrates an example system including an initialization management component configured to send an initialization command to a plurality of memory dies in view of ready busy logic output values, in accordance with some embodiments.

FIG. 6 illustrates setting ready busy logic output values corresponding to stages of an initialization process performed by multiple memory dies, in accordance with some embodiments.

Fig. 7 is a block diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure are directed to power management during reset and initialization of memory devices in a memory subsystem. The memory subsystem may be a memory device, a memory module, or a mixture of memory devices and memory modules. Examples of memory devices and memory modules are described below in connection with FIG. 1. In general, a host system may utilize a memory subsystem that includes one or more components (e.g., memory devices that store data). The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

The memory subsystem may include a memory device including a plurality of memory dies. During power-up operations, multiple memory dies undergo reset and initialization phases during which various operational settings (e.g., threshold voltage levels) are identified and loaded into storage devices (e.g., latches of the memory dies) of the memory dies. The initialization phase includes a plurality of operations and sub-operations that generate peak current events (e.g., charge pump initialization, word line ramp up, bit line charging, etc.). In some cases, multiple memory dies perform the initialization phase simultaneously, causing the total power and current consumption to exceed the peak requirements established for the memory subsystem.

One approach for managing power consumption during initialization is to reduce each peak power event by reducing individual memory die performance. This approach is only useful for memory dies that operate on the same channel using multi-die select (MDS) pad bonding information. Individual memory units are addressed in a memory device using MDSs, where each individual memory die can be addressed using a unique address, such as a Logical Unit Number (LUN) address, that is generated based on the number of Chip Enable (CE) inputs (e.g., control inputs or signals associated with operation of an integrated circuit) in the memory device and the number of memory dies per chip enable input. In this configuration, each memory die of a channel is assigned a predetermined delay value to apply during an initialization phase. For example, a first memory die associated with a first LUN address is assigned a predetermined delay value of five microseconds, and a second memory die associated with a second LUN address is assigned a predetermined delay value of ten microseconds, and so on. Thus, multiple memory dies associated with different LUN addresses may apply different delay times to the same channel in response to receiving initialization commands simultaneously. However, various memory devices do not use the CE input shared with the MDS junction. Alternatively, many memory subsystems use individual CE control for each memory die. Therefore, the aforementioned methods, which are limited to MDS configurations, cannot be applied.

Another approach for managing power consumption during initialization of multiple memory dies is to interleave the initialization time or trim load time (trim load time) associated with each memory die. In this method, the system controller manually time-interleaves the individual CE delays when issuing initialization commands to the respective memory dies. However, particularly as the memory dies continue to update operations performed as part of the initialization process, the resulting interleaving is not accurate and it is not guaranteed that the peak power levels generated by each memory die during the initialization phase are efficiently interleaved due to process, temperature, voltage (PVT) shifts, and corresponding overhead delays. In such cases, the PVT shift shifts the peak current timing in the delayed memory die, thereby causing the peak currents of the multiple memory dies to overlap.

Aspects of the present disclosure address the above and other deficiencies by a memory subsystem configured to manage peak current levels for a set of multiple memory dies during performance of reset and initialization processes. The initialization process may include multiple phases (e.g., one or more groups of operations or sub-operations) performed by the memory die. In an embodiment, each of a plurality of memory dies in a set of memory dies to be initialized maintains a Status Register (SR) that includes bits (referred to herein as "phase bits") that are readable by a controller of the memory subsystem to determine whether an initialization command can be sent to another memory die (e.g., a next memory die) in the set of memory dies.

A controller of the memory subsystem maintains read capability for the phase bits of each memory die to enable polling or reading of the phase bits to identify bit values. For example, the memory die may set a bit to a first bit value (e.g., a value of "1") indicating that the memory die is performing a phase of an initialization process associated with one or more peak current events (e.g., at-risk or sensitive phase or portion of initialization, also referred to as a "peak current phase"). In response to the polling operation, the controller reads the first bit value and determines that the initialization command should not be sent to the next memory die. In embodiments, one or more peak current phases (e.g., sensitive or at-risk phases) of the initialization process may be predetermined during a characterization phase of the memory die. In an embodiment, during operation, the memory subsystem may detect one or more peak current phases based on variations in operating parameters of the memory die, such as PVT variations.

When the memory die completes or exits one or more peak current phases, the memory die may enter one or more phases that do not include a peak current event (also referred to as a "safe phase" of the initialization process). One or more secure phases of the initialization process represent a "valid window" during which the initialization process can be performed on multiple memory dies in parallel without overlapping peak current events. In response to entering the secure phase, the memory die may set or switch the bit value to a second value (e.g., a value of "0"), which indicates to the controller that an initialization command may be sent to the next memory die.

In an embodiment, the memory subsystem may include a set of multiple memory dies with shared ready/busy (RB) outputs. The memory dies may provide a signal via the RB output to indicate a first value (e.g., a low state or value) that indicates that one or more of the memory dies are performing a peak current phase of an initialization process (e.g., a high peak current draw). The RB output signal may indicate a second value (e.g., a high state or value) if the memory die is performing a safe phase of the initialization process (e.g., low peak current draw). Thus, during memory die initialization, when all memory dies are in a low peak power phase, the shared RB output (e.g., the shared RB bus connected to the controller) may indicate a high state (e.g., a second value) that indicates that the controller is to begin a valid window of the initialization process for the next memory die. Advantageously, managing power consumption during the reset and initialization processes of multiple memory dies improves the accuracy of the staggering of peak current events.

FIG. 1 illustrates an example computing system 100 including a memory subsystem 110, according to some embodiments of the present disclosure. Memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such devices. Additional details regarding example computing system 100 are described in more detail below with reference to FIG. 3.

Memory subsystem 110 may be a storage device, a memory module, or a mix of storage devices and memory modules. Examples of storage devices include Solid State Drives (SSDs), flash drives, Universal Serial Bus (USB) flash drives, embedded multimedia controller (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and Hard Disk Drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

The computing system 100 may be a computing device, such as a desktop computer, a notebook computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other vehicle), an internet of things (IoT) -enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or networked market device), or such a computing device that includes memory and a processing device.

The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, host system 120 is coupled to different types of memory subsystems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory subsystem 110. As used herein, "coupled to" or "coupled with … …" generally refers to a connection between components that may be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a Universal Serial Bus (USB) interface, a fibre channel, serial attached SCSI (sas), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled with the host system 120 over a PCIe interface, the host system 120 may further utilize an NVM express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120. FIG. 1 illustrates memory subsystem 110 as an example. In general, host system 120 may access multiple memory subsystems via the same communication connection, multiple separate communication connections, and/or a combination of communication connections.

Memory devices 130, 140 may include different types of non-volatile memory devices and/or any combination of volatile memory devices. Volatile memory devices, such as memory device 140, may be, but are not limited to, Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Synchronous Dynamic Random Access Memory (SDRAM).

Some examples of non-volatile memory devices, such as memory device 130, include NAND (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory devices, which are cross-point arrays of non-volatile memory cells. A cross-point array of non-volatile memory may perform bit storage based on changes in body resistance in conjunction with a stackable cross-meshed data access array. In addition, in contrast to many flash-based memories, cross-point non-volatile memories may perform a write-in-place operation in which non-volatile memory cells may be programmed without pre-erasing the non-volatile memory cells. The NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of memory devices 130 may include one or more arrays of memory cells. One type of memory cell, for example, a Single Level Cell (SLC), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), three-level cells (TLC), and four-level cells (QLC), may store multiple bits per cell. In some embodiments, each of memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion, as well as an MLC portion, a TLC portion, or a QLC portion of a memory cell. The memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device for storing data. For some types of memory (e.g., NAND), the pages may be grouped to form blocks.

Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of non-volatile memory, such as Read Only Memory (ROM), Phase Change Memory (PCM), self-selected memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), Magnetic Random Access Memory (MRAM), Spin Transfer Torque (STT) -MRAM, conductive bridge ram (cbram), Resistive Random Access Memory (RRAM), oxide-based RRAM (oxram), NOR (NOR) flash memory, and Electrically Erasable Programmable Read Only Memory (EEPROM).

Memory subsystem controller 115 (or simply controller 115) may communicate with memory device 130 to perform operations such as reading data, writing data, or erasing data at memory device 130, and other such operations. Memory subsystem controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, cache memory, or a combination thereof. The hardware may comprise digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. Memory subsystem controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor.

Memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and so forth. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory subsystem 110 in fig. 1 has been illustrated as including memory subsystem controller 115, in another embodiment of the present disclosure, memory subsystem 110 does not include memory subsystem controller 115, but instead may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

In general, memory subsystem controller 115 may receive commands or operations from host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve desired access to memory device 130. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, cache operations, and address translation between logical block addresses (e.g., Logical Block Addresses (LBAs), namespaces) and physical block addresses (e.g., physical block addresses) associated with the memory device 130. Memory subsystem controller 115 may further include host interface circuitry to communicate with host system 120 via a physical host interface. Host interface circuitry may convert commands received from the host system into command instructions to access memory device 130 and convert responses associated with memory device 130 into information for host system 120.

Memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that may receive addresses from memory subsystem controller 115 and decode the addresses to access memory devices 130.

In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory units of memory device 130. An external controller (e.g., memory subsystem controller 115) may manage memory device 130 externally (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is an original memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed nand (mnand) device. In an embodiment, each memory die may include an on-die logic controller that controls the sequence and timing of operations (e.g., write, read, verify, etc.) within the memory die.

The memory subsystem 110 includes an initialization management component 113 for managing peak power events of a set of multiple memory dies of one or more memory devices 130, 140 of the memory subsystem 110 during performance of a reset and initialization process that includes multiple phases. In an implementation, the initialization management component 113 may be a hardware logic or firmware implementation that enables the memory subsystem controller 115 to perform the power management functions described herein (e.g., the operations shown in fig. 2 below). The stage of the initialization process may include a set or group of one or more sub-operations. The initialization process includes one or more phases that generate a peak current event (referred to as "peak current phases") and one or more phases that do not include a peak current event (also referred to as "safety phases"). Each of the plurality of memory dies maintains a Status Register (SR) bit that can be set to a first value to indicate that the memory die is processing a peak current phase or to a second value to indicate that the memory die is processing a safe phase. The phase bit can be read by the initialization management component 113 to determine whether an initialization command can be sent to another memory die (e.g., a next memory die) in a set of memory dies.

When the memory die completes or exits one or more peak current phases of the initialization process, the memory die may enter a "safe phase" of the initialization process. The initialization management component 113 can read a new bit value indicating that the memory die is in the valid window during which the initialization process can be performed on multiple memory dies in parallel without overlapping peak current events. In view of the identification of the bit values set by the first memory die that indicate operations in the secure phase, the initialization management component 113 determines a command to the next memory die to perform an initialization process. Advantageously, the initialization management component 113 can use the setting and reading of the phase bits to interleave peak current events associated with the resetting and initialization of multiple memory dies.

In embodiments, the peak current phase and the safety phase of the initialization process may be predetermined and predefined during the characterization phase of the memory die. In an embodiment, a memory die can be configured to perform characterization to identify whether the memory die is in a peak current phase or a safe phase. In an embodiment, initialization management component 113 can determine the peak current phase and the safety phase by detecting and measuring parameter values associated with the initialization process. In an embodiment, the initialization management component 113 can detect the PVT levels (e.g., voltage levels and temperature levels) of each memory die and compare to limits or thresholds (e.g., voltage threshold levels, temperature threshold levels, etc.) to detect peak power phases (e.g., phases that include measured parameter values that exceed corresponding thresholds).

In an embodiment, when the memory die transitions from the peak power phase to the safe phase, the phase bit (e.g., bit 2 of the status register) switches from a first value (e.g., the value "0" associated with the peak power phase) to a second value (e.g., the value "1"). Advantageously, the initialization management component 113 identifies a time slot (e.g., a time slot corresponding to one or more security stages) for each memory die during which the initialization management component 113 can send a command to the next memory die to perform the initialization process to efficiently interleave peak current events generated during initialization.

In an embodiment, the initialization management component 113 can read or receive a signal from a ready/busy (RB) output shared by multiple memory dies to determine whether the memory dies are in a peak current phase of an initialization process. In this embodiment, if any of the memory dies sharing the RB output are performing a peak current phase of the initialization process (e.g., high peak current draw), the composite RB output signal may provide a signal indicating a first value (e.g., an "active high" or "0" value). In an embodiment, the first value indicates that the memory die is in a high power mode (e.g., performing one or more peak current phases). The composite RB output signal may indicate a second value (e.g., an active low or "1" value) if all memory dies associated with the shared RB output signal are performing a safe phase of the initialization process (e.g., low peak current draw). In this embodiment, the active-low state represents a low power window (or "active window") during which the initialization management component 113 can begin the initialization process for the next memory die. In an embodiment, each memory die can provide an active high or active low value to the initialization management component 113 via the RB output to enable the initialization management component 113 to determine a composite value (e.g., active high or active low) for a plurality of memory dies that share the RB output. In an embodiment, the RB output is configured to combine all signals from multiple memory dies and provide a single composite signal representing an active high or active low state to the initialization management component 113.

FIG. 2 is a flow diagram of an example method 200 for managing power levels of multiple memory dies during performance of reset and initialization processes. Method 200 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, method 200 is performed by initialization management component 113 of FIG. 1. Additionally, FIG. 3 illustrates an example memory subsystem 115 that includes an initialization management component 113 configured to perform the operations of method 200. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Thus, it is to be understood that the illustrated embodiments are examples only, and that the illustrated processes can be performed in a different order, and that some processes can be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are also possible.

As shown in fig. 2, at operation 210, processing logic (e.g., the processor 117 of fig. 1, the initialization management component 113 of fig. 3, 4, and 5) sends a first command to perform an initialization process to a first memory die of a plurality of memory dies of a memory subsystem. In an embodiment, the initialization process includes multiple phases (e.g., sets of operations or sub-operations) that produce power consumption. In an embodiment, a first memory die initiates execution of an initialization process (e.g., phase 1 of the initialization process) in response to a command.

At operation 220, processing logic reads a first bit value indicating that the first memory is performing a peak current phase of an initialization process. In an embodiment, one or more peak current phases of the initialization process generate a peak current level that exceeds a threshold peak current level. In an embodiment, each memory die maintains a Status Register (SR) that includes a bit (referred to as a "phase bit") that can set a value to indicate whether the memory die is in a peak current phase. In an embodiment, the first bit value indicative of the peak current phase may be a value of "1" indicating an active-high mode during the window when the initialization management component 113 sends a command to start the initialization process to the next memory die invalidly.

FIG. 3 illustrates an example memory subsystem controller 115 that includes an initialization management component 113 that manages execution of an initialization process by a set of multiple memory dies (e.g., memory die 1, memory die 2 … … memory die N) in view of phase-bit values.

In an embodiment, one or more peak current phases of an initialization process can be identified and specified during a characterization phase of a first memory die. In this embodiment, one or more peak current phases that generate one or more peak current events are predetermined and stored to enable identification by the memory die. Thus, the memory die can recognize that the peak current phase is entered and set the phase bit value to the corresponding value.

In another embodiment, the first memory die may include one or more parameter detectors (e.g., PVT detectors) to measure one or more parameter values during performance of the initialization process. As shown in fig. 3, the first memory die may determine whether the phase of the initialization process being performed is a peak current phase by determining whether one or more parameter levels are changing compared to one or more parameter threshold levels. In an embodiment, one or more parameter level changes may be detected to identify entry and exit from peak current phases.

At operation 230, processing logic reads a second bit value indicating that the first memory die is performing the secure phase of the initialization process. In an embodiment, the safety phase is an initialization process phase in which no peak current event occurs. In an embodiment, a first memory die (e.g., memory die 1 in fig. 3) may set or switch a phase bit from a first bit value (indicative of a peak current phase) to a second bit value indicative of one or more security phases. In an embodiment, the second bit value indicative of the one or more security phases may be a value of "0" indicating an active-low mode during the window when the initialization management component 113 effectively sends a command to start the initialization process to the next memory die. In an embodiment, operation 230 occurs after the execution of operation 220.

In an embodiment, one or more security phases of an initialization process may be identified and marked during a characterization phase associated with a memory die. In another embodiment, one or more parameter value detectors may be used to determine parameter changes indicative of entering and exiting the security phase. In an embodiment, as shown in fig. 3, the parameter detector may detect or measure one or more parameter values (e.g., PVT values) and compare those values to a parameter threshold level to determine a comparison result. In an embodiment, if the comparison satisfies the condition, the phase detector may determine whether the phase is a safe phase.

At operation 240, in response to reading the second bit value, the processing logic sends a second command to a second memory die of the plurality of memory dies of the memory subsystem to perform the initialization process. As shown in fig. 3, reading a second bit value that identifies one or more secure phases indicates to the initialization management component 113 that a command to begin performing the initialization process can be safely sent to the next memory die (e.g., memory die 2 of fig. 3). In an embodiment, this process may be repeated with respect to memory die 2 to identify when memory die 2 is in a secure phase, and a command to begin the initialization process may be sent to the next memory die until the last memory die (e.g., memory die N) is reached.

FIG. 4 illustrates an initialization management system 113 that manages the execution of an initialization process by a set of memory dies (e.g., memory die 1 and memory die 2) that includes multiple stages (e.g., stage 1 through stage N), according to an embodiment of the disclosure. As shown in fig. 4, the initialization management system 113 sends a command to the memory die 1 to begin performing the initialization process. The memory die 1 sets the phase bit value to a first bit value (e.g., "1") to indicate the start of the initialization process and the identification of the peak current phase (e.g., phase 2). The current level of the memory die 1 varies due to the corresponding phase such that the current level during the safe phase is less than the threshold and the current level during the peak current phase (e.g., the phase including one or more peak current events) is greater than the threshold.

As shown in FIG. 4, after phase 2 is completed and one or more security phases (e.g., phase 3-phase 6) are entered, memory die 1 sets the phase bit value to "0". In the illustrated embodiment, the active low mode (e.g., phase bit value "0") indicates that the initialization management component 113 sends a valid window for the next initialization command. In an alternative embodiment, an active high mode (e.g., phase bit value "1"). As illustrated, during parallel execution of the initialization process by multiple memory dies, sending commands to the memory die 2 is staggered relative to starting the initialization process by the memory die 1, and overlapping peak current phases are avoided.

FIG. 5 illustrates an example memory subsystem controller 115 that includes an initialization management component 113 that manages execution of an initialization process by a set of multiple memory dies (e.g., memory die 1, memory die 2 … … memory die N) in view of Read Busy (RB) logic signals. As shown in fig. 5, a plurality of memory dies (e.g., memory die 1, memory die 2 … … memory die N) are connected to the initialization management component 113 via a shared RB connection. In an embodiment, each memory die may set a first value (e.g., a value of "1") for an RB indicating that the memory die is performing a security phase. In an embodiment, each memory die may set a second RB value (e.g., a value of "0") indicating that the memory die is performing a peak current phase.

In an embodiment, initialization management component 113 identifies a composite RB value based on the respective RB values of the memory dies (e.g., the RB-1 value of memory die 1, the RB-2 value of memory die 2, and the RB-N value of memory die 3), as shown in FIG. 6. In an embodiment, the active high mode (e.g., RB value of 1) indicates a low power or active window for sending initialization commands to the next memory die. In this embodiment, the active low mode (e.g., RB value 0) indicates a high power window corresponding to the peak current phase.

In an embodiment, the RB logic of multiple memory dies may be connected to a voltage source with a common pull-up resistor, with each RB output being an open drain circuit. In an embodiment, initialization management component 113 can identify a low output (e.g., RB value 0) for the peak current phase and identify a high output for the safe phase. As shown in FIG. 6, if any of the RB values of the memory die have a low value (e.g., RB-1 equals 0, RB-2 equals 0, or RB-N equals 0) due to the execution of the peak current phase, then the composite RB value is set to a low value (e.g., value 0). Further, when all memory dies are performing the security phase (e.g., RB-1 equals 1, RB-2 equals 1, and RB-N equals 1), the composite RB value is set to a high value (e.g., the first RB value of 1), thus indicating a valid window for sending a command to start the initialization process to the next memory die, as shown in FIG. 6.

In an embodiment, the initialization management component 113 can identify when one of the memory dies on the shared RB bus switches from a low value to a high value indicating that one or more other memory dies receive a command to begin an initialization process. In response, the initialization management component 113 can identify the valid window and send the next initialization command.

Fig. 7 illustrates an example machine of a computer system 700 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system 700 may correspond to a host system (e.g., the host system 120 of fig. 1) that includes, is coupled to, or utilizes a memory subsystem (e.g., the memory subsystem 110 of fig. 1) or may be used to perform operations of a controller (e.g., execute an operating system to perform operations corresponding to the initialization management component 113 of fig. 1). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, digital or non-digital circuitry, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 700 includes a processing device 702, a main memory 704 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

The processing device 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may further include a network interface device 708 to communicate over a network 720.

The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 may also reside, completely or at least partially, within the main memory 704 and/or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage media 724, data storage system 718, and/or main memory 704 may correspond to memory subsystem 110 of fig. 1.

In one embodiment, the instructions 726 include instructions for implementing functionality corresponding to a data protection component (e.g., the initialization management component 113 of FIG. 1). While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may be directed to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory components, and so forth.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.