阅读说明：本技术 一种应用于fpga的阶梯状布线及测试方法 (Stepped wiring and testing method applied to FPGA ) 是由 李岳 舒毅 于 2021-09-15 设计创作，主要内容包括：本发明涉及一种应用于FPGA的阶梯状布线及测试方法,属于芯片测试技术领域。该方法,执行如下步骤：1)定义起始位置；FPGA的第一行、第一列、最后一行、最后一列的CLB作为布线资源的起始位置；2)完成布线；a.正向布线；b.反向布线；3)连通性测试。该发明可遍历水平方向与垂直方向上所有布线资源,与传统技术上依次水平串联布线接口的测试方法相比,解决布线资源测试单一性的缺点,提高了FPGA布线资源测试的覆盖率,为FPGA的可靠应用提供前提。(The invention relates to a step-shaped wiring and testing method applied to an FPGA (field programmable gate array), belonging to the technical field of chip testing. The method comprises the following steps: 1) defining a starting position; the CLBs of the first row, the first column, the last row and the last column of the FPGA are used as the starting positions of wiring resources; 2) finishing wiring; a. wiring in a forward direction; b. reverse wiring; 3) and (5) testing connectivity. The invention can traverse all wiring resources in the horizontal direction and the vertical direction, solves the defect of the wiring resource test unicity compared with the test method of sequentially connecting wiring interfaces in series horizontally in the traditional technology, improves the coverage rate of the FPGA wiring resource test, and provides a premise for the reliable application of the FPGA.)

1. A stepped wiring and testing method applied to an FPGA is characterized by comprising the following steps:

defining a starting position;

the CLBs of the first row, the first column, the last row and the last column of the FPGA are used as the starting positions of wiring resources;

finishing wiring;

wiring in a forward direction;

horizontally executing unit step length from any initial position, then executing the unit step length in the vertical direction, circulating until a first row/a second row/an R-th row/an R-N +1 row or a column/a second column/a C-th column/a C-N +1 column of the FPGA, and stopping forward wiring;

b. reverse wiring;

b, starting from the wiring stopping position in the step a, wiring along a path which is in mirror symmetry with the central point of the FPGA until returning to the starting position in the step a;

wherein R is the total number of rows of the FPGA, C is the total number of columns of the FPGA, and N is the length of the tested line type;

3) testing connectivity;

inputting a logic value into a CLB (line routing initial position) through an IO (input/output) module, carrying out XOR operation in an LUT (look-up table) with a signal which passes through a tested line segment and is input into the CLB, inputting an XOR operation result into an input end of a D trigger of the CLB, connecting the D trigger storing the XOR result into a shift register, shifting and outputting the XOR result, checking whether an output result is consistent with an expected result, and judging the connectivity of the tested line segment according to the result.

2. The stair-stepping wiring and testing method applied to the FPGA according to claim 1, wherein: in step 3), if the result of the shift output is consistent with the exclusive or result of the corresponding D trigger, the connectivity of the corresponding measured line segment is normal, otherwise, the measured line segment has a fault.

Technical Field

The invention relates to a step-shaped wiring and testing method applied to an FPGA (field programmable gate array), belonging to the technical field of chip testing.

Background

The FPGA is used as a semi-custom circuit in the field of integrated circuits, wherein an IO module (Input and Output Block) and an Input and Output module are used; CLB (configurable Logic Block), programmable Logic block, is the basic unit of FPGA. The FPGA has the advantages of flexible design, low cost, rich logic resources and the like, and is widely applied to modern digital system design at present. A circuit designed by HDL generates a binary code stream after being compiled by FPGA EDA software, and the code stream can be used for configuring physical devices such as programmable switches in an FPGA chip, so that the circuit function is finally realized on the FPGA.

The FPGA EDA software flow includes circuit design, behavioral synthesis, process mapping, binning, placement, and routing, where routing is one of the most time consuming steps in the flow. Moreover, the connectivity problem of the wiring often causes the failure of the FPGA application, so it is very important to ensure the connectivity of the wiring resources in the FPGA for improving the reliability of the FPGA chip and the efficiency of EDA software compilation.

The existing FPGA wiring resource test generally adopts a method of connecting wiring interfaces in series in the horizontal direction, the test method cannot traverse the condition of using vertical wiring resources and the condition of using the horizontal wiring resources and the vertical wiring resources simultaneously, and the defects of single wiring resources and low wiring resource coverage rate exist.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the problems of low wiring coverage rate and incomplete wiring connectivity test of the FPGA chip are solved.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: a stepped wiring and testing method applied to an FPGA executes the following steps:

1) defining a starting position;

the CLBs of the first row, the first column, the last row and the last column of the FPGA are used as the starting positions of wiring resources;

2) finishing wiring;

a. starting forward wiring;

horizontally executing unit step length from any initial position, then executing the unit step length in the vertical direction, circulating until a first row/a second row/an R-th row/an R-N +1 row or a column/a second column/a C-th column/a C-N +1 column of the FPGA, and stopping forward wiring;

b. starting reverse wiring;

b, starting from the wiring stopping position in the step a, wiring along a path which is in mirror symmetry with the central point of the FPGA until returning to the starting position in the step a;

wherein R is the total number of rows of the FPGA, C is the total number of columns of the FPGA, and N is the length of the tested line type;

3) testing connectivity;

inputting a logic value into a CLB (line routing initial position) through an IO (input/output) module, carrying out XOR operation in an LUT (look-up table) with a signal which passes through a tested line segment and is input into the CLB, inputting an XOR operation result into an input end of a D trigger of the CLB, connecting the D trigger storing the XOR result into a shift register, shifting and outputting the XOR result, checking whether an output result is consistent with an expected result, and judging the connectivity of the tested line segment according to the result.

The improvement of the technical scheme is as follows: in step 3), if the result of the shift output is consistent with the exclusive or result of the corresponding D trigger, the connectivity of the corresponding measured line segment is normal, otherwise, the measured line segment has a fault.

The invention has the beneficial effects that: the invention can traverse all wiring resources in the horizontal direction and the vertical direction, solves the defect of the wiring resource test unicity compared with the test method of sequentially connecting wiring interfaces in series horizontally in the traditional technology, improves the coverage rate of the FPGA wiring resource test, and provides a premise for the reliable application of the FPGA.

Drawings

Fig. 1a is a flowchart of a wiring method applied to a step-like wiring and testing method of an FPGA according to a first embodiment of the present invention.

Fig. 1b is a flowchart of a testing method applied to a step-like wiring and testing method of an FPGA according to a first embodiment of the present invention.

Fig. 2 is a schematic diagram of a layout structure of an FPGA in a step-like wiring and testing method applied to the FPGA according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of a programmable logic module, namely a CLB in an FPGA, according to the step-like wiring and testing method applied to the FPGA of the first embodiment of the present invention.

Fig. 4a is a schematic diagram of the logic circuit of the LUT of fig. 3.

Fig. 4b is a schematic diagram of the logic circuit of the DFF of fig. 3.

Fig. 5 is a schematic diagram illustrating a definition of a wiring resource direction in a step-like wiring and testing method applied to an FPGA according to an embodiment of the present invention.

Fig. 6 is a schematic diagram of different types of programmable wiring resources applied to a ladder-shaped wiring and testing method of an FPGA according to an embodiment of the present invention.

Fig. 7 is a schematic diagram of a ladder-shaped wiring and testing method applied to an FPGA according to an embodiment of the present invention when wiring is performed in an X1 line type.

Fig. 8 is a schematic diagram of a ladder-shaped wiring and testing method applied to an FPGA according to a first embodiment of the present invention, in which the wiring is performed in an X2 line type.

Detailed Description

Example one

As shown in fig. 1a and 1b, a method for step-like wiring and testing applied to an FPGA executes the following steps:

1) defining a starting position;

the CLBs of the first row, the first column, the last row and the last column of the FPGA are used as the starting positions of wiring resources;

2) completing the wiring

a. Starting forward wiring;

horizontally executing unit step length from any initial position, then executing the unit step length in the vertical direction, circulating until a first row/a second row/an R-th row/an R-N +1 row or a column/a second column/a C-th column/a C-N +1 column of the FPGA, and stopping forward wiring;

b. starting reverse wiring;

b, starting from the wiring stopping position in the step a, wiring along a path which is in mirror symmetry with the central point of the FPGA until returning to the starting position in the step a;

wherein R is the total number of rows of the FPGA, C is the total number of columns of the FPGA, and N is the length of the tested line type;

as shown in fig. 6, the line types of different unit steps, the X1 line type and the X2 line type, are wired in the X1 line type, and the result will be similar to the wiring manner in fig. 7; if the wiring is wired in the X2 line type, the result will be similar to the wiring pattern in fig. 8. And in particular will be deployed later.

3) Testing connectivity;

inputting a logic value into a CLB (line routing initial position) through an IO (input/output) module, carrying out XOR operation in an LUT (look-up table) with a signal which passes through a tested line segment and is input into the CLB, inputting an XOR operation result into an input end of a D trigger of the CLB, connecting the D trigger storing the XOR result into a shift register, shifting and outputting the XOR result, checking whether an output result is consistent with an expected result, and judging the connectivity of the tested line segment according to the result.

In step 3), if the result of the shift output is consistent with the exclusive or result of the corresponding D trigger, the connectivity of the corresponding measured line segment is normal, otherwise, the measured line segment has a fault.

As shown in fig. 2, the routing resource in the horizontal direction of the programmable gate array FPGA of the present embodiment is named H, and the routing resource in the vertical direction is named V. The horizontal right wiring is denoted by E, the horizontal left wiring by W, the vertical up wiring by N, and the vertical down wiring by S, as shown in fig. 5. The length of the routing resource (or the length N of the line under test), i.e., the number of logic blocks CLBs it spans, X1 is the routing resource that spans 1 CLB; x2 is a routing resource … … XN that spans 2 CLBs is a routing resource that spans N CLBs, as shown in FIG. 6. If the measured line type is X1, the unit step size of the measured line segment is 1, namely, the measured line segment spans 1 CLB logic block; if the measured line type is X2, the unit step size of the measured line segment is 2, i.e. it spans 2 CLB logic blocks; if the line type to be measured is XN, the unit step size of the line segment to be measured is N, namely, the line segment to be measured spans N CLB logic blocks. This embodiment is exemplified by 1 and 2 only, and the rest can be analogized.

Taking X1 as an example, as shown in fig. 7, logic values are respectively input to CLBs at a first routing resource starting position (R1C 1) and a second routing resource starting position (R1C 3) through an IO module, a unit step of the line type is executed horizontally to the right (E), then a unit step of the line type is executed vertically to the bottom (S), and sequentially executed until the last row of the FPGA, and then a routing operation opposite to the routing direction is executed until the starting position of the routing. The other wiring starting positions of the first row, the last row, the first column and the last column are all sequentially executed with unit step length according to the wiring operation of the horizontal direction-the vertical direction. The logic value of the starting position CLB reaches the wiring starting position through a step-shaped tested line segment, the logic value of the starting position CLB is subjected to XOR operation in an LUT, the logic XOR results of all the starting positions are respectively input to the input of corresponding D triggers, the XOR results are shifted and output through a shift register connected by the D triggers, whether the shift output result is consistent with the expectation is judged, if the shift result is consistent with the XOR result of the corresponding D triggers, the connectivity of the corresponding tested line segment is normal, otherwise, the tested line segment has faults.

Taking X2 as an example, as shown in fig. 7, the execution steps are similar to X1, and logic values are respectively input to CLBs at the first (R2C 8) and the second (R8C 8) of the routing resources through the IO module, the unit step of the line type is executed horizontally to the right (E), then the unit step of the line type is executed vertically to the bottom (S), the unit step is 2 in this case, and the execution is sequentially performed until the last row or the 2 nd row of the FPGA, and then the routing operation opposite to the starting position is executed until the starting position. The starting positions of other wiring resources of the first row, the last row, the first column and the last column all execute unit step length in sequence according to the wiring operation of the horizontal direction-the vertical direction. The logic value of the starting position CLB reaches the starting position through a step-shaped measured line segment, the XOR operation is carried out on the starting wiring unit, the logic XOR results of all the starting positions are respectively input to the input of the corresponding D triggers, and the XOR results are shifted and output through the shift register connected by the D triggers. And judging the connectivity of the measured line segment according to the result of the register.

The LUT and D flip-flop in the above example are shown in fig. 4a and 4 b.

In addition to the above embodiments, the present invention may have other embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.