阅读说明：本技术 一种二极管及其制造方法 (Diode and manufacturing method thereof ) 是由 盛况 王珩宇 王策 于 2021-10-21 设计创作，主要内容包括：本发明涉及半导体技术领域中的一种二极管及其制造方法,包括阴极层、阳极层和二极管本体,二极管本体包括两组以上的衬底层和两组以上的中间层,每两组衬底层之间设置有一组中间层,或每两组中间层之间设置有一组衬底层,二极管本体上开设有一组以上的沟槽,且沟槽贯穿所有中间层,沟槽的侧壁上设置有连接层,具有提高耐压性的优点,突破了二极管在低压下影响正常开通速度的瓶颈。(The invention relates to a diode and a manufacturing method thereof in the technical field of semiconductors, and the diode comprises a cathode layer, an anode layer and a diode body, wherein the diode body comprises more than two groups of substrate layers and more than two groups of intermediate layers, one group of intermediate layers is arranged between every two groups of substrate layers, or one group of substrate layers is arranged between every two groups of intermediate layers, more than one group of grooves are arranged on the diode body, the grooves penetrate through all the intermediate layers, and connecting layers are arranged on the side walls of the grooves.)

1. The diode comprises a cathode layer, an anode layer and a diode body, and is characterized in that the diode body comprises more than two groups of substrate layers and more than two groups of intermediate layers, each group of intermediate layers are arranged between every two groups of substrate layers, or each group of substrate layers are arranged between every two groups of intermediate layers, more than one group of grooves are formed in the diode body, the grooves penetrate through all the intermediate layers, and connecting layers are arranged on the side walls of the grooves.

2. A diode according to claim 1 wherein said connection layer comprises a first semiconductor layer and an insulating fill layer, and wherein said first semiconductor layer is disposed on the sidewalls of the trench and said insulating fill layer is disposed between said first semiconductor layers.

3. A diode according to claim 2, wherein the side walls of the trench lie in a plane perpendicular to the plane of the intermediate layer.

4. The diode of claim 2, wherein the plane of the sidewall of the trench is at an angle with respect to the plane of the middle layer, and the angle is greater than 0 ° and less than 90 °.

5. A diode according to claim 1, wherein the connection layer comprises a first semiconductor layer, a second semiconductor layer and an insulating filling layer, the first semiconductor layer is disposed on the sidewall of the trench, the second semiconductor layer is disposed on a side of the first semiconductor layer away from the sidewall of the trench, and the insulating filling layer is disposed between the second semiconductor layers.

6. A diode according to claim 5, wherein the side walls of the trench lie in a plane perpendicular to the plane of the intermediate layer.

7. The diode of claim 5, wherein the plane of the sidewall of the trench is at an angle with respect to the plane of the middle layer, and the angle is greater than 0 ° and less than 90 °.

8. A diode according to any of claims 2 to 7 wherein the first semiconductor layer and the intermediate layer are of the same type of semiconductor material.

9. A diode according to any of claims 5 to 7 wherein the second semiconductor layer is of the same type of semiconductor material as the substrate layer.

10. A method of manufacturing a diode, comprising the steps of:

arranging more than two groups of substrate layers and more than two groups of intermediate layers in a staggered manner in the vertical direction to form a diode body;

forming more than one groove on the diode body by a dry etching method;

forming a first semiconductor layer and/or a second semiconductor layer on the side wall of the groove by a side wall ion implantation method or an epitaxial growth method, and filling an insulating medium in the groove;

and forming metal electrodes at two ends of the diode body by sputtering, evaporation or annealing, wherein the metal electrode close to the substrate layer is a cathode layer, and the metal electrode close to the middle layer is an anode layer.

Technical Field

The invention relates to the technical field of semiconductors, in particular to a diode and a manufacturing method thereof.

Background

In recent years, energy conservation and emission reduction are more and more emphasized internationally, which puts higher requirements on loss control and efficiency improvement of large-scale power electronic equipment. Semiconductor power devices have received much attention in the industry as an important component of power electronic equipment.

Breakdown voltage is an important indicator of a semiconductor power device and represents the maximum voltage that the device can withstand. The active region of the power device can obtain the breakdown voltage of several kilovolts by introducing the multilayer inversion doping region, thereby being suitable for the application occasions of higher power. The semiconductor device with the multi-layer inversion type doping region introduced into the active region of the device is called a floating junction device, wherein the inversion type doping region refers to a semiconductor region with the impurity type opposite to that of a substrate layer, and the floating junction device has the problem of delay of turn-on recovery while improving the withstand voltage. This is because the device accumulates charges in the inversion-type doped region in the blocking state, and the charges in the floating inversion-type doped region are restricted by the electric field and cannot be discharged in the process of switching to the on state, so that the device cannot be normally turned on at a low voltage. This turn-on recovery problem causes the floating junction device to cause excessive pulse voltage at the turn-on instant in circuit applications, resulting in excessive energy loss.

Disclosure of Invention

The invention provides a diode and a manufacturing method thereof aiming at the defects in the prior art, has the advantage of improving the voltage resistance, and breaks through the bottleneck that the diode influences the normal switching speed under low voltage.

In order to solve the technical problem, the invention is solved by the following technical scheme:

the diode comprises a cathode layer, an anode layer and a diode body, wherein the diode body comprises more than two groups of substrate layers and more than two groups of intermediate layers, each group of intermediate layers are arranged between every two groups of substrate layers, or each group of substrate layers are arranged between every two groups of intermediate layers, more than one group of grooves are formed in the diode body, the grooves penetrate through all the intermediate layers, and connecting layers are arranged on the side walls of the grooves.

Optionally, the connection layer includes a first semiconductor layer and an insulating filling layer, the first semiconductor layer is disposed on a sidewall of the trench, and the insulating filling layer is disposed between the first semiconductor layers.

Optionally, a plane where the side wall of the trench is located is perpendicular to a plane where the middle layer is located.

Optionally, an included angle is formed between a plane where the side wall of the groove is located and a plane where the middle layer is located, and the included angle is greater than 0 ° and smaller than 90 °.

Optionally, the connection layer includes a first semiconductor layer, a second semiconductor layer and an insulating filling layer, the first semiconductor layer is disposed on the sidewall of the trench, the second semiconductor layer is disposed on a surface of the first semiconductor layer away from the sidewall of the trench, and the insulating filling layer is disposed between the second semiconductor layers.

Optionally, a plane where the side wall of the trench is located is perpendicular to a plane where the middle layer is located.

Optionally, an included angle is formed between a plane where the side wall of the groove is located and a plane where the middle layer is located, and the included angle is greater than 0 ° and smaller than 90 °.

Optionally, the first semiconductor layer and the intermediate layer are made of the same type of semiconductor material.

Optionally, the second semiconductor layer and the substrate layer are made of the same type of semiconductor material.

A method of manufacturing a diode, comprising the steps of:

arranging more than two groups of substrate layers and more than two groups of intermediate layers in a staggered manner in the vertical direction to form a diode body;

forming more than one groove on the diode body by a dry etching method;

forming a first semiconductor layer and/or a second semiconductor layer on the side wall of the groove by a side wall ion implantation method or an epitaxial growth method, and filling an insulating medium in the groove;

and forming metal electrodes at two ends of the diode body by sputtering, evaporation or annealing, wherein the metal electrode close to the substrate layer is a cathode layer, and the metal electrode close to the middle layer is an anode layer.

Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:

through setting up slot and first semiconductor layer, make first semiconductor layer connect each doped layer, thereby make the diode body at opening the in-process, it is total to inject into first semiconductor layer with the lateral wall that the hole passes through the slot, accelerate the turn-on speed of diode body, and through the setting of second semiconductor layer, make second semiconductor layer and the first semiconductor layer that are P type semiconductor material and N type semiconductor material respectively to deplete each other, thereby modulate the electric field distribution near first semiconductor layer, thereby reduce the withstand voltage influence of first semiconductor layer to the diode body, simultaneously through setting up the slot lateral wall of different gradients, further modulate the electric field distribution near first semiconductor layer, it is fast to have the turn-on speed, advantage that the withstand voltage is strong.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 is a structural diagram of a first embodiment of a diode according to an embodiment of the present invention;

fig. 2 is a structural diagram of a second embodiment of a diode according to the present invention;

fig. 3 is a structural diagram of a third embodiment of a diode according to the present invention;

fig. 4 is a structural diagram of a fourth embodiment of a diode according to the present invention;

FIG. 5 is a diagram illustrating one of the structures of an intermediate layer of a diode according to an embodiment of the present invention;

fig. 6 is a second structural diagram of an intermediate layer of a diode according to an embodiment of the present invention;

fig. 7 is a band distribution diagram of a conventional diode when it is turned on again after being turned off.

Reference numerals: 1. a cathode layer; 2. an anode layer; 3. a diode body; 4. a substrate layer; 5. an intermediate layer; 6. a trench; 7. a connecting layer; 8. a first semiconductor layer; 9. a second semiconductor layer; 10. an insulating filling layer; 11. an epitaxial layer; 12. and (5) doping the layers.

Detailed Description

The present invention will be described in further detail with reference to examples, which are illustrative of the present invention and are not to be construed as being limited thereto.

Example one

As shown in fig. 1, a diode includes a cathode layer 1, an anode layer 2 and a diode body 3, the diode body 3 includes more than two groups of substrate layers 4 and more than two groups of intermediate layers 5, a group of intermediate layers 5 is disposed between every two groups of substrate layers 4, or a group of substrate layers 4 is disposed between every two groups of intermediate layers 5, and the number of the substrate layers 4 and the number of the intermediate layers 5 may be the same or different, when the number of the substrate layers 4 and the number of the intermediate layers 5 are different, the number of the substrate layers and the number of the intermediate layers are different by one, the diode body 3 is provided with more than one group of grooves 6, the grooves 6 penetrate through all the intermediate layers 5, and the side walls of the grooves 6 are provided with connecting layers 7.

In this embodiment, the substrate layer 4 is used as the first layer, and the combination is performed in a manner that the intermediate layer 5 and the substrate layer 4 are sequentially arranged in an upward staggered manner, and the number of the substrate layer 4 and the number of the intermediate layer 5 are always kept consistent, at this time, the cathode layer 1 is connected with the substrate layer 4 of the first layer, and the anode layer 2 is connected with the intermediate layer 5 of the last layer, wherein the substrate layer 4 has a doping concentration of~ The N-type semiconductor material of (1).

The connecting layer 7 comprises a first semiconductor layer 8 and an insulating filling layer 10, the first semiconductor layer 8 is arranged on the side wall of the groove 6, the insulating filling layer 10 is arranged between the first semiconductor layers 8, the plane where the side wall of the groove 6 is located is perpendicular to the plane where the middle layer 5 is located, and the first semiconductor layer 8 and the middle layer 5 are made of the same type of semiconductor material.

As shown in fig. 5, the intermediate layer 5 comprises an epitaxial layer 11 and a doped layer 12, wherein the epitaxial layer 11 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, and the doped layer 12 is a doped layer with a doping concentration of ~ The first semiconductor layer 8 is a P-type semiconductor material with the same doping concentration as the doping layer 12, since the trench 6 formed on the diode body 3 has two side walls in common and the two side walls are opposite, so that the first semiconductor layer 8 is correspondingly arranged oppositely, and in the trench 6, a gap between the two first semiconductor layers 8 is used for filling an insulating medium to form an insulating filling layer 10, wherein the doping layer 12 can be in any one of a stripe shape, a grid shape or a honeycomb shape in the horizontal direction, as shown in fig. 6, the middle layer 5 can also not include an epitaxial layer 11 and only consists of the doping layer 12.

In the turn-on process of the conventional diode, when the diode body 3 changes from reverse deflection to zero deflection, since the middle layer 5 located in the middle is not directly connected with the anode layer 2 and the cathode layer 1, hole carriers near the anode layer 2 cannot enter the middle layer 5 located in the middle, so that negative charges are left in the middle layers 5 at both ends to block the flow of electron carriers, and only when the forward bias is large enough, namely the energy band distribution diagram shown in fig. 7, and the voltage at both ends of the diode is 692V, the charges can be conducted through the middle layers 5; on the other hand, after the diode is turned on, the energy band distribution shown in fig. 7 has a large potential barrier, that is, the intermediate layer 5 has a large potential barrier, and therefore, negative charges are still stored, and therefore, a large step-down voltage is maintained after the diode is turned on.

With the structure of the embodiment, when the diode body 3 is under a low voltage state, the doped layers 12 are connected through the first semiconductor layer 8 in the trench 6, so that holes can be injected into the doped layers 12 through the sidewalls of the trench 6 during the turn-on process of the diode body 3, thereby increasing the turn-on speed.

Specifically, by adding the first semiconductor layer 8, in the switching-on process of the diode body 3, hole carriers can be supplemented into the intermediate layer 5 located in the middle through the P-type bus of the first semiconductor layer 8, so that negative charges in the intermediate layer 5 are released, the obstruction to the circulation of electrons is eliminated, the forward conduction voltage drop is greatly reduced, and the conduction power loss is reduced.

On the other hand, in the present embodiment, the materials of the substrate layer 4 and the epitaxial layer 11, the materials of the doped layer 12 and the first semiconductor layer 8 can be interchanged, that is, the substrate layer 4 and the epitaxial layer 11 have doping concentrations of ~ Doped layer 12 and first semiconductor layer 8 are doped with a doping concentration of ~ And the switching speed of the diode body 3 after the interchange under the low-voltage condition is the same as that before the interchange.

Example two

As shown in fig. 2, a diode includes a cathode layer 1, an anode layer 2 and a diode body 3, the diode body 3 includes more than two groups of substrate layers 4 and more than two groups of intermediate layers 5, a group of intermediate layers 5 is disposed between every two groups of substrate layers 4, or a group of substrate layers 4 is disposed between every two groups of intermediate layers 5, and the number of the substrate layers 4 and the number of the intermediate layers 5 may be the same or different, when the number of the substrate layers 4 and the number of the intermediate layers 5 are different, the number of the substrate layers and the number of the intermediate layers are different by one, the diode body 3 is provided with more than one group of trenches 6, the trenches 6 penetrate through all the intermediate layers 5, and the side walls of the trenches 6 are provided with connecting layers 7.

In this embodiment, the substrate layer 4 is used as the first layer, and the combination is performed in a manner that the intermediate layer 5 and the substrate layer 4 are sequentially arranged in an upward staggered manner, and the number of the substrate layer 4 and the number of the intermediate layer 5 are always kept consistent, at this time, the cathode layer 1 is connected with the substrate layer 4 of the first layer, and the anode layer 2 is connected with the intermediate layer 5 of the last layer, wherein the substrate layer 4 has a doping concentration of ~ The N-type semiconductor material of (1).

The connecting layer 7 comprises a first semiconductor layer 8 and an insulating filling layer 10, the first semiconductor layer 8 is arranged on the side wall of the groove 6, the insulating filling layer 10 is arranged between the first semiconductor layer 8, the plane where the side wall of the groove 6 is located and the plane where the middle layer 5 is located are arranged at an included angle, the included angle is larger than 0 degree and smaller than 90 degrees, and the first semiconductor layer 8 and the middle layer 5 are made of semiconductor materials of the same type.

As shown in fig. 5, the intermediate layer 5 comprises an epitaxial layer 11 and a doped layer 12, wherein the epitaxial layer 11 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, and the doped layer 12 is a doped layer with a doping concentration of ~ The first semiconductor layer 8 is a P-type semiconductor material with the same doping concentration as the doping layer 12, and since the trench 6 formed in the diode body 3 has two side walls in common and the two side walls are opposite, the first semiconductor layer 8 is correspondingly arranged oppositely, and in the trench 6, a gap between the two first semiconductor layers 8 is used for filling an insulating medium to form an insulating filling layer 10.

With the structure of the embodiment, when the diode body 3 is under a low voltage state, the doped layers 12 are connected through the first semiconductor layer 8 in the trench 6, so that holes can be injected into the doped layers 12 through the sidewalls of the trench 6 during the turn-on process of the diode body 3, thereby increasing the turn-on speed.

Specifically, by adding the first semiconductor layer 8, in the switching-on process of the diode body 3, hole carriers can be supplemented into the intermediate layer 5 located in the middle through the P-type bus of the first semiconductor layer 8, so that negative charges in the intermediate layer 5 are released, the obstruction to the circulation of electrons is eliminated, the forward conduction voltage drop is greatly reduced, and the conduction power loss is reduced.

Compared with the first embodiment, the present embodiment further modulates the electric field distribution near the first semiconductor layer 8 by adjusting the inclination angle of the sidewall, thereby reducing the influence of the first semiconductor layer 8 on the voltage overshoot of the diode body 3.

On the other hand, when the side wall of the trench 6 is inclined, that is, the included angle is greater than 0 ° and less than 90 °, the area of the substrate layer 4 of the diode body 3 from top to bottom is gradually increased, and the region where the increased area of the substrate layer 4 is located and the first semiconductor layer 8 are mutually depleted, so that the influence of the increased area on the electric field distribution is counteracted, and the withstand voltage influence on the diode body 3 is reduced.

In this embodiment, the materials of the substrate layer 4 and the epitaxial layer 11, the doped layer 12 and the first semiconductor layer 8 can be interchanged, that is, the substrate layer 4 and the epitaxial layer 11 have doping concentrations of ~ Doped layer 12 and first semiconductor layer 8 are doped with a doping concentration of ~ And the switching speed of the diode body 3 after the interchange under the low-voltage condition is the same as that before the interchange.

EXAMPLE III

As shown in fig. 3, the connection layer 7 includes a first semiconductor layer 8, a second semiconductor layer 9 and an insulating filling layer 10, the first semiconductor layer 8 is disposed on the sidewall of the trench 6, the second semiconductor layer 9 is disposed on a side of the first semiconductor layer 8 away from the sidewall of the trench 6, the insulating filling layer 10 is disposed between the second semiconductor layers 9, a plane where the sidewall of the trench 6 is located is perpendicular to a plane where the intermediate layer 5 is located, the first semiconductor layer 8 and the intermediate layer 5 are made of the same type of semiconductor material, and the second semiconductor layer 9 and the substrate layer 4 are made of the same type of semiconductor material.

As shown in fig. 5, the intermediate layer 5 comprises an epitaxial layer 11 and a doped layer 12, wherein the epitaxial layer 11 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, and the doped layer 12 is a doped layer with a doping concentration of ~ The first semiconductor layer 8 is a P-type semiconductor material with the same doping concentration as the doping layer 12, the second semiconductor layer 9 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, the trench 6 formed in the diode body 3 shares two side walls, and the two side walls are opposite, so that the second semiconductor layer 9 is correspondingly arranged oppositely, and in the trench 6, a gap between the two second semiconductor layers 9 is used for filling an insulating medium to form an insulating filling layer 10.

With the structure of the embodiment, when the diode body 3 is under a low voltage state, the doped layers 12 are connected through the first semiconductor layer 8 in the trench 6, so that holes can be injected into the doped layers 12 through the sidewalls of the trench 6 during the turn-on process of the diode body 3, thereby increasing the turn-on speed.

The difference between this embodiment and the first embodiment is that the second semiconductor layer 9 is added, so that the electric field distribution near the first semiconductor layer 8 is modulated by mutual depletion of the P-type semiconductor material and the N-type semiconductor material, thereby reducing the withstand voltage influence of the first semiconductor layer 8 on the diode body 3.

Specifically, by adding the first semiconductor layer 8, in the process of turning on the diode body 3, hole carriers can be supplemented into the intermediate layer 5 in the middle through the P-type bus of the first semiconductor layer 8, so that negative charges in the intermediate layer 5 are released, the obstruction to the circulation of electrons is eliminated, the forward conduction voltage drop is greatly reduced, the conduction power loss is reduced, and the second semiconductor layer 9 is arranged, so that the charges in the first semiconductor layer 8 and the second semiconductor layer 9 are mutually offset, and when the reverse bias of the diode body 3 is reduced, the adverse effect of an electric field is reduced, and the influence on the voltage resistance of the diode body 3 is reduced.

On the other hand, in the present embodiment, the materials of the substrate layer 4, the epitaxial layer 11 and the second semiconductor layer 9 and the materials of the doping layer 12 and the first semiconductor layer 8 can be interchanged, that is, the substrate layer 4, the epitaxial layer 11 and the second semiconductor layer 9 are doped with the doping concentration of ~ Doped layer 12 and first semiconductor layer 8 are doped with a doping concentration of ~ And the switching speed of the diode body 3 after the interchange under the low-voltage condition is the same as that before the interchange.

Example four

As shown in fig. 4, the connection layer 7 includes a first semiconductor layer 8, a second semiconductor layer 9 and an insulating filling layer 10, the first semiconductor layer 8 is disposed on the sidewall of the trench 6, the second semiconductor layer 9 is disposed on the first semiconductor layer 8, which is away from the sidewall of the trench 6, the insulating filling layer 10 is disposed between the second semiconductor layers 9, a plane where the sidewall of the trench 6 is located and a plane where the intermediate layer 5 is located are disposed at an included angle, the included angle is greater than 0 ° and smaller than 90 °, the first semiconductor layer 8 and the intermediate layer 5 are made of the same type of semiconductor material, and the second semiconductor layer 9 and the substrate layer 4 are made of the same type of semiconductor material.

As shown in fig. 5, the intermediate layer 5 comprises an epitaxial layer 11 and a doped layer 12, wherein the epitaxial layer 11 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, and the doped layer 12 is a doped layer with a doping concentration of ~ The first semiconductor layer 8 is a P-type semiconductor material with the same doping concentration as the doping layer 12, the second semiconductor layer 9 is an N-type semiconductor material with the same doping concentration as the substrate layer 4, the trench 6 formed in the diode body 3 shares two side walls, and the two side walls are opposite, so that the second semiconductor layer 9 is correspondingly arranged oppositely, and in the trench 6, a gap between the two second semiconductor layers 9 is used for filling an insulating medium to form an insulating filling layer 10.

With the structure of the embodiment, when in a low-voltage state, the doped layers 12 are connected through the first semiconductor layer 8 in the trench 6, so that during the turn-on process of the diode body 3, holes can be injected into the doped layers 12 through the side walls of the trench 6, thereby accelerating the turn-on speed, and the second semiconductor layer 9 is added, so that the electric field distribution near the first semiconductor layer 8 is modulated through mutual depletion of the P-type semiconductor material and the N-type semiconductor material, thereby reducing the withstand voltage influence of the first semiconductor layer 8 on the diode body 3.

Specifically, by adding the first semiconductor layer 8, in the process of turning on the diode body 3, hole carriers can be supplemented into the intermediate layer 5 in the middle through the P-type bus of the first semiconductor layer 8, so that negative charges in the intermediate layer 5 are released, the obstruction to the circulation of electrons is eliminated, the forward conduction voltage drop is greatly reduced, the conduction power loss is reduced, and the second semiconductor layer 9 is arranged, so that the charges in the first semiconductor layer 8 and the second semiconductor layer 9 are mutually offset, and when the reverse bias of the diode body 3 is reduced, the adverse effect of an electric field is reduced, and the influence on the voltage resistance of the diode body 3 is reduced.

The difference between this embodiment and the third embodiment is that the electric field distribution near the first semiconductor layer 8 is further modulated by adjusting the inclination angle of the sidewall of the trench 6 and combining the mutual depletion effect of the P-type semiconductor material and the N-type semiconductor material, and the influence of the first semiconductor layer 8 on the withstand voltage of the diode body 3 is further reduced.

Specifically, when the side wall of the trench 6 is inclined, that is, the included angle is greater than 0 ° and smaller than 90 °, the area of the substrate layer 4 of the diode body 3 from top to bottom is gradually increased, and the region where the area of the increased substrate layer 4 is located and the first semiconductor layer 8 are mutually depleted, so that the influence of the area on the electric field distribution is offset, and the withstand voltage influence on the diode body 3 is reduced.

On the other hand, in the present embodiment, the materials of the substrate layer 4, the epitaxial layer 11 and the second semiconductor layer 9 and the materials of the doping layer 12 and the first semiconductor layer 8 can be interchanged, that is, the substrate layer 4, the epitaxial layer 11 and the second semiconductor layer 9 are doped with the doping concentration of ~ Doped layer 12 and first semiconductor layer 8 are doped with a doping concentration of ~ And the switching speed of the diode body 3 after the interchange under the low-voltage condition is the same as that before the interchange.

EXAMPLE five

A method of manufacturing a diode, comprising the steps of: arranging more than two groups of substrate layers 4 and more than two groups of intermediate layers 5 in a staggered manner in the vertical direction to form a diode body 3; forming more than one groove 6 on the diode body 3 by a dry etching method; forming a first semiconductor layer 8 and/or a second semiconductor layer 9 on the side wall of the trench 6 by a side wall ion implantation method or an epitaxial growth method, and filling an insulating medium in the trench 6; metal electrodes are formed at both ends of the diode body 3 by sputtering, evaporation or annealing, wherein the metal electrode near the substrate layer 4 is the cathode layer 1 and the metal electrode near the intermediate layer 5 is the anode layer 2.

Taking the structure of the first embodiment as an example, the method of this embodiment first grows an epitaxial layer 11 on the substrate layer 4, and the substrate layer 4 and the epitaxial layer 11 both have doping concentrations of ~ The doping layers 12 are formed on the two sides of the epitaxial layer 11 through P-type ion implantation, so that the intermediate layer 5 is formed by the epitaxial layer 11 and the doping layers 12, then the substrate layer 4 is repeatedly superposed to form the intermediate layer 5, and the operation is repeated for times according to actual production requirements to obtain the diode body 3.

One or more grooves 6 are formed in the diode body 3 through dry etching, a first semiconductor layer 8 is formed on the side wall of each groove 6 through side wall ion implantation or epitaxial growth, an insulating medium is filled between the first semiconductor layers 8 to form an insulating filling layer 10, and finally a metal electrode is formed through modes of sputtering or growing, annealing and the like.

In addition, it should be noted that the specific embodiments described in the present specification may differ in the shape of the components, the names of the components, and the like. All equivalent or simple changes of the structure, the characteristics and the principle of the invention which are described in the patent conception of the invention are included in the protection scope of the patent of the invention. Various modifications, additions and substitutions for the specific embodiments described may be made by those skilled in the art without departing from the scope of the invention as defined in the accompanying claims.