阅读说明：本技术 具有纳微米结构的TOPCon晶硅太阳电池 (TOPCon crystal silicon solar cell with nano-micron structure ) 是由 丁东 沈文忠 李正平 裴骏 于 2021-08-18 设计创作，主要内容包括：一种具有纳微米结构的TOPCon晶硅太阳电池实现方法,在n型晶硅衬底的正面采用碱溶液制备得到微米结构金字塔后,在微米结构金字塔上制备硅纳米柱阵列或金属纳米颗粒阵列；然后在正面通过高温硼扩散形成p-n结、在背面通过LPCVD方法或PVD方法制备氧化硅/掺杂多晶硅叠层结构；最后在正面的p-n结上依次覆盖氧化铝/氢化氮化硅叠层和金属Ag/Al栅线、在背面的氧化硅/掺杂多晶硅叠层结构上覆盖氢化氮化硅层和金属Ag栅线。本发明能够显著降低硅片对入射光的反射率,从而使得更多光子被晶硅衬底吸收,同时新绒面结构没有带来更大载流子复合,电池效率跟常规电池具有可比性。(A TOPCon crystalline silicon solar cell implementation method with a nano-micron structure is characterized in that after a micron structure pyramid is prepared on the front side of an n-type crystalline silicon substrate by adopting an alkaline solution, a silicon nano-pillar array or a metal nano-particle array is prepared on the micron structure pyramid; then forming a p-n junction on the front surface through high-temperature boron diffusion, and preparing a silicon oxide/doped polysilicon laminated structure on the back surface through an LPCVD method or a PVD method; and finally, covering the aluminum oxide/hydrogenated silicon nitride laminated layer and the metal Ag/Al grid line on the p-n junction on the front surface in sequence, and covering the hydrogenated silicon nitride layer and the metal Ag grid line on the silicon oxide/doped polysilicon laminated structure on the back surface. The invention can obviously reduce the reflectivity of the silicon wafer to incident light, thereby enabling more photons to be absorbed by the crystalline silicon substrate, simultaneously, the new suede structure does not bring about larger carrier recombination, and the efficiency of the cell is comparable to that of the conventional cell.)

1. A TOPCon crystalline silicon solar cell implementation method with a nano-micron structure is characterized in that after a micro-structure pyramid is prepared on the front side of an n-type crystalline silicon substrate by adopting an alkaline solution, a silicon nano-pillar array or a metal nano-particle array is prepared on the micro-structure pyramid; then forming a p-n junction on the front surface through high-temperature boron diffusion, and preparing a silicon oxide/doped polysilicon laminated structure on the back surface through an LPCVD method or a PVD method; and finally, covering the aluminum oxide/hydrogenated silicon nitride laminated layer and the metal Ag/Al grid line on the p-n junction on the front surface in sequence, and covering the hydrogenated silicon nitride layer and the metal Ag grid line on the silicon oxide/doped polysilicon laminated structure on the back surface.

2. The method for realizing TOPCon crystal silicon solar cell with nano-micron structure as claimed in claim 1, wherein the alkali solution is a mixed solution of NaOH and isopropanol or a mixed solution of KOH and isopropanol, wherein: the concentration of NaOH or KOH is 1% -3%, and the concentration of isopropanol is 3% -10%.

3. The method for realizing the TOPCon crystalline silicon solar cell with the nano-micro structure as claimed in claim 1, wherein the metal nanoparticle array is realized by the following method: soaking the silicon wafer with the pyramid with the micron structure in AgNO in a back-to-back mode₃And in HF mixed solution, uniformly covering the outer side of the silicon chip with metal Ag nano particle array, and stacking two silicon chips together and inserting the silicon chips into a wet flower basket in AgNO₃And soaking in HF mixed solution to make Ag nano particles deposit on one side of the silicon wafer.

4. The method for realizing the TOPCon crystalline silicon solar cell with the nano-micro structure as claimed in claim 1, wherein the silicon nano-pillar array is realized by the following method: soaking the silicon wafer with the pyramid with the micron structure in AgNO in a back-to-back mode₃In the HF mixed solution, uniformly covering the outer side of the silicon wafer with metal AgSoaking the silicon wafer in H after the rice grains are formed₂O₂And in the HF mixed solution, forming a silicon nano-pillar array by etching.

5. The method for realizing TOPCon crystal silicon solar cell with nano-micron structure as claimed in claim 1, wherein the LPCVD method is characterized by: growing an ultrathin silicon oxide layer on the back of the n-type crystalline silicon substrate, introducing silane to deposit an intrinsic polycrystalline silicon layer, and then carrying out phosphorus doping on the polycrystalline silicon layer; or growing an ultrathin silicon oxide layer on the back of the n-type crystalline silicon substrate, and then introducing silane and phosphine to deposit an in-situ doped polycrystalline silicon layer.

6. The method for realizing the TOPCon crystalline silicon solar cell with the nano-micron structure as claimed in claim 1, wherein the PVD method is characterized in that: growing a silicon oxide layer on the back of the n-type crystalline silicon substrate, then introducing silane to deposit an intrinsic polycrystalline silicon layer, and then carrying out phosphorus doping on the polycrystalline silicon layer, or growing a silicon oxide layer on the back of the n-type crystalline silicon substrate, and then introducing silane and phosphine to deposit an in-situ doped polycrystalline silicon layer.

7. A TOPCon crystalline silicon solar cell with a nano-micron structure prepared by the method of any one of claims 1-6, comprising: the solar cell comprises a battery silicon chip, a micrometer structure pyramid, a metal nanoparticle array or a silicon nano-pillar array, an aluminum oxide layer and a hydrogenated silicon nitride layer for passivation antireflection, an ultrathin silicon oxide layer, a polycrystalline silicon layer and a hydrogenated silicon nitride layer for passivation antireflection, which are sequentially positioned on the front side of the silicon chip, a p-n junction formed by diffusion in the micrometer structure pyramid, and a metal grid line electrode positioned on the outermost part.

Technical Field

The invention relates to a technology in the field of solar photovoltaic cells, in particular to a tunneling oxidation passivation contact (TOPCon) crystalline silicon solar cell with a nano-micron structure.

Background

The tunneling oxidation passivation contact structure is composed of an ultrathin tunneling oxidation layer and a doped polycrystalline silicon layer, and can provide excellent surface passivation for the back of a silicon wafer, the ultrathin oxidation layer can prevent minority carrier hole recombination while enabling multi-electron tunneling to enter the doped polycrystalline silicon, and the electron transverse transmission entering the polycrystalline silicon is collected by a metal electrode. Due to the fact that the front side is shielded by the electrode, incident photon collection has certain limitation, and if the Interdigital Back Contact (IBC) solar cell with the positive electrode and the negative electrode on the back side is prepared, process steps and process difficulty are increased sharply.

It has been found that silicon nanostructures will occupy a position in the next generation of high performance photovoltaic cells due to their desirable optical antireflective properties. The main difficulty in realizing high-performance nano-structure is that the deterioration degree of electrical properties caused by carrier recombination easily exceeds the advantages brought by light absorption enhancement, and the nano-micro composite structure solar cell can solve the contradiction. The nano-micro composite structure is not prepared on a conventional planar substrate, but is prepared on a micron-sized pyramid suede. The structure has the advantages that the superposition effect of the antireflection performance of the micro-structure and the nano-structure can be realized, so that more incident photons are collected, the short-circuit current density of the battery is improved, and the electrical loss of the battery is less.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides the TOPCon crystalline silicon solar cell with the nano-micron structure.

The invention is realized by the following technical scheme:

the invention relates to a TOPCon crystalline silicon solar cell implementation method with a nano-micron structure, which is characterized in that after a micron-structure pyramid is prepared on the front surface of an n-type crystalline silicon substrate by adopting an alkaline solution, a silicon nano-pillar array or a metal nano-particle array is prepared on the micron-structure pyramid; then forming a p-n junction on the front surface through high-temperature boron diffusion, and preparing a silicon oxide/doped polysilicon laminated structure on the back surface through an LPCVD method or a PVD method; and finally, covering the aluminum oxide/hydrogenated silicon nitride laminated layer and the metal Ag/Al grid line on the p-n junction on the front surface in sequence, and covering the hydrogenated silicon nitride layer and the metal Ag grid line on the silicon oxide/doped polysilicon laminated structure on the back surface.

The alkali solution is a mixed solution of NaOH and isopropanol or a mixed solution of KOH and isopropanol, wherein: the concentration of NaOH or KOH is 1% -3%, and the concentration of isopropanol is 3% -10%.

The temperature of the mixed solution is 60-100 ℃.

The height of the micron-structure pyramid is 2-10 mu m.

The metal nanoparticle array is realized by the following modes: soaking the silicon wafer with the pyramid with the micron structure in AgNO in a back-to-back mode₃And in HF mixed solution, uniformly covering the outer side of the silicon chip with metal Ag nano particle array, and stacking two silicon chips together and inserting the silicon chips into a wet flower basket in AgNO₃And soaking in HF mixed solution to make Ag nano particles deposit on one side of the silicon wafer.

The size of Ag particles in the nano array structure is 20-200 nm, and the coverage rate of the Ag particles on the surface is 3% -50%.

The silicon nano-pillar array is realized by the following modes: soaking the silicon wafer with the pyramid with the micron structure in AgNO in a back-to-back mode₃And in the HF mixed solution, after the outer side of the silicon wafer is uniformly covered with metal Ag nano particles, soaking the silicon wafer in H₂O₂And in the HF mixed solution, forming a silicon nano-pillar array by etching.

Preferably, by HNO₃And HF solution to remove residual Ag particlesA silicon oxide layer.

The height of the silicon nano-pillar array is 50-300 nm.

AgNO in the mixed solution₃The mass fraction of (A) is 2-5%.

The LPCVD method refers to: growing an ultrathin silicon oxide layer on the back of the n-type crystalline silicon substrate, introducing silane to deposit an intrinsic polycrystalline silicon layer, and then carrying out phosphorus doping on the polycrystalline silicon layer; or growing an ultrathin silicon oxide layer on the back of the n-type crystalline silicon substrate, and then introducing silane and phosphine to deposit an in-situ doped polycrystalline silicon layer.

The thickness of the ultrathin silicon oxide layer is 0.5-2 nm, the thickness of the polycrystalline silicon layer is 50-200 nm, and the phosphorus doping concentration is 2 multiplied by 10¹⁹～2×10²⁰cm^-3。

The PVD method is as follows: growing a silicon oxide layer on the back of the n-type crystalline silicon substrate, then introducing silane to deposit an intrinsic polycrystalline silicon layer, and then carrying out phosphorus doping on the polycrystalline silicon layer, or growing a silicon oxide layer on the back of the n-type crystalline silicon substrate, and then introducing silane and phosphine to deposit an in-situ doped polycrystalline silicon layer.

The thickness of the silicon oxide layer is 0.5-2 nm, the thickness of the polycrystalline silicon layer is 50-200 nm, and the phosphorus doping concentration is 2 multiplied by 10¹⁹～2×10²⁰cm^-3。

The aluminum oxide/hydrogenated silicon nitride lamination is characterized in that an aluminum oxide layer with the thickness of 1-10 nm and a hydrogenated silicon nitride layer with the thickness of 70-80 nm are sequentially deposited on a p-n junction on the front surface by an Atomic Layer Deposition (ALD) method and a PECVD method,

the hydrogenated silicon nitride layer is deposited on the silicon oxide/doped polysilicon laminated structure on the back surface by a PECVD method, and the thickness of the hydrogenated silicon nitride layer is 50-200 nm.

The metal Ag/Al grid line and the metal Ag grid line are prepared by adopting a screen printing method but not limited to the screen printing method.

The invention relates to a TOPCon crystalline silicon solar cell with a nano-micron structure, which is prepared by the method and comprises the following steps: the solar cell comprises a battery silicon wafer, a micron-structure pyramid positioned on the front side of the silicon wafer, a metal nanoparticle array or a silicon nano-pillar array positioned on the micron-structure pyramid, a p-n junction formed by diffusion, an ultrathin silicon oxide layer and a polycrystalline silicon layer positioned on the back side of the silicon wafer, and a passivation antireflection layer and metal grid line electrodes positioned on two sides of the silicon wafer.

Technical effects

The invention integrally solves the problem that the conversion efficiency of the TOPCon crystalline silicon solar cell is improved by the antireflection function of the silicon wafer suede in the prior art; through the nano-micron structure and the application of the nano-micron structure in the TOPCon crystalline silicon solar cell, the reflectivity of the silicon wafer to incident light is obviously reduced, so that more photons are absorbed by the crystalline silicon substrate, meanwhile, the new suede structure does not bring about larger carrier recombination, and the cell efficiency is comparable to that of a conventional cell.

Drawings

FIG. 1 is a schematic structural diagram of a TOPCon crystalline silicon solar cell with a metal nanoparticle array structure on the front surface according to the present invention;

FIG. 2 is a schematic structural diagram of a TOPCon crystalline silicon solar cell with a silicon nanorod array structure on the front surface according to the present invention;

in the figure: 1 ultrathin silicon oxide layer, 2 polycrystalline silicon layer, 3 hydrogenated silicon nitride layer, 4 back Ag electrode, 5 micron structure pyramid, 6 silicon nano-pillar array, 7 metal nano-particle array, 8 aluminum oxide layer, 9 hydrogenated silicon nitride layer, 10 front Ag/Al electrode and 11 front diffusion formed p-n junction.

Detailed Description

Example 1

As shown in fig. 1, a TOPCon crystalline silicon solar cell with superior photoelectric characteristics according to the present embodiment includes: the solar cell comprises an n-type cell silicon wafer, a micrometer structure pyramid 5, a metal nanoparticle array 7, an aluminum oxide layer 8 and a hydrogenated silicon nitride layer 9 which are sequentially positioned on the front side of the silicon wafer, an ultrathin silicon oxide layer 1, a polycrystalline silicon layer 2 and a hydrogenated silicon nitride layer 3 which are positioned on the back side of the silicon wafer and are used for passivating and antireflection, a p-n junction 11 formed by diffusion in the micrometer structure pyramid 5, and metal grid line electrodes 4 and 10 positioned on the outermost portion.

The solar cell of the embodiment is specifically realized by the following modes:

1) selecting a crystalline silicon substrate: selecting an n-type crystalline silicon substrate, wherein: the thickness of the crystalline silicon substrate is 10-180 mu m, preferably 180 mu m, the resistivity is 0.5-2 omega cm, preferably 1 omega cm, a NaOH solution with the concentration of 10-20% is adopted to remove the damaged layer on the surface of the silicon wafer at the temperature of 75-100 ℃, and the concentration and temperature of the NaOH solution are preferably 15% and 80 ℃.

2) Preparing a pyramid with a micron structure on the front surface of the silicon wafer: and (3) adopting a mixed solution of NaOH and isopropanol or adopting a mixed solution of KOH and isopropanol to perform texturing on the front surface of the silicon wafer after the damage layer is removed so as to form a pyramid with a micron structure. The concentration of NaOH or KOH aqueous alkali is 1 to 3 percent, preferably 2 percent, and the concentration of isopropanol solution is 3 to 10 percent, preferably 5 percent; the temperature of the solution in the alkaline texturing tank body is 60-100 ℃, the preferred temperature is 90 ℃, and the height of the pyramid is 2-10 μm.

3) Preparing a silicon wafer front metal nanoparticle array: soaking the silicon wafer with pyramid structure in AgNO in a back-to-back manner by using a metal-assisted chemical etching method₃And HF mixed solution, Ag⁺The ions are reacted and then uniformly covered on the outer side of the silicon wafer in a metal Ag particle mode; AgNO₃The mass fraction of the Ag particles in the mixed solution is 2-5%, preferably 3%, the size of the formed Ag particles is 20-200 nm, preferably 100nm, and the coverage rate of the Ag particles on the surface of the pyramid is 3-50%, preferably 20%.

4) Preparing a p-n junction on the front surface of the silicon wafer: taking the surface with the nano-particle array as the front side of the silicon wafer treated in the step 3) in a two-to-two back-to-back mode, and adopting BBr₃Or BCl₃Performing medium-high temperature diffusion doping to form p as boron source⁺In the region, the diffusion temperature is about 900 ℃, the diffusion time is 50-120 min, preferably 120min, the diffusion sheet resistance is 100-200 omega/□, preferably 160 omega/□; then placing the back of the silicon chip after boron diffusion into HF/HNO₃/H₂SO₄Etching treatment is carried out in the mixed solution to remove the back p⁺And (5) doping the layers.

5) Preparing a TOPCon structure on the back of the silicon wafer: growing an ultrathin silicon oxide layer on the back of the silicon wafer treated in the step 4) by adopting an LPCVD method or a PVD method, then introducing silane to deposit an intrinsic amorphous silicon layer, and then carrying out plasma etching on the silicon waferPhosphorus doping and annealing are carried out on the amorphous silicon layer, or after the silicon oxide layer grows, silane and phosphine are introduced to deposit the in-situ doped amorphous silicon layer, and then the TOPCon structure is formed through annealing; wherein the PVD method comprises magnetron sputtering and PECVD method. Wherein the temperature for growing the silicon oxide layer by LPCVD is 550-650 ℃, preferably 600 ℃, the time for growing the silicon oxide layer is 5-10 min, preferably 8min, and the thickness of the oxide layer is 0.5-2 nm; the temperature of the amorphous silicon layer deposited by LPCVD is 580-650 ℃, preferably 650 ℃, the thickness of the amorphous silicon layer is 50-200 nm, the phosphorus doping concentration is 2 multiplied by 10¹⁹～2×10²⁰cm^-3Preferably 1X 10²⁰cm^-3(ii) a Wherein the reaction pressure of the chamber is less than 1Pa during magnetron sputtering, the deposition temperature is 100-300 ℃, and the preferred temperature is 200 ℃; wherein the PECVD deposition temperature is 100-400 ℃, and preferably 250 ℃.

6) Preparing a passivated antireflection layer on two sides of a silicon wafer: depositing an aluminum oxide layer and a hydrogenated silicon nitride layer on the front side of the silicon wafer treated in the step 5) by an ALD (atomic layer deposition) and PECVD (plasma enhanced chemical vapor deposition) method, wherein the thickness of the aluminum oxide layer is 1-10 nm, and the thickness of the hydrogenated silicon nitride layer is 70-80 nm; and depositing a hydrogenated silicon nitride layer on the back of the silicon wafer by a PECVD method, wherein the thickness of the hydrogenated silicon nitride layer is 50-200 nm.

7) Preparing metal electrodes on two sides of a silicon wafer: preparing an Ag/Al grid line electrode on the front side of the silicon wafer treated in the step 6) by a screen printing method, preparing an Ag grid line electrode on the back side of the silicon wafer by a screen printing method, and finally sintering to form the TOPCon crystalline silicon solar cell with excellent photoelectric characteristics.

Through specific practical experiments, under the conventional specific environment setting, by a method of combining the preparation of the metal nanoparticle structure battery and theoretical simulation, 80% of incident photons can be absorbed by a crystalline silicon substrate with the thickness of 180 mu m, after the metal nanoparticles are adopted, the light absorption of the crystalline silicon substrate can be enhanced by 5.2%, and the simulation result is consistent with the experimental result; the simulation of the crystalline silicon substrate with the thickness of only 1 mu m shows that the thin crystalline silicon can only absorb 33% of incident photons, and after the metal nanoparticles are adopted, the light absorption of the crystalline silicon substrate can be enhanced by 24.4%; in the aspect of electrical performance of the cell, the crystalline silicon solar cell with the thickness of 180 micrometers is simulated by adopting a metal nanoparticle structure, so that the conversion efficiency can be improved by about 5%, the crystalline silicon solar cell with the thickness of 1 micrometer can improve the conversion efficiency by about 30%, and the thinner crystalline silicon cell uses the nanoparticle structure, so that the effect improvement effect is more obvious.

Example 2

As shown in fig. 2, compared with embodiment 1, in the TOPCon crystalline silicon solar cell with superior photoelectric characteristics according to this embodiment, the preparation of the silicon nanorod array on the pyramid surface includes: the silicon chip comprises an n-type battery silicon chip, a micrometer structure pyramid 5, a silicon nano-pillar array 6, an aluminum oxide layer 8 and a hydrogenated silicon nitride layer 9 which are sequentially positioned on the front side of the silicon chip and used for passivating and antireflection, an ultrathin silicon oxide layer 1, a polycrystalline silicon layer 2 and a hydrogenated silicon nitride layer 3 which are positioned on the back side of the silicon chip and used for passivating and antireflection, a p-n junction 11 formed by diffusion in the micrometer structure pyramid 5, and metal grid line electrodes 4 and 10 positioned on the outermost portion.

The solar cell of the embodiment is specifically realized by the following modes:

1) selecting a crystalline silicon substrate: selecting an n-type crystalline silicon substrate, wherein the thickness of the crystalline silicon substrate is 100-180 mu m, preferably 180 mu m, the resistivity is 0.5-2 omega cm, preferably 1 omega cm, removing a silicon wafer surface damage layer by adopting a NaOH solution with the concentration of 10-20% at the temperature of 75-100 ℃, and the concentration and the temperature of the NaOH solution are preferably 15% and 80 ℃.

2) Preparing a pyramid with a micron structure on the front surface of the silicon wafer: adopting a mixed solution of NaOH and isopropanol or a mixed solution of KOH and isopropanol to texture the front surface of the silicon wafer after the damage layer is removed so as to form a micrometer structure pyramid, wherein: the concentration of NaOH or KOH aqueous alkali is 1 to 3 percent, preferably 2 percent, and the concentration of isopropanol solution is 3 to 10 percent, preferably 5 percent; the temperature of the solution in the alkaline texturing tank body is 60-100 ℃, preferably 85 ℃, and the height of the pyramid is 2-10 μm.

3) Preparing a silicon nano-pillar array on the front surface of a silicon wafer: a metal auxiliary chemical etching method is adopted, namely, the silicon chip with the pyramid structure is soaked in AgNO in a back-to-back mode₃And HF mixed solution, Ag⁺The ions are reacted and then are uniform in the mode of metal Ag particlesCovering the silicon wafer outside, and soaking the silicon wafer in H₂O₂And in HF mixed solution, etching the area without Ag particles to form silicon nano-pillar array, wherein the residual Ag particles and the silicon oxide layer are respectively formed by HNO₃And HF solution removal; AgNO₃The mass fraction of the silicon nano-pillar in the mixed solution is 2% -5%, preferably 3%, and the height of the formed silicon nano-pillar array is 50-300 nm.

4) Preparing a p-n junction on the front surface of the silicon wafer: taking the silicon wafer processed in the step 3 in a pairwise back-to-back mode, taking the surface with the silicon nano-pillar array as the front side to face outwards, and adopting BBr₃Or BCl₃High temperature diffusion doping as boron source to form p⁺In the region, the diffusion temperature is about 900-1100 ℃, preferably 1030 ℃, the diffusion time is 50-120 min, preferably 110min, the diffusion sheet resistance is 70-140 omega/□, preferably 80 omega/□; then placing the back of the silicon chip after boron diffusion into HF/HNO₃/H₂SO₄Etching treatment is carried out in the mixed solution to remove the back p⁺And (5) doping the layers.

5) Preparing a TOPCon structure on the back of the silicon wafer: growing an ultrathin silicon oxide layer on the back of the silicon wafer treated in the step 4) by adopting an LPCVD (low pressure chemical vapor deposition) method or a PVD (physical vapor deposition) method, then introducing silane to deposit an intrinsic amorphous silicon layer, then doping phosphorus in the amorphous silicon layer and annealing, or after growing the silicon oxide layer, introducing silane and phosphine to deposit an in-situ doped amorphous silicon layer, and then annealing to form a TOPCon structure; wherein the PVD method comprises magnetron sputtering and PECVD method. Wherein the temperature for growing the silicon oxide layer by LPCVD is 550-650 ℃, preferably 600 ℃, the time for growing the silicon oxide layer is 5-10 min, preferably 8min, and the thickness of the oxide layer is 0.5-2 nm; the temperature of the amorphous silicon layer deposited by LPCVD is 580-650 ℃, preferably 650 ℃, the thickness of the amorphous silicon layer is 50-200 nm, the phosphorus doping concentration is 2 multiplied by 10¹⁹～2×10²⁰cm^-3Preferably 1.5X 10²⁰cm^-3(ii) a Wherein the reaction pressure of the chamber is less than 1Pa during magnetron sputtering, the deposition temperature is 100-300 ℃, and the preferred temperature is 200 ℃; wherein the PECVD deposition temperature is 100-400 ℃, and preferably 250 ℃.

6) Preparing a passivated antireflection layer on two sides of a silicon wafer: depositing an aluminum oxide layer and a hydrogenated silicon nitride layer on the front side of the silicon wafer treated in the step 5) by an ALD (atomic layer deposition) and PECVD (plasma enhanced chemical vapor deposition) method, wherein the thickness of the aluminum oxide layer is 1-10 nm, and the thickness of the hydrogenated silicon nitride layer is 70-80 nm; and depositing a hydrogenated silicon nitride layer on the back of the silicon wafer by a PECVD method, wherein the thickness of the hydrogenated silicon nitride layer is 50-200 nm.

7) Preparing metal electrodes on two sides of a silicon wafer: preparing an Ag/Al grid line electrode on the front side of the silicon wafer treated in the step 6 by a screen printing method, preparing the Ag grid line electrode on the back side of the silicon wafer by the screen printing method, and finally sintering to form the TOPCon crystalline silicon solar cell with excellent photoelectric characteristics.

Through specific practical experiments, under the conventional specific environment setting, four kinds of nano-pillar structures with different heights are prepared, the heights are respectively 100nm, 150nm, 200nm and 300nm, when the front surface of a silicon wafer where the nano-pillars are located is not covered by a passivation film layer, the measured reflectivities are respectively 8.8%, 6.1%, 5.3% and 4.2%, compared with the reflectivity of 13% of a pyramid with a micro-structure (without the passivation film layer), the reflectivities are greatly reduced, and the higher the nano-pillars are, the more the reflectivities are reduced; when the front surface of the silicon wafer where the nano-pillars are located is covered by the passivation film layer, the measured reflectivity is respectively 2.4%, 2.5%, 2.7% and 2.8%, and compared with the reflectivity of 4% of a pyramid with a micro-structure (with the passivation film layer), the reflectivity is also improved, and at the moment, the dependence of the reflectivity on the pyramid height is not obvious; in the aspect of electrical performance of the battery, experiments show that the battery efficiency can be equal to that of a conventional battery by adopting a silicon nano-pillar structure.

Compared with the prior art, the device reduces the reflection of the silicon wafer to incident light by preparing the nano array structure on the surface of the conventional micron gold tower, so that more photons are absorbed by the crystalline silicon substrate, thereby improving the short-circuit current density of the battery and improving the conversion efficiency of the battery; meanwhile, the battery preparation method can be compatible with the existing production line process.

The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.