阅读说明：本技术 锁相环电路及数字时间转换器误差消除方法 (Phase-locked loop circuit and digital time converter error elimination method ) 是由 邱威豪 林昂生 阙资展 于 2021-05-06 设计创作，主要内容包括：本发明提供了一种锁相环(PLL)电路。锁相环(PLL)电路包括第一DTC,第一选择电路和第二选择电路。第一选择电路耦接第一DTC,第一选择电路接收参考信号和反馈信号,并根据选择信号将参考信号或反馈信号发送给第一DTC。第一DTC接收第一延迟控制信号,以抖动接收到的参考信号或反馈信号。第二选择电路耦接到第一DTC和第一选择电路,第二选择电路根据选择信号确定输出参考信号或输出反馈信号的路径。相应地,本发明还提供了一种数字时间转换器(DTC)误差消除方法,能够在锁相环(PLL)电路中减少DTC误差。(The invention provides a phase-locked loop (PLL) circuit. A phase-locked loop (PLL) circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first selection circuit is coupled with the first DTC, receives the reference signal and the feedback signal, and sends the reference signal or the feedback signal to the first DTC according to the selection signal. The first DTC receives a first delay control signal to dither a received reference signal or feedback signal. The second selection circuit is coupled to the first DTC and the first selection circuit, and the second selection circuit determines a path for outputting the reference signal or the feedback signal according to the selection signal. Accordingly, the present invention also provides a Digital Time Converter (DTC) error cancellation method capable of reducing DTC errors in a Phase Locked Loop (PLL) circuit.)

1. A phase locked loop, PLL, circuit comprising a first selection circuit, a first digital to time converter, DTC, and a second selection circuit;

wherein the first selection circuit is configured to receive a reference signal and a feedback signal, and to send one of the reference signal and the feedback signal to the first DTC according to a selection signal;

the first DTC is coupled to the first selection circuit, and is used for receiving the reference signal or the feedback signal and jittering the received reference signal or the feedback signal according to a first delay control signal; and the number of the first and second groups,

the second selection circuit is coupled to the first DTC and the first selection circuit, and is used for determining a coupling path for outputting a reference signal and a feedback signal according to the selection signal.

2. The PLL circuit of claim 1, wherein the first selection circuit comprises a first multiplexer and a second multiplexer, and the second selection circuit comprises a third multiplexer and a fourth multiplexer;

alternatively, the first and second electrodes may be,

the first selection circuit includes a first switch and a second switch, and the second selection circuit includes a third switch and a fourth switch.

3. The PLL circuit of claim 1 wherein the select signal is a first value during a first period and the first select circuit sends the reference signal to the first DTC, and wherein the select signal is a second value during a second period and the first select circuit sends the feedback signal to the first DTC.

4. The PLL circuit of claim 3, wherein the second selection circuit outputs the output reference signal based on its first input from the first DTC and the output feedback signal based on its second input from the first selection circuit in the first period; in the second period, the second selection circuit outputs the output feedback signal based on its first input from the first DTC and outputs the output reference signal based on its second input from the first selection circuit.

5. The PLL circuit of claim 3, wherein the first delay control signal has a same setting during the first period and the second period.

6. The PLL circuit of claim 1, wherein the PLL circuit further comprises a second DTC, the second DTC coupled to the first selection circuit and the second selection circuit;

wherein the first selection circuit is further configured to send the other of the reference signal and the feedback signal to the second DTC according to the selection signal, and the second DTC is configured to dither the received reference signal or the feedback signal according to a second delay control signal;

wherein the second selection circuit determines from the selection signal whether to output the output reference signal based on its first input from the first DTC and the output feedback signal based on its second input from the second DTC, or to output the output feedback signal based on its first input from the first DTC and the output reference signal based on its second input from the second DTC.

7. The PLL circuit of claim 6, wherein the second delay control signal has a same setting during the first period and the second period.

8. The PLL circuit of claim 1, wherein the second selection circuit sends the output reference signal and the output feedback signal to a phase frequency detector PFD or a time to digital converter TDC.

9. The PLL circuit of claim 8, wherein the PFD is disposed between the first TDC and the second selection circuit or in front of the first selection circuit.

10. A DTC error elimination method of a digital time converter is applied to a phase-locked loop (PLL) circuit, and comprises the following steps:

a first selection circuit of the PLL circuit receives a reference signal and a feedback signal;

the first selection circuit transmits one of the reference signal and the feedback signal to a first DTC of the PLL circuit according to a selection signal;

the first DTC jitters the received reference signal or the feedback signal according to a first delay control signal; and the number of the first and second groups,

a second selection circuit of the PLL circuit determines a coupling path for outputting a reference signal and a feedback signal according to the selection signal.

11. The DTC error cancellation method of claim 10, wherein the first selection circuit comprises a first multiplexer and a second multiplexer, the second selection circuit comprises a third multiplexer and a fourth multiplexer;

alternatively, the first and second electrodes may be,

the first selection circuit comprises a first switch and a second switch, and the second selection circuit comprises a third switch and a fourth switch.

12. The DTC error cancellation method of claim 10, wherein the select signal is a first value during a first period, and wherein the method further comprises:

the first selection circuit transmits the reference signal to the first DTC.

13. The DTC error cancellation method of claim 12, wherein the select signal is at a second value during a second period, and wherein the method further comprises:

the first selection circuit sends the feedback signal to the first DTC.

14. The DTC error cancellation method of claim 13, wherein in the first cycle, the method further comprises:

the second selection circuit outputs the output reference signal based on its first input from the first DTC and the output feedback signal based on its second input from the first selection circuit.

15. The DTC error cancellation method of claim 13, wherein in the second period, the method further comprises:

the second selection circuit outputs the output feedback signal based on its first input from the first DTC and the output reference signal based on its second input from the second DTC.

16. The DTC error cancellation method of claim 13, wherein the first delay control signal has the same setting during the first period and the second period.

17. The DTC error cancellation method of claim 10, further comprising:

a second DTC of the PLL circuit for dithering the received reference signal or the feedback signal according to a second delay control signal;

the first selection circuit transmits the other of the reference signal and the feedback signal to the second DTC according to the selection signal; and the number of the first and second groups,

the second selection circuit determines from the selection signal whether to output the output reference signal based on its first input from the first DTC and the output feedback signal based on its second input from the second DTC, or to output the output feedback signal based on its first input from the first DTC and the output reference signal based on its second input from the second DTC.

18. The DTC error cancellation method of claim 17, wherein the second delay control signal has the same setting during the first period and the second period.

19. The DTC error cancellation method of claim 10, further comprising:

the second selection circuit sends the output reference signal and the output feedback signal to a Phase Frequency Detector (PFD) or a time To Digital Converter (TDC).

20. The DTC error cancellation method of claim 19, wherein the PFD is disposed between the first TDC and the second selection circuit or is disposed in front of the first selection circuit.

Technical Field

The present invention relates generally to digital-to-time converter (DTC) technology and, more particularly, to DTC error cancellation (error cancellation) technology in which a reference signal and a feedback signal can be alternately (alternatingly) transmitted to a Digital Time Converter (DTC).

Background

Digital-to-time converters (DTCs) are often used in Phase-Locked Loop (PLL) circuits, such as all-digital Phase-Locked Loop (ADPLL). A digital-to-time converter (DTC) can be used to delay edges (edges) of an input signal (e.g., a reference signal) according to a delay control signal at its input. However, due to pressure (pressure), temperature or voltage variations, a DTC error term may be generated. DTC errors can cause mismatch and low frequency noise in Phase Locked Loop (PLL) circuits.

Disclosure of Invention

In view of the above, an objective of the present invention is to provide a power allocation method and a user equipment, so as to solve the above problem. The present invention provides a Phase Locked Loop (PLL) circuit and a digital to time converter (DTC) error cancellation method to overcome the above-mentioned problems.

Embodiments of the present invention provide a Phase Locked Loop (PLL) circuit. The phase-locked loop (PLL) circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first selection circuit receives a reference signal and a feedback signal and transmits the reference signal or the feedback signal to a first DTC according to a selection signal. The first DTC receives a first delay control signal to dither (dither) the received reference signal or feedback signal. The first selection circuit is coupled to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines a coupling path of the output reference signal or the output feedback signal according to the selection signal.

In some embodiments of the present invention, the first selection circuit includes a first multiplexer and a second multiplexer, and the second selection circuit includes a third multiplexer and a fourth multiplexer.

In some embodiments of the invention, the first selection circuit comprises a first switch and a second switch, and the second selection circuit comprises a third switch and a fourth switch.

In some embodiments of the invention, the selection signal is a first value during the first period, and the first selection circuit sends the reference signal to the first DTC and the feedback signal to the second selection circuit. In the second period, the selection signal is a second value, and the first selection circuit transmits the feedback signal to the first DTC and the reference signal to the second selection circuit. In a first period, the second selection circuit outputs the output reference signal based on a first input from the first DTC and outputs the output feedback signal based on a second input from the first selection circuit, and in a second period, the second selection circuit outputs the output feedback signal based on the first input from the first DTC and outputs the output reference signal based on the second input from the first selection circuit.

In some embodiments of the invention, the Phase Locked Loop (PLL) circuit further comprises a second DTC. The second DTC is coupled to the first selection circuit and the second selection circuit. The second DTC receives a second delay control signal to dither a received reference signal or feedback signal. The first selection circuit transmits a reference signal or a feedback signal to the second DTC according to the selection signal. In accordance with the selection signal, the second selection circuit determines to output the output reference signal based on a first input from the first DTC and to output the output feedback signal based on a second input from the second DTC; alternatively, the output feedback signal is output based on a first input from the first DTC and the output reference signal is output based on a second input from the second DTC.

In some embodiments of the invention, the second selection circuit sends the output reference signal and the output feedback signal to a Phase Frequency Detector (PFD) or a time To Digital Converter (TDC).

In some embodiments of the invention, a Phase Frequency Detector (PFD) is located between the first TDC and the second selection circuit.

In some embodiments of the invention, a Phase Frequency Detector (PFD) is coupled to the first selection circuit, and the Phase Frequency Detector (PFD) is arranged in front of the first selection circuit.

Embodiments of the present invention provide a digital-to-time converter (DTC) error cancellation method. The DTC error cancellation method is applicable to a phase-locked loop (PLL) circuit. The DTC error elimination method comprises the following steps: a first selection circuit of a phase-locked loop (PLL) circuit receives a reference signal and a feedback signal; the first selection circuit sends the reference signal or the feedback signal to a first DTC of a phase-locked loop (PLL) circuit according to a selection signal; the first DTC jitters a received reference signal or feedback signal according to the first delay control signal; a second selection circuit of the phase-locked loop (PLL) circuit determines a path (coupling path) of the output reference signal or the output feedback signal according to the selection signal.

By alternately switching (alternating swappinging) the paths of the reference and feedback signals (e.g., applying DTC dithering alternately on the reference and feedback signals), the present invention can eliminate/remove (remove) or reduce (reduce) DTC non-ideal errors or in-band dither noise without the need for digital calibration. More specifically, the noise phase (noise phase) existing on the reference signal path (i.e., the transmission path of the reference signal) may be copied or backed up to the feedback signal path (i.e., the transmission path of the feedback signal) and then cancelled out (e.g., by the TDC or LPF of the PLL) in the next stage of the PLL. The first delay control signal and the second delay control signal are proposed to maintain the same setting (e.g., the same DTC code, which is used to represent the value of the delay control signal) in two consecutive cycles, thereby ensuring that the same error/noise is applied to the reference signal path and the feedback signal path.

Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of Phase Locked Loop (PLL) circuits and DTC error cancellation methods. The summary is not intended to be limiting and the invention is defined by the claims.

These and other objects of the present invention will be readily apparent to those skilled in the art from the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings.

Drawings

The invention may be more completely understood in consideration of the following detailed description and the examples given in connection with the accompanying drawings, in which:

fig. 1 is a block schematic diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the present invention.

Fig. 3 is a timing diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the invention.

FIG. 4A shows a reference signal CK according to an embodiment of the invention_{IN_REF}And a reference signal CK_{IN_REF}Schematic diagram of an equivalent path of (a);

FIG. 4B shows a reference signal CK according to another embodiment of the present invention_{IN_REF}And a reference signal CK_{IN_REF}Schematic diagram of the equivalent path of (a).

Fig. 5 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention.

Fig. 6 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention.

Fig. 7 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention.

Fig. 8 is a flowchart illustrating a DTC error (error) removal method according to an embodiment of the present invention.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired, and should not be limited to the embodiments set forth in the accompanying drawings.

Detailed Description

The following description is of the preferred embodiments of the present invention, which are provided for illustration of the technical features of the present invention and are not intended to limit the scope of the present invention. Certain terms are used throughout the description and claims to refer to particular elements, it being understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not intend to distinguish between components that differ in name but not function. The terms "component," "system," and "apparatus" used herein may be an entity associated with a computer, wherein the computer may be hardware, software, or a combination of hardware and software. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means either an indirect or direct electrical connection. Thus, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Wherein corresponding numerals and symbols in the various figures of the drawing generally refer to corresponding parts unless otherwise indicated. The accompanying drawings, which are drawn to clearly illustrate the relevant portions of the embodiments, are not necessarily drawn to scale.

The term "substantially" or "approximately" as used herein means within an acceptable range that a person skilled in the art can solve the technical problem to substantially achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner that is acceptable to the skilled artisan with some error from "substantially equal" without affecting the correctness of the results.

Fig. 1 is a block schematic diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the present invention. In an embodiment of the present invention, the phase-locked loop (PLL) circuit 100 may be applied to an all-digital phase-locked loop (ADPLL), but the present invention is not limited thereto. As shown in fig. 1, a phase-locked loop (PLL) circuit 100 may include a first selection circuit (first selection circuit)110, a first digital-to-time converter (DTC)120, and a second selection circuit 130. It should be noted that fig. 1 shows a simplified block diagram in which only the components relevant to the present invention are shown. However, the present invention should not be limited to the schematic structure shown in FIG. 1. The phase-locked loop (PLL) circuit 100 may also include other components. For example, the phase-locked loop (PLL) circuit 100 may further include a phase-frequency detector (PFD), a time-to-digital converter (TDC), a frequency divider (also referred to as a "frequency divider"), a voltage-controlled oscillator (VCO), a low-pass filter (LPF), and the like, but the invention is not limited thereto.

In an embodiment of the present invention, the first selection circuit 110 receives the reference signal CK_{IN_REF}Feedback signal CK_{IN_FB}And a selection signal S_SEL. In one embodiment, the reference signal CK_{IN_REF}Is a reference clock input to a Phase Locked Loop (PLL) circuit 100. In one embodiment, the feedback signal CK_{IN_FB}Is a signal fed back (is feedback from) a Voltage Controlled Oscillator (VCO) (not shown) of the Phase Locked Loop (PLL) circuit 100. In another embodiment, the feedback signal CK_{IN_FB}Is a signal fed back from a frequency divider (not shown) of the Phase Locked Loop (PLL) circuit 100, wherein the frequency divider is arranged between the first selection circuit 110 and the Voltage Controlled Oscillator (VCO) in the Phase Locked Loop (PLL) circuit 100. In one embodiment, the first selection circuit 110 selects the signal S according to the selection signal_SELTo determine/decide (determine) whether to use the reference signal CK_{IN_REF}Whether it is sent to the first digital-to-time converter (DTC)120 or the feedback signal CK_{IN_FB}To a first digital-to-time converter (DTC) 120. For example, in the embodiment shown in FIG. 1, if the first selection circuit 110 is based on the selection signal S_SELDetermining whether to use the reference signal CK_{IN_REF}Transmitted to a first digital-to-time converter (DTC)120, the first selection circuit 110 transmits the reference signal CK_{IN_REF}To a first digital-to-time converter (DTC)120, and a first selection circuit 110 sends a feedback signal CK_{IN_FB}To the second selection circuit 130. If the first selection circuit 110 is based on the selection signal S_SELDetermining whether to use the feedback signal CK_{IN_FB}Sent to the first digital-to-time converter (DTC)120, the first selection circuit 110 sends the feedback signal CK_{IN_FB}To a first digital-to-time converter (DTC)120, anda selection circuit 110 for selecting the reference signal CK_{IN_REF}To the second selection circuit 130. That is, in the embodiment shown in FIG. 1, in the selection signal S_SELUnder the control of (2), the feedback signal CK_{IN_FB}And a reference signal CK_{IN_REF}One of them is sent to a first digital-to-time converter (DTC)120, and a feedback signal CK_{IN_FB}And a reference signal CK_{IN_REF}The other is sent to the second selection circuit 130. It should be noted that in some embodiments, the other may be transmitted to the second selection circuit 130 via other components (e.g., the second DTC140 shown in fig. 5).

For ease of understanding and explanation, the present invention is illustrated in an embodiment using two cycles as an example to achieve DTC reduction. In an embodiment of the present invention, a first digital-to-time converter (DTC)120 receives a first delay control signal D_{DTC_1}Reference signal CK received by jitter (dither)_{IN_REF}Or feedback signal CK_{IN_FB}. Here, it should be noted that dithering the signal is a matter that a person having ordinary skill in the art should understand, and includes, for example and without limitation, "delaying the signal," and for ease of understanding and explanation, the embodiment of the present invention is illustrated with a delay. For example, according to the first delay control signal D_{DTC_1}The first digital-to-time converter (DTC)120 may delay (delay) the received reference signal CK_{IN_REF}Or a received feedback signal CK_{IN_FB}Such as rising edges. In some embodiments, the first delay control signal D_{DTC_1}Is held/maintained (keep) for at least two periods (e.g., the at least two periods are an even number of periods) to ensure that DTC errors in a first period (e.g., a first half of the at least two periods, such as a first one of the two consecutive periods) and DTC errors in a second period (e.g., a second half of the at least two periods, such as a second one of the two consecutive periods) cancel each other out (cancelled). That is, in some embodiments, the first delay control signal D is changed if needed_{DTC_1}Then the first delay control signal D_{DTC_1}Must maintain/maintain (maintain) at leastTwo cycles (e.g., two cycles as an example, the first delay control signal D_{DTC_1}The value in the first period and the first delay control signal D_{DTC_1}The values in the second period are the same). Therefore, the first delay control signal D is changed again if necessary_{DTC_1}Then the first delay control signal D_{DTC_1}It must also last for at least two cycles (e.g., the first delay control signal D for two cycles as an example)_{DTC_1}The value in the third period and the first delay control signal D_{DTC_1}The value in the fourth period is the same). In some embodiments, the DTC error reduction scheme may be implemented using two or more periods, where the two or more periods are an even number of periods, e.g., 2, 4, 6, etc. …, by alternately switching the transmission path of the reference signal and the transmission path of the feedback signal and ensuring that the DTC error in the first half of the period and the DTC error in the second half of the period are the same or substantially the same, thereby enabling the DTC errors to cancel each other. For convenience of description and understanding, the embodiment of the present invention is exemplified by a preferred embodiment taking 2 cycles as an example, however, the present invention should not be limited to this exemplary description, since a person of ordinary skill in the art will understand or be able to correspondingly obtain modified implementations of other even numbers of cycles after reading the embodiment of the present invention. For example, in some embodiments, taking 2N (where N is a positive integer) cycles as an example, in the first N cycles, the select signal has a first value, and the first delay control signal D_{DTC_1}In each of the first N periods, the selection signal has a second value, and the first delay control signal D is controlled by the same or different DTC code, in the last N periods_{DTC_1}The DTC codes are controlled one by the same or different DTC codes in each of the last N periods (it should be noted that the DTC codes may be different in control order in the last N periods). For example, for ease of understanding and explanation, taking 4 cycles as an example, the selection signal has a first value in the first two cycles and a second value in the second two cycles, so if the first delay control signal D is asserted_{DTC_1}The corresponding DTC codes in the first 2 periods are "A", "B" (it should be noted that A, B is only usedMarked as an example), the first delay control signal D is applied_{DTC_1}The corresponding DTC code in the last 2 periods may be "a", "B", or "B", "a", so that similarly switching the coupling paths of the reference signal and the feedback signal according to the selection signal can make the DTC error in the first half period and the DTC error in the second half period the same, thereby being able to reduce the DTC error. It will be appreciated that in some embodiments the period of the selection signal is N times the period of the reference signal, for example in the example of figure 3 the period of the selection signal is 2 times the period of the reference signal.

In an embodiment of the present invention, the second selection circuit 130 selects the signal S according to the selection signal_SELDetermining whether the output of a first digital-to-time converter (DTC)120 is coupled to a reference signal CK serving as (servas) output_{OUT_REF}Is also coupled to serve as an output feedback signal CK_{OUT_FB}Output feedback port (output feedback port). That is, the second selection circuit 130 may determine/determine (determine) a coupling path (coupling paths) between the first digital-to-time converter (DTC)120, the output reference port of the first selection circuit 110 and the second selection circuit 130, and the output feedback port. If the second selection circuit 130 determines that its first input (e.g., the output signal of the first digital-to-time converter (DTC)120) is to be output as the output reference signal CK_{OUT_REF}The second selection circuit 130 will also output its second input (e.g., the output signal of the first selection circuit 110) as the output feedback signal CK_{OUT_FB}. If the second selection circuit 130 decides to output its first input (e.g., the output signal of the first digital-to-time converter (DTC)120) as the output feedback signal CK_{OUT_FB}The second selection circuit 130 also outputs a second input thereof (e.g., the output signal of the first selection circuit 110) as the output reference signal CK_{OUT_REF}. In the embodiment of the present invention, the output reference signal is a signal outputted from the reference signal after passing through at least the first selection circuit 110 and the second selection circuit 130, and is outputted through the output reference port of the second selection circuit, and the output feedback signal is a feedback signal at least passing through the output reference port of the second selection circuitThe signals output by the first selection circuit 110 and the second selection circuit 130 are output through the output feedback port of the second selection circuit. In the embodiment of the present invention, the second selection circuit 130 may further output the reference signal CK_{OUT_REF}And the output feedback signal CK_{OUT_FB}The signal is sent to a phase-frequency detector (PFD)200 (shown in fig. 2) of the phase-locked loop (PLL) circuit 100, and then the signal processed by the phase-frequency detector (PFD)200 is sent to a time-to-digital converter (TDC) (not shown) of the phase-locked loop (PLL) circuit 100. In another embodiment, the second selection circuit 130 may output the reference signal CK_{OUT_REF}And the output feedback signal CK_{OUT_FB}The TDC (not shown) is sent to a Phase Locked Loop (PLL) circuit 100, and in particular, the present invention is not limited thereto.

In the structure of the Phase Locked Loop (PLL) circuit 100 of fig. 1, the first selection circuit 110 is used to select the signal S_SELUnder the control of (2), reference signal CK_{IN_REF}Or feedback signal CK_{IN_FB}Can be sent alternately (alternatively) to the first digital-to-time converter (DTC)120 (e.g., two consecutive periods, in the first period, which may be the reference signal CK_{IN_REF}Is sent to a first digital to time converter (DTC)120 and, in a second cycle, is the feedback signal CK_{IN_FB}Is sent to a first digital-to-time converter (DTC) 120). Accordingly, in the structure of the phase-locked loop (PLL) circuit 100 of fig. 1, since the DTC error can be eliminated or reduced in the phase-locked loop (PLL) circuit 100, there is no need to configure an additional calibration loop circuit for the first digital-to-time converter (DTC)120 in the phase-locked loop (PLL) circuit 100. In addition, in another embodiment of the present invention, the residual high frequency error may be further reduced by a Low Pass Filter (LPF) (not shown) of the Phase Locked Loop (PLL) circuit 100.

Fig. 2 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the present invention. As shown in fig. 2, in an embodiment of the present invention, the first selection circuit 110 may include a first Multiplexer (MUX) 111 and a second MUX112, and the second selection circuit 130 may include a third MUX131 and a fourth MUXFour MUXs 132. For example, in the example of fig. 2, the first MUX 111 and the third MUX131 may receive the selection signal S_SELAnd the second MUX112 and the fourth MUX132 may receive an inversion (inverse) select signalI.e. the selection signal and the inverted selection signal are inverted with respect to each other. The first MUX 111 according to the selection signal S_SELDetermining whether to use reference signal CK_{IN_REF}Or feedback signal CK_{IN_FB}To a first digital-to-time converter (DTC) 120. The second MUX112 selects the signal according to the inversionDetermining whether to use reference signal CK_{IN_REF}Or feedback signal CK_{IN_FB}To the second selection circuit 130. The third MUX131 according to the selection signal S_SELIt is determined whether to output an output signal of the first digital-to-time converter (DTC)120 or the second MUX 112. The fourth MUX132 selects the signal according to the inversionIt is determined whether to output an output signal of the first digital-to-time converter (DTC)120 or the second MUX 112. In addition, the third MUX131 may output the reference signal CK_{OUT_REF}Sent to the Phase Frequency Detector (PFD)200, and the fourth MUX132 may output the feedback signal CK_{OUT_FB}Sent to a Phase Frequency Detector (PFD) 200.

It should be noted that the first selection circuit 110 and the second selection circuit 130 shown in fig. 2 are used to exemplarily illustrate an embodiment of the present invention, and thus, the structures of the first selection circuit 110 and the second selection circuit 130 should not be limited to the schematic diagram of fig. 2. For example, in another embodiment, the first selection circuit 110 may include a first switch and a second switch, and the second selection circuit 130 may include a third switch and a fourth switch. Specifically, the embodiment of the present invention is not limited, and therefore, any circuit that can implement alternate coupling according to the selection signal (for example, alternately coupling the same input terminal to different output terminals) can be used to implement the first selection circuit 110 and the second selection circuit 130.

Fig. 3 is a timing diagram of a phase-locked loop (PLL) circuit 100 according to an embodiment of the invention. As shown in fig. 3, in the first period, the signal S is selected_SELAt a low level (low level), and outputs a reference signal CK_{OUT_REF}A delay occurs in the process. It will be appreciated that the selection signal is a digital signal. Taking fig. 2 as an example, in the first period, for example, the first MUX 111 of the first selection circuit 110 is according to the selection signal S_SELReference signal CK_{IN_REF}To a first digital-to-time converter (DTC)120, and then the first digital-to-time converter (DTC)120 controls the delay according to a first delay control signal D_{DTC_1}Dithering the reference signal CK_{IN_REF}In response to a reference signal CK_{IN_REF}An output signal is generated with a delay. Then, the third MUX131 of the second selection circuit 130 receives the output signal of the first digital-to-time converter (DTC)120 and selects S according to the selection signal_SELUsing it as output reference signal CK_{OUT_REF}Output to a Phase Frequency Detector (PFD) 200. In addition, in the first period, the second MUX112 of the first selection circuit 110 receives the feedback signal CK_{IN_FB}And according to the inverted selection signalThe feedback signal CK_{IN_FB}To the fourth MUX132 of the second selection circuit 130. The fourth MUX132 may then select the signal according to the inversionThe feedback signal CK_{IN_FB}As an output feedback signal CK_{OUT_FB}Output to a Phase Frequency Detector (PFD) 200. Thus, in a first period, the signal diagram of fig. 2 may be substantially equivalent to the diagram of fig. 4A, wherein the Phase Frequency Detector (PFD) is shown in fig. 4A with "+".

In the second period, the signal S is selected_SELAt a high level (high level) and the same delay is applied to the first DTC 120. That is, in the second period, the secondA first MUX 111 of the selection circuit 110 according to the selection signal S_SELTransmitting a feedback signal CK_{IN_FB}To the first digital-to-time converter (DTC)120, and then the first digital-to-time converter (DTC)120 controls the delay according to the first delay control signal D_{DTC_1}Jitter feedback signal CK_{IN_FB}In response to the feedback signal CK_{IN_FB}An output signal is generated with a delay. Due to the control signal D_{DTC_1}The same setting is maintained in the first period and the second period, and therefore, the delay amount (delay amount) in the second period is the same as that in the first period. Then, the fourth MUX132 of the second selection circuit 130 receives the output signal of the first digital-to-time converter (DTC)120 and selects a signal according to the inversionUsing it as output feedback signal CK_{OUT_FB}Output to a Phase Frequency Detector (PFD) 200. In addition, in the second period, the second MUX112 of the first selection circuit 110 may receive the reference signal CK_{IN_REF}And based on the inverted select signalThe reference signal CK_{IN_REF}To the third MUX131 of the second selection circuit 130. Then, the third MUX131 can select the signal S_SELReference signal CK_{IN_REF}As an output reference signal CK_{OUT_REF}Output to a Phase Frequency Detector (PFD) 200. Thus, in the second period, the signal diagram of fig. 2 may be substantially equivalent to the diagram of fig. 4B.

Accordingly, in the third period, compared with the reference signal CK_{IN_REF}Outputs a reference signal CK_{OUT_REF}A second delay (which may be the same or different from the previous delay value) occurs, and, in the fourth period, compared to the feedback signal CK_{IN_FB}Outputs a feedback signal CK_{OUT_FB}The second delay occurs. That is, the first selection circuit 110 selects the signal S according to the selection signal S_SELInterchanging (swap) reference signals CK in each cycle_{IN_REF}And a feedback signal CK_{IN_FB}(ii) a transmission pathtransmission paths). Additionally, in some embodiments, the first delay control signal D is delayed_{DTC_1}The value of (d) is kept constant for at least two cycles to ensure that the DTC error in the first cycle and the DTC error in the second cycle cancel each other out. It should be noted that the timing diagram of fig. 3 is only used to schematically illustrate an embodiment of the present invention, but the present invention is not limited to this example.

Fig. 5 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention. As shown in fig. 5, in an embodiment of the present invention, the phase-locked loop (PLL) circuit 100 may further include a second DTC 140. In an embodiment of the present invention, the second DTC140 may receive a second delay control signal D_{DTC_2}With jittered received reference signal CK_{IN_REF}Or feedback signal CK_{IN_FB}. For example, the second DTC140 controls the delay according to the second delay control signal D_{DTC_2}To delay (delay) the received reference signal CK_{IN_REF}Or feedback signal CK_{IN_FB}Of the edge of (a). In some embodiments, the second delay control signal D_{DTC_2}The value of (d) is kept constant for at least two cycles to ensure that DTC errors in the first cycle and DTC errors in the second cycle cancel each other out. That is, the second delay control signal D is changed if necessary_{DTC_2}Then the second delay control signal D_{DTC_2}Must be maintained for at least two cycles (e.g., the second delay control signal D, for example, two cycles)_{DTC_2}The value in the first period and the second delay control signal D_{DTC_2}The values in the second period are the same). Therefore, the second delay control signal D is changed again if necessary_{DTC_2}Then the second delay control signal D_{DTC_2}It must also last for at least two cycles (e.g., two cycles, for example, the second delay control signal D_{DTC_2}The value in the third period and the second delay control signal D_{DTC_2}The same value in the fourth period). It should be noted that although the second DTC140 is configured in the phase-locked loop (PLL) circuit 100, no additional calibration loop circuitry for the second DTC140 need be configured in the phase-locked loop (PLL) circuit 100.

Taking FIG. 5 as an example, in the first cycle, for example, the first cycleThe first MUX 111 of a selection circuit 110 can be according to the selection signal S_SELReference signal CK_{IN_REF}To a first digital-to-time converter (DTC)120, and then the first digital-to-time converter (DTC)120 controls the delay according to a first delay control signal D_{DTC_1}For reference signal CK_{IN_REF}Performing dithering in response to a reference signal CK_{IN_REF}Producing an output signal with a delay. Then, the third MUX131 of the second selection circuit 130 receives the output signal of the first digital-to-time converter (DTC)120 and can select the signal S according to the selection signal_SELUsing it as output reference signal CK_{OUT_REF}Output to a Phase Frequency Detector (PFD) 200. In addition, the second MUX112 of the first selection circuit 110 may receive the feedback signal CK during the first period_{IN_FB}And based on the inverted select signalThe feedback signal CK_{IN_FB}Is sent to the second DTC140, and the second DTC140 may then control the signal D according to the second delay_{DTC_2}To feedback signal CK_{IN_FB}Performing dithering in response to the feedback signal CK_{IN_FB}An output signal is generated with a delay. Then, the fourth MUX132 of the second selection circuit 130 may receive the output signal of the second DTC140 and select the signal according to the inversionUsing it as output feedback signal CK_{OUT_FB}Output to a Phase Frequency Detector (PFD) 200.

In the second period, the first MUX 111 of the first selection circuit 110 may be according to the selection signal S_SELWill feedback the signal CK_{IN_FB}To a first digital-to-time converter (DTC)120, and then the first digital-to-time converter (DTC)120 may control the signal D according to the first delay_{DTC_1}Jitter feedback signal CK_{IN_FB}In response to the feedback signal CK_{IN_FB}An output signal is generated with a delay. When the control signal D_{DTC_1}While maintaining the same setting in the first and second periods, the delay amount in the second period is the same as that in the first periodThe same delay amount. Then, the fourth MUX132 of the second selection circuit 130 receives the output signal of the first digital-to-time converter (DTC)120 and selects a signal according to the inversionUsing it as output feedback signal CK_{OUT_FB}Output to a Phase Frequency Detector (PFD) 200. In addition, in the second period, the second MUX112 of the first selection circuit 110 may receive the reference signal CK_{IN_REF}And based on the inverted select signalThe reference signal CK_{IN_REF}To the second DTC140, and the second DTC140 may then control the signal D according to the second delay_{DTC_2}Jitter reference signal CK_{IN_REF}In response to a reference signal CK_{IN_REF}An output signal is generated with a delay. When the control signal D_{DTC_2}While the same setting is maintained in the first period and the second period, the delay amount in the second period is the same as the delay amount in the first period. Then, the third MUX131 of the second selection circuit 130 receives the output signal of the second DTC140 and selects S according to the selection signal_SELUsing it as output reference signal CK_{OUT_REF}Output to a Phase Frequency Detector (PFD) 200.

It should be noted that the example of fig. 5 is merely used to schematically illustrate an embodiment of the present invention, but the present invention is not limited to this example. Other operations of the phase-locked loop (PLL) circuit 100 of fig. 5 may be similar to the phase-locked loop (PLL) circuit 100 of fig. 1 and 2. Accordingly, such details will not be repeated here.

Fig. 6 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention. As shown in fig. 6, a Phase Frequency Detector (PFD)200 may be disposed between the first digital-to-time converter (DTC)120 and the second selection circuit 130. It should be noted that in another embodiment of the present invention, the Phase Locked Loop (PLL) circuit 100 of fig. 6 may also include only one DTC, which is similar to the structure of fig. 1. The operation of the phase-locked loop (PLL) circuit 100 of fig. 6 is similar to the phase-locked loop (PLL) circuit 100 of fig. 1 and 2. Therefore, details are not repeated here.

Fig. 7 is a schematic diagram of a phase-locked loop (PLL) circuit 100 according to another embodiment of the present invention. As shown in fig. 7, the Phase Frequency Detector (PFD)200 is coupled to the first selection circuit 110, and the Phase Frequency Detector (PFD)200 is disposed in front of the first selection circuit (front), that is, the reference signal CK_{IN_REF}And a feedback signal CK_{IN_FB}Processed by a Phase Frequency Detector (PFD)200 and transmitted to the first selection circuit 110. It should be noted that in another embodiment of the present invention, the Phase Locked Loop (PLL) circuit 100 of fig. 7 may also include only one DTC, which is similar to the structure of fig. 1. The operation of the phase-locked loop (PLL) circuit 100 of fig. 7 is similar to the phase-locked loop (PLL) circuit 100 of fig. 1 and 2. Therefore, details are not repeated here.

Fig. 8 is a flowchart illustrating a digital-to-time converter (DTC) error cancellation method according to an embodiment of the present invention. The DTC error cancellation method is applicable to a Phase Locked Loop (PLL) circuit 100. As shown in fig. 8, in step S810, a first selection circuit of the phase-locked loop (PLL) circuit 100 receives a reference signal and a feedback signal.

In step S820, the first selection circuit of the phase-locked loop (PLL) circuit 100 transmits the reference signal or the feedback signal (i.e., one of the reference signal and the feedback signal) to the first DTC of the phase-locked loop (PLL) circuit 100 according to the selection signal.

In step S830, the first DTC of the Phase Locked Loop (PLL) circuit 100 jitters the received reference signal or feedback signal according to the first delay control signal.

In step S840, the second selection circuit of the phase-locked loop (PLL) circuit 100 determines a path or a coupling path to output the reference signal or the feedback signal according to the selection signal. For example, taking the example of fig. 6 as an example, it is determined which one of the output signal of the first DTC 120 and the output signal of the second DTC 120 is to be the output reference signal, and accordingly, the other is to be the output feedback signal.

In some embodiments, in the DTC error cancellation method, the first selection circuit of the phase-locked loop (PLL) circuit 100 may include a first multiplexer and a second multiplexer, and the second selection circuit of the phase-locked loop (PLL) circuit 100 may include a third multiplexer and a fourth multiplexer.

In some embodiments, in the DTC error cancellation method, the first selection circuit of the phase-locked loop (PLL) circuit 100 may include a first switch and a second switch, and the second selection circuit of the phase-locked loop (PLL) circuit 100 may include a third switch and a fourth switch.

In some embodiments, in the DTC error cancellation method, in a first period, the selection signal is a first value, and a first selection circuit of the phase-locked loop (PLL) circuit 100 sends the reference signal to a first DTC of the phase-locked loop (PLL) circuit and sends the feedback signal to a second selection circuit of the phase-locked loop (PLL) circuit 100. In the second period, the selection signal is a second value, and the first selection circuit of the phase-locked loop (PLL) circuit 100 sends the feedback signal to the first DTC of the phase-locked loop (PLL) circuit 100 and sends the reference signal to the second selection circuit of the phase-locked loop (PLL) circuit 100. Further, in the DTC error canceling method, in the first period, the second selection circuit of the phase-locked loop (PLL) circuit 100 may output the output reference signal based on its first input from the first DTC (that is, in the first period, output the output signal of the first DTC to the output reference port to use the output signal of the first DTC as the output reference signal), and output the output feedback signal based on its second input from the first selection circuit (that is, output the output signal of the first selection circuit to the output feedback port to use the output signal of the first selection circuit as the output feedback signal). In the second period, the second selection circuit of the phase-locked loop (PLL) circuit 100 may output the output feedback signal based on its first input from the first DTC (that is, in the second period, output the output signal of the first DTC to the output feedback port to use the output signal of the first DTC as the output feedback signal), and output the output reference signal based on its second input from the first selection circuit (that is, output the output signal of the first selection circuit to the output reference port to use the output signal of the first selection circuit as the output reference signal).

In some embodiments of the invention, in the DTC error cancellation method, a second DTC of the Phase Locked Loop (PLL) circuit 100 may receive a second delay control signal to dither a received reference signal or feedback signal. The first selection circuit of the phase-locked loop (PLL) circuit 100 may then send a reference signal or a feedback signal to the second DTC according to the selection signal. Then, according to the selection signal, the second selection circuit of the phase-locked loop (PLL) circuit 100 may determine to output the output reference signal based on the first input (e.g., the output signal of the first DTC) and to output the output feedback signal based on the second input (e.g., the output signal of the second DTC), or to output the output feedback signal based on the first input (e.g., the output signal of the first DTC) from the first DTC and to output the output reference signal based on the second input (e.g., the output signal of the second DTC) from the second DTC.

In some embodiments of the present invention, in the DTC error cancellation method, the second selection circuit of the Phase Locked Loop (PLL) circuit 100 may further send the output reference signal and the output feedback signal to a Phase Frequency Detector (PFD) or a time To Digital Converter (TDC). In some embodiments of the invention, in the DTC error cancellation method, a Phase Frequency Detector (PFD) is arranged between the first TDC and the second selection circuit. In some embodiments of the invention, in the DTC error cancellation method, a Phase Frequency Detector (PFD) is coupled to the first selection circuit, and the Phase Frequency Detector (PFD) is arranged in front of the first selection circuit.

According to the DTC error cancellation method of the present invention, a reference signal and a feedback signal can be alternately transmitted to a DTC of a Phase Locked Loop (PLL) circuit. Therefore, DTC errors can be eliminated or reduced in a Phase Locked Loop (PLL) circuit to reduce mismatch and low frequency noise.

By alternately switching the transmission paths of the reference signal and the feedback signal (e.g., alternately applying DTC jitter to the reference signal and the feedback signal), the present invention can remove or reduce DTC non-ideal errors or in-band jitter noise without digital calibration. More specifically, the noise phases present on the reference signal path may be copied (copied) or duplicated (duplicated) to the feedback signal path and then cancelled out (e.g., by a TDC or LPF of the PLL) in the next stage of the PLL. The present invention proposes that the first delay control signal and the second delay control signal maintain the same setting (e.g. the same DTC code) in two consecutive periods to ensure that the same error/noise is applied to the transmission path of the reference signal and the transmission path of the feedback signal. A scheme with two DTCs (e.g., a first DTC and a second DTC) may have a smaller step size (step size) per DTC than a scheme with one DTC (e.g., a first DTC). However, the first delay control signal and the second delay control signal may be the same or different. For example, the first delay control signal may have a varying DTC code, while the second delay control signal may have a fixed DTC code.

Although the present invention has been described in connection with certain specific embodiments for instructional purposes, the present invention is not limited thereto. The subject matter described herein sometimes describes different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact, other architectures can be implemented which achieve the same functionality. Conceptually, any arrangement of components that achieves the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or intermedial components. Similarly, any two components so associated can also be viewed as being "operably connected," or "operably coupled," to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being "operably couplable," to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting with each other and/or logically interacting and/or logically interactable components.

Furthermore, for any plural and/or singular terms used herein, those having skill in the art can translate from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or application. For the sake of clarity, various permutations between the singular/plural are expressly set forth herein.

Furthermore, it will be understood by those within the art that, in general, terms used herein, and especially in the appended claims, such as in the main claim body, are generally intended to have an "open" meaning, e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," etc. It will be further understood by those within the art that if a claim recitation is intended to include a specific numerical value, such an intent will be explicitly recited in the claim, and if not, such intent will be absent. To facilitate understanding, for example, the appended claims may contain introductory phrases such as "at least one" and "one or more" to introduce claim recitations. However, such phrases should not be construed to limit the claim recitation to: the introduction of the indefinite articles "a" or "an" means that any particular claim containing such an introductory claim recitation is limited to an embodiment containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" similarly, i.e., "a" or "an" should be interpreted to mean "at least one" or "one or more". Also, the use of definite articles to introduce claim recitations is equivalent. In addition, even if a specific value is explicitly recited in a claim recitation, those skilled in the art will recognize that such recitation should be interpreted to include at least the recited values, e.g., the bare recitation of "two recitations," without any other recitation, means at least two recitations, or two or more recitations. Further, if a similarity of "at least one of A, B and C, etc." is used, it is generally understood by those skilled in the art that a "system having at least one of A, B and C" would include, but not be limited to, a system having only A, a system having only B, a system having only C, a system having A and B, a system having A and C, a system having B and C, and/or a system having A, B and C, etc. If a "A, B or C or the like" similarity is used, it will be understood by those skilled in the art that, for example, "a system having at least one of A, B or C" will include but not be limited to systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and/or A, B and C together, and the like. It will be further understood by those within the art that virtually all disjunctive words and/or phrases connecting two or more alternative words or phrases appearing in the specification, claims, or drawings are to be understood to contemplate all possibilities, including one of the words or both words or phrases. For example, the phrase "a or B" should be understood to include the following possibilities: "A", "B" or "A and B".

From the foregoing, it will be appreciated that various embodiments of the present application have been described herein for purposes of illustration, and that various modifications may be made to the embodiments without deviating from the scope and spirit of the invention. Therefore, the various embodiments disclosed herein are not to be considered in a limiting sense, with the true scope and spirit being indicated by the following claims.

While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art), e.g., combinations or substitutions of different features in different embodiments. The scope of the appended claims should, therefore, be accorded the broadest interpretation so as to encompass all such modifications and similar structures.