阅读说明：本技术 半导体器件、制作半导体器件的方法及处理系统 (Semiconductor device, method of manufacturing semiconductor device, and processing system ) 是由 高拉夫·塔雷贾 李学斌 阿布舍克·杜贝 黄奕樵 罗源辉 帕特里夏·M·刘 桑杰·纳塔拉扬 于 2020-01-27 设计创作，主要内容包括：本公开内容大致上关于形成半导体器件的方法、一种半导体器件及一种处理腔室。该方法包括：在处理系统中形成源极/漏极区域；在该处理系统中于该源极/漏极区域上形成掺杂的半导体层；形成金属硅化物层；形成介电材料；在该介电材料中形成沟槽；以及以导体填充该沟槽。在不破真空的情况下形成该源极/漏极区域、该掺杂的半导体层和该金属硅化物层。一种半导体器件包括多个层,且该半导体器件具有减小的接触电阻。一种处理系统被配置成执行该方法并且形成该半导体器件。本公开内容的实施方式使得能够通过使用整合工艺形成具有减小的接触电阻的源极/漏极接触,该整合工艺容许在同一处理系统内执行形成源极/漏极接触的各种操作。(The present disclosure generally relates to methods of forming semiconductor devices, a semiconductor device, and a processing chamber. The method comprises the following steps: forming source/drain regions in a processing system; forming a doped semiconductor layer on the source/drain region in the processing system; forming a metal silicide layer; forming a dielectric material; forming a trench in the dielectric material; and filling the trench with a conductor. The source/drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking vacuum. A semiconductor device includes a plurality of layers and has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. Embodiments of the present disclosure enable the formation of source/drain contacts with reduced contact resistance by using an integrated process that allows various operations for forming the source/drain contacts to be performed within the same processing system.)

1. A method for forming a semiconductor device, the method comprising:

forming a source/drain region on a substrate;

forming a doped semiconductor layer on the source/drain regions;

forming a metal silicide layer on the doped semiconductor layer in a processing system, wherein the source/drain regions, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum;

forming a dielectric material over the metal silicide layer;

forming a trench in the dielectric material to expose a portion of the metal silicide layer; and

the trench is filled with a conductor.

2. The method of claim 1, wherein the method is performed in a single processing system.

3. The method of claim 1, wherein the doped semiconductor layer wraps around the source/drain region.

4. The method of claim 1, wherein said metal silicide layer wraps around said source/drain regions.

5. A semiconductor device, comprising:

a source/drain region extending from the semiconductor structure;

a doped semiconductor layer disposed on and encasing the source/drain region;

a metal silicide layer disposed on the doped semiconductor layer and wrapping around the source/drain regions; and

a conductor disposed on the metal silicide layer.

6. The semiconductor device of claim 5, wherein the source/drain region comprises silicon, germanium, silicon germanium, or a group III/V compound semiconductor.

7. The semiconductor device of claim 6, wherein said source/drain regions are doped with a dopant.

8. The semiconductor device of claim 7, wherein a dopant concentration of the doped semiconductor layer is higher than a dopant concentration of the source/drain region.

9. The semiconductor device of claim 5, wherein said source/drain regions comprise a metal silicide.

10. The semiconductor device of claim 5, further comprising a contact etch stop layer disposed on a portion of the metal silicide layer.

11. The semiconductor device of claim 10, wherein the contact etch stop layer comprises a dielectric material.

12. A processing system, comprising:

a transfer chamber;

a plurality of processing chambers coupled to the transfer chamber; and

a controller configured to cause a process to be performed in the processing system, the process comprising:

forming source/drain regions;

forming a doped semiconductor layer on the source/drain regions; and

forming a metal silicide layer on the doped semiconductor layer, wherein the source/drain regions, the doped semiconductor layer, and the metal silicide layer are formed without breaking a vacuum.

13. The processing system of claim 12, wherein the process further comprises: forming a dielectric material over the metal silicide layer; forming a trench in the dielectric material to expose a portion of the metal silicide layer; and filling the trench with a conductor.

14. The processing system of claim 13, wherein the process further comprises: forming a capping layer on the metal silicide layer, wherein the capping layer comprises a dielectric material.

15. The processing system of claim 12, further comprising a pre-clean chamber.

Technical Field

Embodiments of the present disclosure generally relate to an apparatus and method, and more particularly, to a semiconductor device, a method of fabricating a semiconductor device, and a processing system.

Background

Transistors are a fundamental device element of modern digital processors and memory devices, and have found application in high power electronics. Currently, there are a variety of semiconductor device (e.g., transistor) designs or types that may be used for different applications. Various transistor types include, for example, Field Effect Transistors (FETs), Bipolar Junction Transistors (BJTs), Junction Field Effect Transistors (JFETs), Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), vertical channel or trench field effect transistors, and super junction or multi-drain transistors. One type of transistor that has emerged in the MOSFET family of transistors is the fin field effect transistor (FinFET).

Finfets may be fabricated on a bulk semiconductor substrate (e.g., a silicon substrate) and include fin structures that extend in a length direction along a surface of the substrate and in a height direction perpendicular to the substrate surface. The fins have a narrow width (e.g., less than 250 nanometers). The fin can pass through the insulating layer. A gate structure including a conductive gate material and a gate insulator can be formed over a region of the fin. The upper portion of the fin is doped on either side of the gate structure to form source/drain regions adjacent the gate.

Finfets have good electrostatic properties for complementary MOSFETs that scale to smaller sizes. Because the fin is a three-dimensional structure, the channel of the transistor can be formed on three surfaces of the fin, so that the FinFET can exhibit high current switching capability for a given surface area occupied on the substrate. Since the channel and devices can be elevated from the substrate surface, there can be reduced electric field coupling between adjacent devices compared to conventional planar MOSFETs.

A key challenge in semiconductor design, fabrication, and operation is contact resistance. For example, the source and drain regions of a FinFET device may be eroded by the etching process used to form the source/drain contact trenches, resulting in increased contact resistance. As a result of the increased contact resistance, the performance of circuit devices, including transistors and other device structures formed on semiconductor substrates, is reduced.

Accordingly, there is a need for improved semiconductor processing methods for forming semiconductor devices with reduced contact resistance.

Disclosure of Invention

Embodiments of the present disclosure generally relate to a semiconductor device, a method of manufacturing a semiconductor device, and a processing system. The method results in a semiconductor device having reduced contact resistance. The method can be performed in the processing system.

In one embodiment, a method for forming a semiconductor device is provided. The method comprises the following steps: forming source/drain regions in a substrate; forming a doped semiconductor layer on the source/drain region; forming a metal silicide layer on the doped semiconductor layer in the processing system; forming a dielectric material over the metal silicide layer; forming a trench in the dielectric material to expose a portion of the metal silicide layer; and filling the trench with a conductor. The source/drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking vacuum.

In another embodiment, a semiconductor device is provided. The semiconductor device includes: a source/drain region extending from the semiconductor structure; a doped semiconductor layer disposed on and encasing the source/drain region; a metal silicide layer disposed on the doped semiconductor layer and wrapping around the source/drain region; and a conductor disposed on the metal silicide layer.

In yet another embodiment, a processing system is provided. The processing system comprises: a transfer chamber; a plurality of processing chambers coupled to the transfer chamber; and a controller. The controller is configured to cause a process to be performed in the processing system, the process comprising: forming source/drain regions; forming a doped semiconductor layer on the source/drain region; and forming a metal silicide layer on the doped semiconductor layer. The source/drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking vacuum.

Drawings

So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope of the disclosure, for the disclosure may admit to other equally effective embodiments.

Fig. 1 is a flow chart of the method operations for forming a semiconductor device, according to one embodiment.

Fig. 2A to 2H illustrate cross-sectional views of a substrate according to an embodiment.

Fig. 3 shows a schematic top view of a processing system according to an embodiment.

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

Detailed Description

Embodiments described herein include a method of forming a semiconductor device, and a processing system. The method comprises the following steps: forming source/drain regions; forming a doped semiconductor layer; forming a metal silicide layer on the doped semiconductor layer; forming a dielectric material; forming a trench in the dielectric material; and filling the trench with a conductor. The source/drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking vacuum. A semiconductor device can be formed by the method. The semiconductor device includes a plurality of layers, and the semiconductor device has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device. The dopant concentration of the doped semiconductor layer is higher than that of the source/drain regions, and the higher dopant concentration results in a reduction in contact resistance. Embodiments disclosed herein can be used in, but are not limited to, semiconductor devices with reduced contact resistance.

The techniques described in this disclosure are generally presented above. It is contemplated that the concepts of the present disclosure can be implemented with respect to planar transistor devices or three-dimensional transistor devices such as fin field effect transistors (finfets), Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, nanowire channel FETs, strained semiconductor devices, and the like.

As used herein, the term "about" refers to +/-10% deviation from the nominal value. It is to be understood that such a deviation can be included in any of the values provided herein.

Fig. 1 is a flow chart of the method 100 operations for forming a semiconductor device according to one embodiment. Fig. 2A to 2H illustrate cross-sectional views of a substrate 200 according to an embodiment. Although the operations of method 100 are described in conjunction with fig. 1 and 2A-2D, those skilled in the art will understand that any system configured to perform the method operations in any order is within the scope of the embodiments described herein. Note that the method 100 can be used to form any other semiconductor structure not presented herein. Those skilled in the art will recognize that the complete process for forming semiconductor devices and related structures is not shown in the figures or described herein.

The method 100 begins at operation 102 by placing a substrate 200 into a processing chamber. In one example, the processing chamber is an etch chamber. As shown in fig. 2A, the substrate 200 includes a semiconductor layer 202, at least one semiconductor structure 204 extending from the semiconductor layer 202, and a dielectric material 206 disposed between adjacent semiconductor structures 204 on the semiconductor layer 202. The semiconductor structure 204 can be a semiconductor fin. The semiconductor layer 202 can be made of silicon, germanium, silicon germanium, a group III/V compound semiconductor, gallium arsenide (GaAs) and/or indium gallium arsenide (InGaAs), or other semiconductor materials. The semiconductor layer 202 can be doped with either p-type or n-type dopants. For example, the semiconductor layer 202 is doped with a P-type dopant such As boron (B), or with an n-type dopant such As phosphorus (P) and/or arsenic (As). The semiconductor structure 204 may be made of the same material as the semiconductor layer 202. The semiconductor structure 204 may be integrated with the semiconductor layer 202. The dielectric material 206 may include Shallow Trench Isolation (STI) regions, and mayFrom carbon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon carbonitride (SiCN), mixtures of the above, or any other suitable dielectric material.

At operation 104, a portion of the at least one semiconductor structure 204 is removed, exposing a surface 207 of the remaining portion of the semiconductor structure 204. The surface 207 of the semiconductor structure 204 may be recessed from the surface 209 of the dielectric material 206, as shown in fig. 2B. In other embodiments, surface 207 is coplanar with surface 209 of dielectric material 206. The portion of the semiconductor structure 204 may be removed by an etch process performed in an etch chamber.

In operation 106, source/drain regions 208 are formed on the surface 207 of the semiconductor structure 204. The source/drain regions 208 may be source regions or drain regions, as shown in fig. 2C. The source/drain regions 208 may include merged source and drain regions 208. In either example, the source/drain regions 208 are made of a semiconductor material that is epitaxially grown on the surface 207 of the semiconductor structure 204. The source/drain regions 208 may be formed in an epitaxial deposition chamber of a processing system. The substrate 200 may include a plurality of gates (not shown) disposed across the source/drain regions 208.

In one implementation that can include or be combined with one or more implementations described herein, the source/drain regions 208 are made of silicon, germanium, silicon germanium, or a group III/V compound semiconductor, such as gallium arsenide (GaAs) and/or indium gallium arsenide (InGaAs), or any other suitable semiconductor. The source/drain regions 208 may be doped with p-type or n-type dopants. In one example, the source/drain regions 208 are doped with a p-type dopant such as B. Alternatively, the source/drain regions 208 are doped with n-type dopants such As P and/or As. The source/drain regions 208 may be made of a metal silicide, such as titanium silicide, tungsten silicide, molybdenum silicide, ruthenium silicide, cobalt silicide, or any combination of the above materials.

The metal silicide source/drain regions 208 have a reduced resistance compared to the semiconductor source/drain regions 208. The source/drain regions 208 are selectively epitaxially grown on the surface 207 of the semiconductor structure 204 and, due to the different growth rates on the different surface planes, facets (facets) 210, 212, 214, 216 can be formed such that the source/drain regions 208 have a diamond shape, as shown in fig. 2C.

A pre-clean process may be performed on the surface 207 of the semiconductor structure 204 prior to forming the source/drain regions 208. A preclean process is performed to remove contaminants, such as carbon or oxide contaminants, on the surface 207 of the semiconductor structure 204. The pre-clean process may include any suitable etching process, such as dry etching, wet etching, or a combination thereof. The precleaning process may be isotropic (isotropic) or directional. In one example, a pre-clean process is performed in a processing chamber using a remote plasma source. One example processing chamber suitable for performing the Pre-cleaning process is AKTIV Pre-Clean available from applied materials, Inc. of Santa Clara, Calif^TMThe chamber isThe chamber is cleaned. Alternatively, the pre-clean process is performed in an etch chamber, such as an etch chamber using an Inductively Coupled Plasma (ICP) source. One exemplary etch chamber may be a modified Decoupled Plasma Nitridation (DPN) chamber available from applied materials corporation of Santa Clara, california. However, it is contemplated that other suitably configured chambers from other manufacturers could be implemented to perform the pre-clean process.

In operation 108, as shown in fig. 2D, a doped semiconductor layer 220 is formed on the source/drain regions 208 in the processing system. The doped semiconductor layer 220 may be formed by a selective epitaxial deposition process. The doped semiconductor layer 220 is formed in the same processing system as the source/drain regions 208. In one example, the doped semiconductor layer 220 is formed in the same epitaxial deposition chamber as the source/drain regions 208. In another example, the doped semiconductor layer 220 is formed in a different epitaxial deposition chamber of a processing system. Because the source/drain regions 208 and the doped semiconductor layer 220 are formed in the same processing system, there is no vacuum break between the processes (e.g., operations 106 and 108). Thus, no pre-cleaning process is required between processes.

A doped semiconductor layer 220 is formed on the facets 210, 212, 214, 216, but not on the dielectric material 206. Because the doped semiconductor layer 220 is formed by an epitaxial deposition process, the doped semiconductor layer 220 conformally covers the facets 210, 212, 214, 216 of the source/drain region 208. In other words, the conformal doped semiconductor layer 220 wraps around the source/drain region 208. The selective epitaxial deposition process may be performed while maintaining the substrate at a temperature of less than about 450 ℃. The doped semiconductor layer 220 may be made of the same material as the source/drain regions 208, with the difference that the dopant concentration in the doped semiconductor layer 220 is substantially higher than the dopant concentration in the source/drain regions 208. For example, the doped semiconductor layer 220 may be made of germanium tin (GeSn) doped with B and/or gallium (Ga), silicon germanium (SiGe) doped with B, germanium (Ge) doped with B and/or Ga, or silicon doped with P and/or As. In one example, the doped semiconductor layer 220 includes a first layer and a second layer, and the first layer is a silicon layer doped with As and the second layer is a silicon layer doped with P.

According to one embodiment, the doped semiconductor layer 220 is formed by a dopant dip process. During the dopant soaking process, the outer portions of the source/drain regions 208 (such as from each facet 210, 212, 214, 216 to a predetermined depth) are converted into a doped semiconductor layer 220. For example, during a dopant soak process, the facets 210, 212, 214, 216 of the source/drain regions 208 are exposed to one or more gases containing one or more dopants, such As Ga, B, P, and/or As. The doped semiconductor layer 220 may have a thickness in the range of about 1 angstrom to about 10 nm. The dopant concentration in the source/drain regions 208 is less than the dopant concentration in the doped semiconductor layer 220. The increased dopant concentration in the doped semiconductor layer 220 reduces contact resistance.

The doped semiconductor layer 220 may be formed in a Reduced Pressure (RP) epitaxial chamber available from applied materials, Santa Clara, california. However, it is contemplated that other suitably configured chambers from other manufacturers can also be implemented to perform selective epitaxial deposition or dopant soak processes to form the doped semiconductor layer 220.

At operation 110, as shown in FIG. 2E, a metal silicide layer 222 is formed on the doped semiconductor layer 220 in the processing system. In one example, the metal silicide layer 222 is formed by a Chemical Vapor Deposition (CVD) process. In another example, metal silicide layer 222 is formed by an epitaxial deposition process. For example, as a result of the selective epitaxial deposition process, metal silicide layer 222 is formed on doped semiconductor layer 220 and not on dielectric material 206. Because the metal silicide layer 222 is formed by an epitaxial deposition process, the metal silicide layer 222 conformally covers the facets 210, 212, 214, 216 of the source/drain regions 208. In other words, the conformal metal silicide layer 222 wraps around the source/drain regions 208.

Metal silicide layer 222 may comprise titanium silicide, cobalt silicide, ruthenium silicide, tungsten silicide, molybdenum silicide, any combination of the above materials, or other suitable metal silicides. In one example, the metal silicide layer 222 is formed in the same processing chamber as the doped semiconductor layer 220. In another example, the metal silicide layer 222 is formed in a different processing chamber of the processing system, such as an epitaxial deposition chamber. Because the doped semiconductor layer 220 and the metal silicide layer 222 are formed in the same processing system, no vacuum is created between these processes (e.g., operations 108 and 110). No pre-cleaning process is required between these processes.

An optional capping layer may be formed on the metal suicide layer 222. The capping layer may include a dielectric. The capping layer may be made of a nitride or oxide material such as titanium nitride, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, manganese oxide, or any combination of the above materials. In some embodiments, the capping layer is formed by nitriding the metal silicide layer 222, and the capping layer is a metal silicon nitride layer. The nitridation process may include exposing the metal silicide layer 222 to a nitrogen-containing plasma or a nitrogen-containing ambient environment such that the nitrogen atoms chemically react with atoms located on the exposed surface of the metal silicide layer 222 to form a surface nitride layer (e.g., a capping layer). The nitridation process may be performed in the plasma chamber using a plasma source, such as an Inductively Coupled Plasma (ICP) source, a Capacitively Coupled Plasma (CCP) source, or a combination of the above plasma sources. The nitridation process may be performed in a modified Decoupled Plasma Nitridation (DPN) chamber available from applied materials corporation of Santa Clara, california, usa or other suitable chamber.

At operation 112, a Contact Etch Stop Layer (CESL)224 is formed on the dielectric material 206 and the metal silicide layer 222, as shown in fig. 2F. CESL 224 is made of, for example, a dielectric material such as silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

At operation 114, a dielectric material 226 is formed on the CESL 224, as shown in figure 2F. The dielectric material 226 may be an interlayer dielectric and may be made of a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof.

At operation 116, as shown in fig. 2G, a trench 228 is formed in the dielectric material 226 to expose a portion of the metal suicide layer 222 disposed over the facets 210, 212. A trench 228 is formed by removing a portion of dielectric material 226 and CESL 224 disposed over the facets 210, 212 of the source/drain regions 208 and exposing a portion of the metal suicide layer 222. The trench 228 can be formed by any suitable removal process. In one example, the trench 228 is formed by a Reactive Ion Etch (RIE) process. The trench 228 may be formed in an RIE chamber or other suitable etch chamber.

At operation 118, as shown in fig. 2H, a conductor 230 is formed in the trench 228 to fill the trench 228. The conductor 230 is made of a conductive material such as metal. In one example, conductor 230 includes cobalt. Conductor 230 may be formed by one or more deposition processes. For example, the conductor 230 may be formed by first forming a seed layer, and then forming a bulk (bulk) fill on the seed layer. The seed layer and the bulk fill are made of the same material. Conductor 230 may be formed by any suitable deposition method, such as Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD). Thus, the method 100 results in the formation of a semiconductor device 290.

Operations 106, 108, and 110 are performed to reduce contact resistance of source/drain contacts in a transistor. In some embodiments, one or more of operations 108 and 110 may be omitted while still achieving reduced contact resistance.

In one implementation that can include or be combined with one or more implementations described herein, operation 106 is performed and then operation 112 is performed without performing operations 108 and 110. For example, CESL 224 is formed on the source/drain regions 208 after the metal silicide source/drain regions 208 are formed, without forming the doped semiconductor layer 220 and the metal silicide layer 222 between the source/drain regions 208 and the CESL 224.

Fig. 3 shows a schematic top view of a processing system 300 according to an embodiment. The processing system 300 is configured to perform the method 100. Examples of treatment systems that can be suitably modified in accordance with the teachings provided herein include those available from applied materials, Inc. of Santa Clara, Calif OrAn integrated processing system or other suitable processing system. It is contemplated that other processing systems (including processing systems from other manufacturers) may also be adapted to benefit from the aspects described herein.

As shown, the processing system 300 includes a plurality of processing chambers 302, 314, 316, a first transfer chamber 304, a pass-through chamber 306, a second transfer chamber 310, a Factory Interface (FI)320, a pod (pod)330, and a system controller 380. A plurality of processing chambers 302 are coupled to a first transfer chamber 304. The first transfer chamber 304 is also coupled to a first pair of through-chambers 306. The first transfer chamber 304 has a centrally disposed transfer robot (not shown) for transferring substrates between the pass-through chamber 306 and the processing chamber 302. The pass-through chamber 306 is coupled to a second transfer chamber 310, the second transfer chamber 310 being coupled to a processing chamber 314 configured to perform a pre-clean process and a processing chamber 316 configured to perform a selective epitaxial deposition process (operations 106, 108, 110). The second transfer chamber 310 has a centrally disposed transfer robot (not shown) for transferring substrates between a set of load lock chambers 312 and either process chambers 314 or 316. The factory interface 320 is connected to the second transfer chamber 310 through the load lock chamber 312. The factory interface 320 is coupled to one or more cassettes 330 located on opposite sides of the load lock chamber 312. The cassette 330 is typically a Front Opening Unified Pod (FOUP) that can be accessed from a clean room.

During operation, the substrate is first transferred to the processing chamber 314 where a pre-clean process is performed to remove contaminants, such as carbon or oxide contaminants, from the exposed surfaces of the semiconductor structure. The substrate is then transferred to the processing chamber 316 where operations 106, 108, and 110 are performed. In some embodiments, the process chamber 314 and/or the process chamber 316 can be switched with any of the one or more process chambers 302. In some embodiments, the operations 106, 108, 110 are performed in different process chambers 302. For example, operation 106 is performed in a first process chamber 302, operation 108 is performed in a second process chamber 302, and operation 110 is performed in a third process chamber 302.

The substrate is then transferred to one or more processing chambers 302 where operations 112 through 118 are performed. Because all of the operations 106, 108, 110, 112, 114, 116, 118 are performed within the same processing system 300, no vacuum is broken while transferring the substrates to the various chambers, which reduces the chance of contamination and improves the quality of the deposited epitaxial film.

A system controller 380 is coupled to the processing system 300 to control the processing system 300 or components thereof. For example, the system controller 380 controls the operation of the processing system 300 using direct control of the chambers 302, 304, 306, 310, 312, 314, 316, the factory interface 320, and the cassette 330 of the processing system 300. In another example, the system controller 380 controls the respective controllers associated with the chambers 302, 304, 306, 310, 312, 314, 316, the factory interface 320, and the cassette 330. In operation, the system controller 380 enables data collection and feedback from the various chambers to coordinate the performance of the processing system 300.

The system controller 380 generally includes a Central Processing Unit (CPU)382, a memory 384, and support circuits 386. The CPU382 may be one of any form of general purpose processor that can be used in an industrial setting. The memory 384, non-transitory computer readable medium or machine readable storage device is accessible by the CPU382 and can be one or more of the following: such as Random Access Memory (RAM), Read Only Memory (ROM), floppy disk, hard disk, or any other form of digital storage, local or remote. The support circuits 386 are coupled to the CPU382 and can include cache, clock circuits, input/output subsystems, power supplies, and the like. The system controller 380 is configured to execute the method 100 stored in the memory 384. The various embodiments disclosed in the present disclosure can be implemented generally under the control of the CPU382 by executing computer instruction code stored in the memory 384 (or the memory of a particular process chamber), for example, as a computer program product or software program. That is, the computer program product is tangibly embodied on the memory 384 (or a non-transitory computer-readable medium or machine-readable storage device). When the CPU382 executes the computer instruction code, the CPU382 controls the chamber to perform operations according to various embodiments.

As described above, the method comprises: the method includes forming source/drain regions in a processing system, forming a doped semiconductor layer on the source/drain regions in the processing system, forming a metal silicide layer on the doped semiconductor layer in the processing system, forming a dielectric material over the metal silicide layer, forming a trench in the dielectric material to expose a portion of the metal silicide layer, and filling the trench with a conductor. The source/drain regions, the doped semiconductor layer and the metal silicide layer are formed without breaking vacuum. The semiconductor device includes a plurality of layers and has reduced contact resistance. A processing system is configured to perform the method and form the semiconductor device.

Embodiments of the present disclosure enable the formation of source/drain contacts with reduced contact resistance by using an integrated process that allows various operations of forming the source/drain contacts to be performed within the same processing system. In some embodiments, after forming the source/drain regions, a doped semiconductor layer is formed on the source/drain regions. The doped semiconductor layer has a higher dopant concentration than the source/drain regions, and the higher dopant concentration results in reduced contact resistance.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.