阅读说明：本技术 采用错误计数器和内部地址生成的管芯上ecc (On-die ECC with error counter and internal address generation ) 是由 J·B·哈尔伯特 K·S·拜因斯 于 2016-05-27 设计创作，主要内容包括：本发明涉及采用错误计数器和内部地址生成的管芯上ECC,以及涉及一种存储器子系统实现管理错误纠正信息。存储器装置对存储器位置的范围内部执行错误检测,并且对所检测的各错误使内部计数递增。存储器装置包括ECC逻辑,以生成指示内部计数与对存储器装置预设的错误的基准数量之间的差的错误结果。存储器装置能够向系统的关联主机提供错误结果,以便仅暴露所累加的错误数量,而没有从结合到系统中之前暴露内部错误。能够使存储器装置能够生成内部地址,以运行从存储器控制器所接收的命令。能够使存储器装置能够在经过在其中对错误计数的存储区的第一遍之后重置计数器。(The present invention relates to on-die ECC employing error counters and internal address generation, and to a memory subsystem implementation managing error correction information. The memory device performs error detection internally to the range of memory locations and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device is capable of providing error results to an associated host of the system so that only the accumulated number of errors is exposed, without exposing internal errors from before incorporation into the system. The memory device can be enabled to generate an internal address to execute a command received from the memory controller. The memory device can be enabled to reset the counter after a first pass through the memory area in which errors are counted.)

1. A Random Access Memory (RAM) device, comprising:

a memory array; and

an Error Checking and Correcting (ECC) module to perform ECC operations on a plurality of rows of a memory array, the ECC module including a counter to accumulate an error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC module is to generate an error result as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result.

2. The RAM device of claim 1, wherein the ECC module is to perform the ECC operation in response to an error detection test being initiated by the RAM device.

3. The RAM device of claim 1, wherein the ECC module is to perform ECC operations on the plurality of rows of the memory array within a bounded address space.

4. The RAM device of claim 1, wherein the ECC module is to perform ECC operations on all rows of the memory array.

5. The RAM device of claim 1, wherein the ECC module is to internally generate address information for the plurality of rows of the memory array.

6. The RAM device of claim 5, wherein the ECC module is to automatically reset the accumulated error count in response to detecting an address flip to a previously tested address.

7. The RAM device of claim 1, wherein the ECC module further comprises a register to store the error result to indicate a number of errors since deployment into a system.

8. The RAM device of claim 7, wherein the registers comprise registers accessible by an associated memory controller.

9. The RAM device of claim 1, wherein the baseline number of errors comprises a number of errors detected during manufacturing testing of the RAM device.

10. The RAM device of claim 1, wherein the RAM device comprises a volatile Dynamic Random Access Memory (DRAM) device.

11. The RAM device of claim 1, wherein the RAM device comprises a non-volatile RAM device.

12. A system, comprising:

a memory controller; and

a plurality of Random Access Memory (RAM) devices coupled in parallel, wherein the RAM devices comprise:

a memory array; and

an Error Checking and Correcting (ECC) module to perform ECC operations on a plurality of rows of the memory array, the ECC module including a counter to accumulate an error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC module is to generate an error result as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result;

wherein the RAM device provides internal error correction to data independent of error correction based on check bits provided by the memory controller.

13. The system of claim 12, wherein the ECC module is to perform the ECC operation in response to an error detection test being initiated by the RAM device.

14. The system of claim 12, wherein the ECC module is to internally generate address information for the plurality of rows of the memory array.

15. The system of claim 14, wherein the ECC module is to automatically reset the accumulated error count in response to detecting an address rollover to a previously tested address.

16. The system of claim 12, wherein the ECC module further comprises a register to store the error result to indicate a number of errors since deployment into a system.

17. The system of claim 16, wherein the registers comprise registers accessible by an associated memory controller.

18. The system of claim 12, wherein the RAM device comprises a volatile Dynamic Random Access Memory (DRAM) device.

19. The system of claim 12, wherein the RAM device comprises a non-volatile RAM device.

20. The system of claim 12, further comprising one or more of:

at least one processor communicatively coupled to the memory controller;

a display communicatively coupled to the at least one processor; or

A network interface communicatively coupled to the at least one processor.

21. A method for managing error correction information in a memory, comprising:

initiating an Error Check and Correction (ECC) operation on multiple rows of a memory array with an ECC module within a Synchronous Dynamic Random Access Memory (SDRAM) device;

accumulating an error count to be incremented in response to detecting an error in any of the plurality of rows; and

an error result is generated as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result.

22. The method of claim 21, further comprising:

internally generating information for the plurality of row addresses of the memory array.

23. The method of claim 22, further comprising:

automatically resetting the accumulated error count in response to detecting an address flip to a previously tested address.

24. The method of claim 21, further comprising storing the error result in a register to indicate a number of errors since deployment into a system.

Technical Field

Embodiments of the invention relate generally to memory devices and, more particularly, to memories that provide selective internal error correction information.

Copyright notice/permission

Portions of the disclosure of this patent document may contain material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the patent and trademark office patent file or records, but otherwise reserves all copyright rights whatsoever. The copyright notice applies to all data described below and in the drawings and any software described below: copyright 2015, Intel Corporation, copyright owner, must not be reprinted.

Background

Computing devices use memory devices to store data and code for processors to perform their operations. As the size of memory devices decreases and the density increases, they encounter more errors during processing, known as yield issues. Thus, memory devices suffer from increased bit failures even with modern processing techniques. To mitigate bit failures, modern memory devices provide internal error correction mechanisms, such as ECC (error correction code). The ECC data is generated internally in the memory device and used internally in the memory device. Internal error correction within a memory device can supplement whatever system-wide error correction or error mitigation the system is configured to use in data exchanges between the memory device and the memory controller.

The SBE (single bit error) corrected by the memory device appears to the memory controller or host system as if there were no errors. Thus, if additional errors accumulate in the memory device after manufacture, the memory device will continue to perform ECC and the increased number of failures of the memory device may not be visible to the host system. Memory devices may traditionally need to identify information related to internal error correction to provide information related to error accumulation. However, exposing error correction information can provide proprietary information about the process and manufacturing, such as internal error information or details about internal error correction. There is currently no mechanism to reveal information related to error accumulation within a memory device without exposing information related to internal error correction.

Disclosure of Invention

A Synchronous Dynamic Random Access Memory (SDRAM) device according to a first aspect of the present invention includes:

a memory array; and

an Error Checking and Correcting (ECC) circuit to perform an ECC operation on a plurality of rows of a memory array, the ECC circuit including a counter to accumulate an error count to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC circuit is to generate an error result as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result.

A system according to a second aspect of the invention having a memory device, comprises:

a memory controller; and

a plurality of Synchronous Dynamic Random Access Memory (SDRAM) devices coupled in parallel, wherein the SDRAM devices comprise:

a memory array; and

error Checking and Correcting (ECC) circuitry to perform ECC operations on a plurality of rows of the memory array, the ECC circuitry including a counter to accumulate error counts to be incremented in response to detecting an error in any of the plurality of rows, wherein the ECC circuitry is to generate an error result as a difference between the accumulated error counts and a non-zero error threshold to be reached before incrementing the error result;

wherein the SDRAM device provides internal error correction to data independent of error correction based on check bits provided by the memory controller.

A method for managing error correction information in a memory according to a third aspect of the present invention includes:

initiating an Error Check and Correction (ECC) operation on multiple rows of a memory array with ECC circuitry within a Synchronous Dynamic Random Access Memory (SDRAM) device;

accumulating an error count to be incremented in response to detecting an error in any of the plurality of rows; and

an error result is generated as a difference between the accumulated error count and a non-zero error threshold to be reached before incrementing the error result.

Drawings

The following description includes a discussion of figures having descriptions given by way of example of implementations of embodiments of the invention. The drawings should be understood by way of example and not by way of limitation. As used herein, references to one or more "embodiments" are to be understood as describing a particular feature, structure, and/or characteristic included in at least one implementation of the invention. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" appearing herein describe various embodiments and implementations of the invention, and do not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

FIG. 1 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller.

FIG. 2 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller.

FIG. 3 is a block diagram of an embodiment of a system in which a memory device generates an internal address for executing a received command.

FIG. 4 is a flow diagram of an embodiment of a process for managing internal ECC information, including generating internal addresses.

FIG. 5 is a block diagram of an embodiment of a computing system in which a memory device generating internal addresses can be implemented.

FIG. 6 is a block diagram of an embodiment of a mobile device in which a memory device generating internal addresses is enabled.

The following is a description of certain details and implementations, including a description of the accompanying drawings, which may depict some or all of the embodiments described below, as well as other potential embodiments or implementations, which discuss the inventive concepts presented herein.

Detailed Description

As described herein, the memory subsystem implements managing error correction information. The memory device internally performs error correction on a range of memory locations and increments an internal count for each error detected. The memory device includes ECC logic to generate an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device. The memory device is capable of providing error results to an associated host of the system so that only the accumulated number of errors is exposed, without exposing internal errors from before incorporation into the system. In one embodiment, the memory device is capable of generating an internal address to execute commands received from the memory controller. In one embodiment, the memory device is capable of resetting the counter after a first pass through the memory region in which errors are counted.

In one embodiment, the memory device generates an internal address to execute a command received from the memory controller. The memory device performs error correction to correct Single Bit Errors (SBEs) in the accessed data and generates an error count indicating a number of SBEs corrected that exceeds a baseline number of SBEs preset for the memory device. The memory device provides the error count to the memory controller so that only the number of SBEs accumulated after manufacture is exposed. In one embodiment, the memory device is capable of resetting the counter after a first pass through the memory region in which errors are counted.

References to memory devices can apply to different memory types and in particular to any memory having a bank architecture. Memory devices are generally referred to as volatile memory technologies. Volatile memory is memory whose state (and thus the data stored thereon) is indeterminate when power is interrupted to the device. A non-volatile memory refers to a memory whose state is determined even when power is interrupted to a device. Dynamic volatile memory requires that data stored in the device be refreshed to retain state. One example of dynamic volatile memory includes DRAM (dynamic random access memory) or some variant, such as synchronous DRAM (sdram). The memory subsystem as described herein may be compatible with a variety of memory technologies, such as DDR4 (DDR version 4, an initial specification published by JEDEC in 9 months 2012), LPDDR4 (low power double data transfer rate (LPDDR) version 4, JESD209-4, originally published by JEDEC in 8 months 2014), WIO2 (wide I/O2 (WideIO2), JESD229-2, originally published by JEDEC in 8 months 2014), HBM (high bandwidth memory DRAM, JESD235, originally published by JEDEC in 10 months 2013), DDR5 (DDR version 5, currently being discussed by JEDEC), HBM2 (HBM version 2, currently being discussed by JEDEC), and/or other and derivative or extended technologies based on such specifications.

The current design of DRAM devices for technologies such as WIO2 and LPDDR4 is to include additional bits internally to store error correction data (e.g., ECC (error correction code) information). For internal ECC, the DRAM internally detects and corrects Single Bit Errors (SBEs) using Single Error Correction (SEC), which utilizes 8 dedicated ECC bits per 128 data bits. The external data transfer size and the internal prefetch size are 128 bits in the case of both LPDDR4 and WIO 2. For internal ECC, however, these designs traditionally lack a way to track error accumulation in DRAM, which makes the device prone to accumulating errors until the number of errors overwhelms the ability of the on-die or internal ECC to correct SBE. If too many errors accumulate, the device may pass data with uncorrected errors to the memory controller, causing a failure.

If the DRAM does not perform internal error correction, the system may be able to perform system level error correction, but all errors within the DRAM will be visible. Exposing information about all errors exposes internal error information, which can reveal information that is proprietary to the memory device manufacturer and generally considered undesirable for sharing within the industry. As described herein, the system can provide a relative error count to indicate how many errors have been accumulated since the memory device was shipped or deployed in the system. Relative errors as described herein can indicate how many errors have been accumulated over a baseline number of errors. The baseline number of errors for a memory device is the number of errors detected during manufacturing testing. The accumulation of errors can be determined, for example, by counting the total number of errors compared to a reference number. It is noted, however, that even internal errors detected during manufacture can be proprietary information, and the device manufacturer can internally configure this number and configure the memory device to expose only the accumulated differences.

Typically, during normal operation, DDR4 DRAM devices implemented for internal ECC do not signal that a single bit error has been corrected. In one embodiment, the total number of single bit errors on the device is permanently stored in the memory device during manufacturing. For example, the number of errors can be stored in an error threshold register. The stored error threshold count represents the total number of single bit errors detected during manufacturing testing. In one embodiment, the error threshold register is not directly readable by a user and/or a host system. In one embodiment, the memory device includes an error counter that counts SBEs along with a comparator that compares the result of the error counter to an error threshold register.

In one embodiment, the memory device includes an address generator to generate an internal address for the received command. Thus, the memory device is able to control which locations of the memory device are to be accessed and when. The memory device can then internally manage error detection and count the number of errors relative to a baseline number of errors. Internally generating the address enables the memory device to internally reset the error accumulation counter and prevent the internal error count from continuing to increase. Without resetting the counter after the first pass through the memory space, the user can potentially run the error test twice (with the errors continuing to accumulate), and then simply divide the number of errors in half to expose information about internal errors and internal error corrections. By resetting the counter, each time the error test is run, the same number of errors will be revealed, even when running continuously.

In one embodiment, the error counter is cleared during reset. In one embodiment, the error counter is enabled by setting a mode register bit (e.g., MRx bit A [ y ]) and is initially cleared. Once enabled, the counter can be incremented for each read that detects a single bit error. A single pass through the array is allowed by only allowing the DRAM to generate addresses to read the array. Once the single pass through all memory locations is complete, in one embodiment, the control logic reads the relative error count result and resets the counter. In one embodiment, the relative error count can be stored in a multifunction register, which can then be read by a host (e.g., a memory controller). For example, the memory device can store the relative error count in a multi-function register (e.g., MPR3, page 3 register). In one embodiment, the register or other storage location includes a count representing a difference between a number of errors detected since the register was enabled and a stored error count. In one embodiment, in addition to reporting accumulated errors, the memory device is also capable of reporting addresses of one or more rows that contain the highest number of errors. In one embodiment, the memory device is able to report how many errors are contained in the row with the highest number of errors. In one embodiment, an on-die or DRAM internal counter can generate an internal address for a read error pass through a memory resource or memory device array. At the beginning of a read error pass through the array, the relative error count result register can be cleared. After one pass through the array, the relative count can be read out of the DRAM. In one embodiment, if the second pass is attempted, the error result register is cleared before the second pass begins.

FIG. 1 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller. System 100 includes elements of a memory subsystem in a computing device. Host 110 represents a host computing platform that runs an Operating System (OS) and applications. The OS and applications run operations that cause memory accesses. The host 110 includes a processor or processing unit, which can be a single-core or multi-core processor. The system 100 can be implemented as an SOC or with stand-alone components. When multiple memory devices 120 are included in system 100, each memory device can manage its internal ECC alone, either separate from the host or from other memory devices.

Memory controller 112 represents control logic that generates memory access commands in response to execution of operations by the processor(s). In one embodiment, system 100 includes multiple memory controllers. In one embodiment, system 100 includes one or more memory controllers per channel, where the channels are coupled to access multiple memory devices. Each channel is a separate access path to memory, so multiple different memory accesses can occur in parallel on different channels. In one embodiment, memory controller 112 is an integral part of host 110, such as logic implemented on the same die or package space as the host processor. Thus, the memory controller can be implemented as an integral part of the same die as the host processor, or coupled to the host processor in the system on a chip (SoC) configuration.

Memory device 120 represents a memory resource of system 100 and can be, for example, a DRAM device. Memory devices 120 each include a plurality of memory arrays 122. Memory array 122 represents the logic in which memory device 120 stores data bits. Memory device 120 includes I/O logic 126, which represents interconnect logic that enables the memory device to be coupled to memory controller 112. I/O logic 126 can include a command/address bus (commonly referred to as a C/A bus, a CMD/ADDR bus, or an ADD/CMD bus). I/O logic 126 can also include a data bus and other signal lines. I/O logic 126 can include signal lines, connectors, drivers, transceivers, termination control, and/or other logic to enable communication between a memory controller and a memory device.

In one embodiment, memory device 120 includes ECC 124, which represents logic and memory to implement internal error correction. Thus, ECC 124 represents the ability of memory device 120 to generate and use internal error correction bits. In one embodiment, ECC 124 is an integral part of an internal controller within memory device 120 (not specifically shown). Such internal controllers control the operation of the memory device, such as the receipt and processing of commands and the execution of commands, including controlling the timing of operations that execute commands and return data in response to requests from the memory controller (external to the memory device). In one embodiment, ECC 124 can be implemented in whole or in part as a circuit separate from the internal controller. In one embodiment, ECC 124 enables memory device 120 to perform reads of memory locations in a range of addresses and detect and correct SBEs, as well as increment an error count for each SBE corrected.

In one embodiment, memory controller 112 generates a command or request for an ECC count to determine accumulated errors from memory device 120. For clarity in the description, consider that ECC 124 processes such requests, and can generate a count in response to such requests. ECC 124 enables the memory to perform a series of operations to detect errors in response to error test commands received from the memory controller. For example, ECC 124 can include or have access to a counter that is incremented to track detected errors in read memory locations. As described herein, the memory device 120 is capable of generating a sequence of runs of memory locations through a memory space or a range of memory address locations to be tested for errors.

In one embodiment, ECC 124 determines the number of errors in the memory space and generates a count of corrected errors. In one embodiment, ECC 124 generates a relative error count by calculating the difference between the number of detected errors and a known number of errors preset for the memory device prior to deployment. For example, the preset error can be a threshold or baseline number generated during manufacturing testing to detect the number of errors present in the device at the time of manufacture. In one embodiment, ECC 124 includes or has access to comparator logic that is capable of calculating a difference based on a threshold.

In one embodiment, when ECC 124 receives a continuous command to perform an error test, it will determine when the entire memory space of the memory array has been tested and can reset the error count. Thus, each time an error check is performed, ECC 124 can restart the error count, and the difference between the generated count and a preset number indicating a threshold or baseline number of errors for the device will also restart each time. In one embodiment, ECC 124 is also capable of resetting the error count in response to a start condition when the memory subsystem is reset.

FIG. 2 is a block diagram of an embodiment of a system having a memory device capable of exposing internal error correction bits for use by an external memory controller. System 200 is one example of an embodiment of system 100 of fig. 1. System 200 illustrates address generation logic 240 within memory device 220 that generates addresses for internal operations in response to commands received from memory controller 210. Memory device 220 and memory controller 210 communicate via an I/O interface (not specifically shown) between the devices.

Address generation 240 can include an address counter that is used by an internal controller (not specifically shown) within memory device 220 to determine which address space to address an operation, e.g., read, to detect errors. Traditionally, the memory controller generates an address for ECC testing, and the memory device simply runs the command provided at the address indicated by the memory controller. However, by address generation 240 within memory device 220, the memory controller can simply generate a command or request for ECC testing and allow the memory device itself to generate addresses internally. Address generation 240 can include a mechanism (e.g., a counter) that tracks the address under test. Thus, the memory device itself is able to manage error correction testing.

Memory device 220 includes data storage 222, which represents storage space in memory device 220, where the memory device writes data received from memory controller 210 and accesses stored data for transmission to memory controller 210. In one embodiment, memory device 220 includes ECC logic 230. ECC logic 230 represents logic used by the memory device to calculate error correction. For example, ECC logic 230 can enable memory device 220 to detect and correct SBEs for data taken from memory locations within a range of addresses under test. ECC logic 230 can represent an application within the memory device that controls error correction from internal to memory device 220 to external to memory controller 210. ECC logic 230 can be implemented at least partially within the processor device, such as by an internal controller of memory device 220. In one embodiment, ECC logic 230 is implemented in whole or in part within a circuit separate from the internal controller.

In one embodiment, ECC control logic 230 includes or uses information stored in memory 220. More specifically, ECC control logic 230 is capable of using a threshold 232 that represents a baseline number of errors for memory device 220. In one embodiment, a BIOS (basic input/output System) or other logic can determine a baseline number of errors and write that number for permanent storage within a register or other storage location in memory device 220. By using threshold 232, ECC control logic 230 is able to generate an error output indicating the number of accumulated errors without exposing the baseline number. For example, the error output can indicate a number of SBEs corrected that exceeds a baseline number of SBEs preset for the memory device.

In one embodiment, ECC control logic 230 includes or uses counter 234, which is a counter that indicates how many errors are present (e.g., how many SBEs were detected and corrected) in data storage device 222. Counter 234 can be reset by ECC control logic 230 on each pass through the data storage space to determine how many errors are present. Thus, counter 234 is able to accumulate a count for each error detected, but will not continue to accumulate errors once the entire memory space has been checked. In one embodiment, checking the memory space again will cause ECC control logic 230 to determine that address generator 240 has reached the maximum address of the memory space, and thus will reset counter 234 in response to detecting that the counter has flipped. When the address generator 240 completes all addresses and returns to the starting address, the counter rolls over.

In one embodiment, ECC control logic 230 is capable of generating an error output that includes an indication of the row with the highest number of accumulated errors. Thus, in one embodiment, ECC control logic 230 accumulates errors on a per-row basis and identifies the row with the highest number of errors. For example, the counter 234 can include a plurality of counters. The counters 234 can include a counter for each row, all of which can be aggregated to get a total number of detected errors. Counters 234 can include a global counter that accumulates all errors for all rows and a row counter that is reset at the end of each row. This individual row count can be compared to the highest row count and if the count exceeds the current highest count, the new count can be stored in the storage location and the address of the row can also be stored. In one embodiment, if the count is the same as the highest count, the count will not be changed, but multiple row addresses will be stored. In providing error results to memory controller 210, ECC control logic 230 can report the total number of errors accumulated and an indication of the row with the highest error count. Reporting the row with the highest error count can include reporting the count of the row and the address of the row or rows with the highest count. In one embodiment, reporting the row with the highest error count includes reporting the row address instead of a count of the number of errors.

In one embodiment, memory device 220 includes a register 224, which represents one or more storage locations or registers where ECC control logic 230 is capable of storing error count and/or error report data. For example, ECC control logic 230 can record a total number of accumulated errors in register 224 that exceed a threshold of memory device 220. In one embodiment, registers 224 comprise mode registers or multi-function registers or other storage locations. In one embodiment, registers 224 can include or point to other storage locations that store row address information indicating one or more rows having the highest number of errors. In one embodiment, register 224 represents a storage device within memory device 220 accessible to memory controller 210 that enables memory controller 210 to access the reporting data. In one embodiment, memory device 220 sends reporting data to memory controller 210.

In one embodiment, memory controller 210 includes ECC 212, which represents ECC logic for use at a system level in system 200. It will be understood that ECC control logic 230 is logic within each memory device coupled to memory controller 210, with ECC 212 representing logic within memory controller 210 that performs ECC on data received from each memory device. By performing ECC operations on the data and then passing the data to the memory controller, the results of the operation of ECC control logic 230 can be transparent to memory controller 210. In one embodiment, ECC 212 is logic included within circuitry of memory controller 210. In one embodiment, ECC 212 is logic external to the memory controller circuitry that is accessible to the memory controller and capable of performing one or more operations related to ECC within system 200. For example, in one embodiment, ECC 212 can include ECC circuitry in a processor or SoC coupled to memory controller 210.

However, memory controller 210 can also provide an ECC for system 200 that is based not only on data from memory device 220, but also on data from multiple connected memory devices. Thus, not only can the error count from memory device 220 provide information about the useful life of the memory device itself as described herein, it can also operate as metadata for memory controller 210 for system-level ECC implementations. By knowing the corrected errors from the memory device level, the memory controller can adjust its error correction operation.

FIG. 3 is a block diagram of an embodiment of a system in which a memory device generates an internal address for executing a received command. System 300 is one embodiment of ECC control logic in accordance with system 100 and/or system 200. It will be understood that system 300 can be an integral part of the logic of the system and can include additional logic (not specifically shown). For example, system 300 can represent logic specifically for exposing errors that exceed a threshold, without specifically illustrating logic used to perform error detection or receive and process commands.

In one embodiment, the ECC control logic receives a command to initiate an ECC test. In one embodiment, the ECC control logic is an integral part of an on-die controller within the memory device. The controller controls the operation of the memory device, including generating internal commands and/or control signals to cause operations required to execute commands received by the memory device. The control logic can generate a reset at start signal and pass this signal to a row-column address generator 310 internal to the memory device. The start can be any time the device is powered up and initialized and any time the host computer system is configured to perform ECC testing to determine the number of accumulated errors. The reset signal at the beginning can be a binary (true/false) signal indicating whether or not to reset the counter.

In one embodiment, the on-die controller is capable of generating an increment signal. The increment signal can signal the increment of the operation to a subsequent operation. In one embodiment, the on-die controller provides the increment signal as an input to address generator 310. The address rollover detector 320 can determine when the incrementing of the counter causes the counter to restart at the initial address. The address rollover detector 320 can generate an output indicating a rollover. In one embodiment, the output is a binary (true/false) signal indicating a roll-over condition.

In one embodiment, address rollover detector 320 provides its output to XOR logic 330. In one embodiment, ECC control logic also provides a start-time reset signal as an input to XOR logic 330. XOR logic 330 is capable of performing an XOR ("exclusive or") operation on two input signals and outputting a binary output when either condition is true. In one embodiment, if either condition is true, system 300 resets error counter 340. Thus, the following conditions are considered as examples: wherein if the system is initialized, the counter is reset; or if the address of the internal address generator flips to start again at the initial address, the counter is reset.

In addition to the reset operation, the error counter 340 can receive as input an error detection signal. Error detection logic (not specifically shown) detects errors in the memory locations and is capable of generating a binary signal indicating the errors. In one embodiment, error counter 340 receives an error indication signal and increments an error count each time an error is detected. Thus, error counter 340 is able to accumulate errors, and system 300 is able to reset the error count upon conditions of reset at the beginning and address rollover.

Error threshold 350 represents a threshold or baseline number of errors expected for the memory devices in which system 300 is incorporated. Error threshold 350 can be set by manufacturing tests and does not change over the life of the memory device. Comparator 360 is capable of determining the difference between error threshold 350 and error counter 340. The count in error counter 340 that exceeds error threshold 350 is provided to result register 370. It will be appreciated that by storing only the difference between error threshold 350 and error counter 340, the system is able to report only accumulated errors without exposing information about internal errors. In one embodiment, result register 370 is available to the host system to read to determine the number of errors accumulated over the life of the memory device, not including the number of errors present at the time of manufacture of the device.

In one embodiment, system 300 includes storage for one or more rows that indicate the highest amount of data with an error in addition to or as part of result register 370. In one embodiment, system 300 stores address information for one or more rows and reports the addresses to an associated memory controller. In one embodiment, if a row is determined to have the highest number of errors or equal to the highest number of errors, address generator 310 records the address of the row.

FIG. 4 is a flow diagram of an embodiment of a process for managing internal ECC information, including generating internal addresses. Process 400 enables ECC logic internal to a memory device to manage internal ECC information that can be selectively exposed to an associated memory controller/host. The manufacturer manufactures the memory device 402 and performs manufacturing tests on the device 404. In one embodiment, testing includes testing that employs internal ECC to determine the number of errors present in a new device, and can be configured for internal error correction when the device is deployed or incorporated into a computing device. The manufacturer can store the number of errors as a threshold or baseline number for the memory device (408). The manufacturer can store the number in a register or other memory or storage location within the memory device. The memory device will use the threshold number as a basis for determining how many errors accumulate over the life of the memory device. It will be understood that each memory device can have a different threshold based on separate testing of the device.

In one embodiment, the threshold is applicable to the range of memory locations to be tested. In one embodiment, the range of memory locations is the entire available address space for the memory device. In one embodiment, the range of memory locations is a subset of the available address space for the memory device. In one embodiment, during operation when the memory device is incorporated into a system, the memory device receives an access command (410). In one embodiment, such commands can include commands to perform error testing on a range of address spaces (e.g., the entire memory address space or a subset of the memory address space). In one embodiment, in response to the command and/or in response to initiating the error detection test, the memory device resets an address counter that generates the internal address and resets the error count (412). By resetting the error count before starting the error detection test, the memory device can prevent double counting errors if the memory test is required to be performed multiple times.

In one embodiment, the memory device generates an internal address for an operation that is performed to execute the requested command(s) (414). In one embodiment, the memory device determines whether an internally generated address flip has occurred (416). In one embodiment, in response to the address flipping (yes branch of 416), the memory device can reset the error count (418). If an address roll-over has not occurred ("NO" branch of 416), the address has not been previously checked for errors during the current cycle of the error count. By internally generating addresses and detecting flips, the memory device can prevent counting the same error of a memory location twice and provide a more accurate count of errors. Thus, address rollover detection can occur each time the selected memory address space is tested.

In one embodiment, internal ECC logic within the memory device identifies and corrects SBEs in response to the requested command(s) (420). In one embodiment, the requested command is an error test command that triggers the memory device to pass through the identified range of memory locations in sequence or through all memory locations. In one embodiment, the error test command is controlled by the memory device, and the memory device reads memory locations within a range of memory locations. Upon reading the contents of the location, the memory device is able to perform ECC on the contents and SBE correction using known techniques.

In one embodiment, the detection of errors is tracked on a per-row basis to determine the row or rows within the memory device having the highest number of errors. This per-row error tracking can be achieved by using multiple counters to track total errors and per-row errors. In one embodiment, in addition to storing the total accumulated errors, the highest number of errors per row is also stored. For example, the highest number of errors can be stored, and then testing or subsequent rows can cause a comparison of the errors of the current row to the stored highest count. In one embodiment, address information for one or more rows detected as having the highest number of errors is also stored. If the error count of the current row is equal to the highest count, the address information of the current row can be stored. If the error count of the current row is higher than the highest stored count, the count can be overwritten and any address information can also be replaced by the address information of the current row. After passing through all rows in the range of addresses, the count should include the highest number of errors per row count, and can include address information for the row or rows to which the count applies.

The ECC logic can accumulate a total number of errors each time a test is performed. The number of errors may increase over the lifetime of the memory device as the device ages. In one embodiment, if the last address in the range to be tested has not been reached ("NO" branch of 422), the memory device can increment the address and repeat the test for another memory location. In one embodiment, if the last address in the range to be tested has been reached ("yes" branch of 422), the ECC logic compares the number of SBEs corrected or detected during operational testing to a stored threshold (424), which indicates the number of errors that existed since manufacture or before the memory device was incorporated into the system. The ECC logic can store a difference between the current detected error and a threshold number (426). The stored difference can be referred to as an error result, error count, or error report.

In one embodiment, the ECC logic of the memory device stores the error result in a register accessible to the host. For example, the memory device can store the error result to a mode register, a multifunction register, or other register or storage location, which can be accessed by a memory controller or comparable logic of the host. If there is a difference in the count, the memory device has formed more errors, and if the number of errors becomes too large, the host system can be notified. For example, the memory device can store the difference in a register or other memory location accessible to the host device. In one embodiment, the memory device can be configured to periodically provide the amount to the host. Although sharing information about accumulating errors over the lifetime of the memory device, because the memory device controls address generation and counters for error detection, it is able to reveal errors accumulated since manufacture without revealing the total error information. In one embodiment, the ECC logic of the memory device also reports address information for the row with the highest number of errors and/or a count of errors for the row with the highest number of errors.

In one embodiment, the memory device records that completion of the test of the range of memory locations has occurred, for example, when the cycle or transfer through all addresses within the range of memory locations has completed. In one embodiment, the system resets the count of detected errors at the beginning or initiation of the memory subsystem. In one embodiment, the count of errors to be reset is an internal count of errors that is compared to a threshold or baseline number of errors. In one embodiment, the count of errors is an error result that can be reset from a register or memory location storing the result.

FIG. 5 is a block diagram of an embodiment of a computing system in which a memory device generating internal addresses can be implemented. System 500 represents a computing device according to any embodiment described herein, and can be a laptop computer, desktop computer, server, game or entertainment control system, scanner, copier, printer, routing or switching device, or other electronic device. System 500 includes a processor 520 that provides processing, operational management, and execution of instructions for system 500. Processor 520 can include any type of microprocessor, Central Processing Unit (CPU), processing core, or other processing hardware to provide processing for system 500. Processor 520 controls the overall operation of system 500 and can be or include one or more programmable general or special purpose microprocessors, Digital Signal Processors (DSPs), programmable controllers, Application Specific Integrated Circuits (ASICs), Programmable Logic Devices (PLDs), and the like, or a combination of such devices.

Memory subsystem 530 represents the main memory of system 500 and provides temporary storage for code to be executed by processor 520 or data values to be used in executing routines. Memory subsystem 530 can include one or more memory devices, such as Read Only Memory (ROM), flash memory, one or more types of Random Access Memory (RAM) or other memory devices, or a combination of such devices. Memory subsystem 530 stores and hosts, among other things, an Operating System (OS)536 to provide a software platform for execution of instructions in system 500. Additionally, other instructions 538 are stored and executed from memory subsystem 530 to provide the logic and processing of system 500. OS 536 and instructions 538 are executed by processor 520. Memory subsystem 530 includes a memory device 532 where it stores data, instructions, programs, or other items. In one embodiment, memory subsystem includes memory controller 534, which is the memory controller that generates and issues commands to memory devices 532. It will be appreciated that memory controller 534 can be a physical part of processor 520.

Processor 520 and memory subsystem 530 are coupled to bus/bus system 510. Bus 510 is an abstraction that represents any one or more separate physical buses, communication lines/interfaces, and/or point-to-point connections, connected by appropriate bridges, adapters, and/or controllers. Thus, bus 510 can include, for example, one or more of a system bus, a Peripheral Component Interconnect (PCI) bus, an ultra-transport or Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (commonly referred to as a "firewire"). The buses of bus 510 can also correspond to interfaces in network interface 550.

The system 500 also includes one or more input/output (I/O) interfaces 540, a network interface 550, one or more internal mass storage devices 560, and a peripheral interface 570 coupled to the bus 510. I/O interface 540 can include one or more interface components through which a user interacts with system 500 (e.g., a video, audio, and/or alphanumeric interface). Network interface 550 provides system 500 with the ability to communicate with remote devices (e.g., servers, other computing devices) over one or more networks. Network interface 550 can include an ethernet adapter, wireless interconnect component, USB (universal serial bus), or other wired or wireless standard-based or proprietary interface.

The storage 560 can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical based disks or disks, or a combination. The storage 560 stores code or instructions and data 562 in a persistent state (i.e., values are retained despite power interruptions to the system 500). Storage 560 can be generally considered a "memory," but memory 530 is a running or operating memory to provide instructions to processor 520. Although storage 560 is non-volatile, memory 530 can include volatile memory (i.e., the value or state of the data is indeterminate if power is interrupted to system 500).

The peripheral interface 570 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that are correlatively connected to system 500. A coherent connection is one in which the system 500 provides a software and/or hardware platform on which operations run and with which a user interacts.

In one embodiment, memory subsystem 530 includes internal ECC logic 580, which represents logic to manage internal ECC for memory 532 in accordance with any of the embodiments described herein. In one embodiment, internal ECC 580 generates an address for one pass through the read to perform error testing. Internal ECC 580 can generate a relative count indicating how many errors have been accumulated since the device was manufactured. Thus, the number of errors can be exposed to show how many errors have been made since the manufacturing device. In one embodiment, internal ECC 580 can include logic to reset an internal counter (which provides error accumulation information).

FIG. 6 is a block diagram of an embodiment of a mobile device in which a memory device generating internal addresses is enabled. Device 600 represents a mobile computing device, such as a computing tablet, mobile phone or smartphone, wireless-enabled e-reader, wearable computing device, or other mobile device. It will be understood that some of the components are generally shown, but not all of the components of such an apparatus are shown in apparatus 600.

The apparatus 600 includes a processor 610 that performs the primary processing operations of the apparatus 600. Processor 610 can include one or more physical devices such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing components. The processing operations performed by the processor 610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. Processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting device 600 to another device. The processing operations can also include operations related to audio I/O and/or display I/O.

In one embodiment, device 600 includes an audio subsystem 620, which represents hardware (e.g., audio hardware and audio circuitry) and software (e.g., drivers, codecs) components associated with providing audio functionality to a computing device. The audio functions can include speaker and/or headphone outputs and microphone inputs. Means for such functions can be integrated into the apparatus 600 or connected to the apparatus 600. In one embodiment, a user interacts with the device 600 by providing audio commands, which are received and processed by the processor 610.

Display subsystem 630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide visual and/or tactile displays for user interaction with a computing device. Display subsystem 630 includes a display interface 632, which includes a specific screen or hardware device used to provide a display to a user. In one embodiment, display interface 632 includes logic separate from processor 610 to perform at least some processing associated with the display. In one embodiment, display subsystem 630 includes a touch screen device that provides both output and input to a user. In one embodiment, display subsystem 630 includes a High Definition (HD) display that provides output to a user. High definition can refer to displays having a pixel density of about 100 PPI (pixels per inch) or greater, and can include formats such as full HD (e.g., 1080p), retinal displays, 4K (ultra high definition or UHD), and the like.

I/O controller 640 represents hardware devices and software components associated with interaction with a user. I/O controller 640 is operable to manage hardware that is part of audio subsystem 620 and/or display subsystem 630. In addition, I/O controller 640 illustrates a connection point for additional devices connected to device 600 through which a user may interact with the system. For example, devices that can be attached to device 600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I/O device for use with a particular application, such as a card reader or other device.

As mentioned above, I/O controller 640 is capable of interacting with audio subsystem 620 and/or display subsystem 630. For example, input via a microphone or other audio device can provide input or commands for one or more applications or functions of device 600. In addition, audio output can be provided instead of or in addition to display output. In another example, if the display subsystem includes a touch screen, the display device also acts as an input device, which can be managed, at least in part, by I/O controller 640. Additional buttons or switches can also be present on device 600 to provide I/O functions managed by I/O controller 640.

In one embodiment, I/O controller 640 manages devices such as accelerometers, cameras, light or other environmental sensors, gyroscopes, Global Positioning Systems (GPS), or other hardware capable of being included in device 600. The input can be part of direct user interaction, as well as providing environmental input to the system to affect its operation (e.g., filtering for noise, adjusting the display for brightness detection, applying a flash to a camera device, or other features). In one embodiment, the apparatus 600 includes power management 650 that manages battery power usage, charging of the battery, and features related to power saving operations.

Memory subsystem 660 includes memory device(s) 662 for storing information in device 600. Memory subsystem 660 can include non-volatile (if the power state to the memory device is not interrupted from changing) and/or volatile (if the power state to the memory device is interrupted is indeterminate) memory devices. Memory 660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the operation of the applications and functions of system 600. In one embodiment, memory subsystem 660 includes a memory controller 664 (which can also be considered a component of the control of system 600, and can potentially be considered a component of processor 610). The memory controller 664 includes a scheduler that generates and issues commands to the memory devices 662.

Connectivity 670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable device 600 to communicate with external devices. The external devices may be stand-alone devices (e.g., other computing devices, wireless access points or base stations) as well as peripherals (e.g., headphones, printers, or other devices).

The connectivity 670 can include a number of different types of connectivity. In general terms, the apparatus 600 is illustrated with cellular connectivity 672 and wireless connectivity 674. Cellular connectivity 672 generally refers to cellular network connectivity provided by a wireless operator, for example, via GSM (global system for mobile communications) or changes or derivations, CDMA (code division multiple access) or changes or derivations, TDM (time division multiplexing) or changes or derivations, LTE (long term evolution-also referred to as "4G") or other cellular service standards. Wireless connectivity 674 refers to wireless connectivity that is not cellular, and can include personal area networks (e.g., bluetooth), local area networks (e.g., WiFi), and/or wide area networks (e.g., WiMax), or other wireless communications. Wireless communication refers to the transfer of data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication is conducted via a solid communication medium.

Peripheral connections 680 include hardware interfaces and connectors and software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the device 600 can be a peripheral device ("to" 682) to other computing devices as well as having a peripheral device ("from" 684) connected thereto. The device 600 typically has a "docking" connector for connecting to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on the device 600. Additionally, a docking connector can allow the device 600 to connect to certain peripherals that allow the device 600 to control content output, for example, to audiovisual or other systems.

In addition to proprietary docking connectors or other proprietary connection hardware, the device 600 is also capable of peripheral connection 680 via a generic or standards-based connector. Common types can include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), displayports including minidisplayport (mdp), High Definition Multimedia Interface (HDMI), firewire, or other types.

In one embodiment, memory subsystem 660 includes internal ECC logic 690, which refers to logic to manage internal ECC for memory 662 in accordance with any of the embodiments described herein. In one embodiment, internal ECC 690 generates an address for one pass through a read to perform error testing. Internal ECC 690 can generate a relative count indicating how many errors have been accumulated since the manufacturing device. Thus, the number of errors can be exposed to show how many errors have been made since the manufacturing device. In one embodiment, internal ECC 690 can include logic to reset an internal counter (which provides error accumulation information).

In one aspect, a method for managing error correction information in a memory includes: performing error detection within a range of memory locations within a memory device; incrementing an internal count for each error detected; generating an error result indicating a difference between the internal count and a baseline number of errors preset for the memory device, the preset based on a number of errors detected for the memory device prior to incorporation into the system; and providing the error result to an associated host of the system so as to expose only a number of errors accumulated after the memory device is incorporated into the system.

In one embodiment, performing error detection includes performing a series of operations to detect errors in response to an error test command received from a host. In one embodiment, performing error detection on the range of memory locations includes performing error detection on the entire memory device. In one embodiment, performing error detection further comprises generating an address within a range of memory locations in the memory device. In one embodiment, incrementing the internal count for each error detected further comprises incrementing the count for each Single Bit Error (SBE) detection and correction performed in the range of memory locations. In one embodiment, the baseline number of errors comprises a number of errors detected during manufacturing testing of the memory device. In one embodiment, providing the error result further includes storing the error result in a register for access by the host. In one embodiment, providing the error result further includes indicating the row with the highest number of errors. In one embodiment, indicating the row with the highest number of errors includes reporting the address of the row and the number of errors in the row. In one embodiment, further comprising resetting the internal count upon completion of the range of memory locations.

In one aspect, a memory device with internal error correction includes: error detection logic internal to the memory device to perform internal error detection on a range of memory locations; a counter for incrementing an internal count for each error detected; comparator logic to generate an error result indicative of a difference between the internal count and a baseline number of errors preset for the memory device, the preset based on a number of errors detected for the memory device prior to incorporation into the system; and a register to store the error report for access by the associated host without exposing the benchmark quantity.

In one embodiment, the error detection logic performing internal error detection is capable of performing a series of operations to detect errors in response to an error test command received from an associated host. In one embodiment, error detection logic that performs internal error detection of a range of memory locations is capable of performing error detection of the entire memory device. In one embodiment, error detection logic that performs internal error detection is capable of internally generating addresses within a memory device for a range of memory locations. In one embodiment, the counter that increments the internal error count comprises a counter that is capable of incrementing the internal count for each Single Bit Error (SBE) detection and correction performed in the range of memory locations. In one embodiment, the baseline number of errors comprises a number of errors detected during manufacturing testing of the memory device. In one embodiment, the counter is also capable of resetting the internal count upon completion of the range of memory locations. In one embodiment, error detection logic to identify the highest number of rows with errors and storage to store an indication of the highest number of rows with errors is also included. In one embodiment, the indication includes an address of the row and a number of errors in the row. In one embodiment, the storage device includes a register.

In one aspect, a system comprises: a memory controller coupled to the memory device, the memory controller capable of generating an error detection command for the coupled memory device; a memory device coupled to the memory controller, the memory device including input/output (I/O) logic to receive commands from the memory controller; ECC (error correction code) logic capable of performing ECC internally within the memory device to correct Single Bit Errors (SBEs) detected in data taken from a range of memory locations, to generate an error count indicating a number of SBEs corrected that exceeds a baseline number of SBEs preset for the memory device, and to provide the error count to the memory controller without exposing the baseline number.

Wherein the memory device is a system of memory devices in accordance with any embodiment of the aspects of the memory devices set forth above. In one aspect, an apparatus includes means for performing operations to execute a method for managing error correction information in accordance with any embodiment of an aspect of the method. In one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon that, when accessed, results in performance of operations to execute a method for managing error correction information in accordance with any embodiment of an aspect of the method.

In one aspect, a second method for managing error correction information in a memory includes: accessing data in the memory device in response to a read access request from an associated memory controller; performing internal error correction in the memory device to correct detected Single Bit Errors (SBE) in the fetched data; generating an error count indicating a number of SBEs corrected exceeding a reference number of SBEs preset for the memory device based on the manufacturing test; and providing the error count to the memory controller to expose only the number of SBEs accumulated after manufacture.

In one embodiment, the read access request is part of an error detection test routine generated by the memory controller. In one embodiment, performing internal error correction further comprises internally generating an address within the memory device for the fetch data. In one embodiment, providing the error count includes storing the error count in a register for access by the memory controller. In one embodiment, further comprising resetting the error count upon completion of the range of memory locations. In one embodiment, resetting the error count at the initiation of the memory device is also included. In one embodiment, further comprising: identifying a highest number of rows having SBEs; and providing an indication of the highest number of rows with SBEs. In one embodiment, the indication includes an address of the row and a number of errors in the row.

In one aspect, a memory device with internal error correction includes: logic internal to the memory device to fetch data in response to a read access request from an associated memory controller and to perform internal error correction to correct a detected Single Bit Error (SBE) in the fetched data; a counter to increment an error count indicating a number of SBEs corrected exceeding a reference number of SBEs preset for the memory device based on a manufacturing test; and logic to provide the error count to the memory controller to expose only the number of SBEs accumulated after manufacturing.

The second memory device further includes features for operating in accordance with any embodiment of the aspect of the second method. In one aspect, an apparatus includes means for performing operations to execute a method for managing error correction information in accordance with any embodiment of an aspect of the second method. In one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon that, when accessed, results in performance of operations to execute a method for managing error correction information in accordance with any embodiment of an aspect of the second method.

In one aspect, a third method for managing error correction information in a memory includes: receiving a command at a memory device from an associated memory controller; generating an address internally with the memory device to perform an operation to execute the command; performing internal error correction in the memory device to correct detected Single Bit Errors (SBE) in the fetched data; generating an error count indicating a number of SBEs corrected exceeding a reference number of SBEs preset for the memory device based on the manufacturing test; and providing the error count to the memory controller to expose only the number of SBEs accumulated after manufacture.

In one embodiment, performing error detection includes performing a series of operations to detect errors in response to an error test command received from a host. In one embodiment, performing error detection on the range of memory locations includes performing error detection on the entire memory device. In one embodiment, performing error detection further comprises generating an address within a range of memory locations in the memory device. In one embodiment, generating the error count includes incrementing the count for each Single Bit Error (SBE) detection and correction performed in the range of memory locations that exceeds a reference. In one embodiment, generating the error count further comprises incrementing the count for each SBE detection and correction performed, comparing the count to a baseline, and storing only the number of SBEs that exceed the baseline. In one embodiment, the baseline number of errors comprises a number of errors detected during manufacturing testing of the memory device. In one embodiment, providing the error count further comprises storing the error count in a register for access by the host. In one embodiment, further comprising resetting the error count upon completion of the range of memory locations. In one embodiment, further comprising: identifying a highest number of rows having SBEs; and providing an indication of the highest number of rows with SBEs. In one embodiment, the indication includes an address of the row and a number of errors in the row.

In one aspect, a memory device with internal error correction includes: logic internal to the memory device that receives commands from an associated memory controller, internally generates addresses with the memory device to perform operations to execute the commands, and performs internal error correction to correct Single Bit Errors (SBEs) detected in the fetched data; a counter to generate an error count indicating a number of SBEs corrected exceeding a reference number of SBEs preset for the memory device based on the manufacturing test; and logic to provide the error count to the memory controller to expose only the number of SBEs accumulated after manufacturing.

The third memory device further includes features for operation in accordance with any embodiment of the aspect of the third method. In one aspect, an apparatus includes means for performing operations to execute a method for managing error correction information in accordance with any embodiment of aspects of the third method. In one aspect, an article of manufacture includes a computer-readable storage medium having content stored thereon that, when accessed, results in performance of operations to execute a method for managing error correction information in accordance with any embodiment of an aspect of the third method.

The flow diagrams illustrated herein provide examples of sequences of various process actions. The flow diagrams can indicate operations to be performed by software or firmware routines and physical operations. In one embodiment, the flow diagram can illustrate the state of a Finite State Machine (FSM), which can be implemented in hardware and/or software. Although shown in a particular sequence or order, the order of the acts can be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples, and the processes can be performed in a different order, and some actions can be performed in parallel. Additionally, in various embodiments, one or more acts can be omitted; thus, not all acts may be required in every embodiment. Other process flows are possible.

To the extent various operations or functions are described herein, they can be described or defined as software code, instructions, configurations, and/or data. The content can be directly executable ("object" or "executable" form) source code or difference code ("delta" or "patch" code). The software content of the embodiments described herein can be provided via an article of manufacture having the content stored thereon or via a method of operating a communication interface to transmit data via the communication interface. A machine-readable storage medium enables a machine to perform the functions or operations described, and includes any mechanism for storing information in a form accessible by a machine (e.g., a computing device, an electronic system, etc.), such as recordable/non-recordable media (e.g., Read Only Memory (ROM), Random Access Memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism for interfacing with any of a hardwired, wireless, optical, etc. medium to communicate with another device, such as a memory bus interface, a processor bus interface, an internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and/or sending signals to prepare the communication interface to provide data signals describing the software content. The communication interface is accessible via one or more commands or signals sent to the communication interface.

The various components described herein can be means for performing the operations or functions described. Each component described herein includes software, hardware, or a combination of these. A component can be implemented as a software module, a hardware module, dedicated hardware (e.g., application specific hardware, Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), etc.), embedded controller, hardwired circuitry, or the like.

Various modifications of the disclosed embodiments and implementations of the invention, in addition to those described herein, can be made without departing from their scope. Accordingly, the description and examples herein should be construed as illustrative, and not restrictive. The scope of the invention should be measured solely by reference to the claims that follow.