阅读说明：本技术 半导体结构的形成方法 (Method for forming semiconductor structure ) 是由 张海洋 赵振阳 张恩宁 于 2020-05-18 设计创作，主要内容包括：一种半导体结构的形成方法,包括：提供衬底；在衬底上形成堆叠材料结构；在堆叠材料结构内形成若干凹槽,凹槽的底部位于所述第一材料层内,形成初始堆叠结构,初始堆叠结构包括初始第一层、位于初始第一层上的初始第二层以及位于初始第二层上的初始第三层；对初始第三层进行刻蚀,形成若干过渡第三层,若干过渡第三层沿平行于衬底表面的第二方向排列,第二方向与第一方向垂直；形成过渡第三层之后,去除初始堆叠结构在第二方向两侧的部分初始第一层和部分初始第二层,形成堆叠结构,堆叠结构包括第一层、位于第一层上的第二层以及位于第二层上的过渡第三层；形成栅极结构。所述方法形成的半导体结构性能较好。(A method of forming a semiconductor structure, comprising: providing a substrate; forming a stacked material structure on a substrate; forming a plurality of grooves in the stacked material structure, wherein the bottoms of the grooves are positioned in the first material layer to form an initial stacked structure, and the initial stacked structure comprises an initial first layer, an initial second layer positioned on the initial first layer and an initial third layer positioned on the initial second layer; etching the initial third layer to form a plurality of transitional third layers, wherein the transitional third layers are arranged along a second direction parallel to the surface of the substrate, and the second direction is vertical to the first direction; after the transitional third layer is formed, removing part of the initial first layer and part of the initial second layer on two sides of the initial stacking structure in the second direction to form a stacking structure, wherein the stacking structure comprises the first layer, the second layer located on the first layer and the transitional third layer located on the second layer; and forming a gate structure. The semiconductor structure formed by the method has better performance.)

1. A method of forming a semiconductor structure, comprising:

providing a substrate;

forming a stacked material structure on a substrate, the stacked material structure comprising a first material layer, a second material layer on the first material layer, and a third material layer on the second material layer;

forming a plurality of grooves in the stacked material structure, wherein the bottoms of the grooves are positioned in the first material layer, the grooves are arranged along a first direction parallel to the surface of the substrate to form an initial stacked structure, and the initial stacked structure comprises an initial first layer, an initial second layer positioned on the initial first layer and an initial third layer positioned on the initial second layer;

etching the initial third layer to form a plurality of transitional third layers, wherein the transitional third layers are arranged along a second direction parallel to the surface of the substrate, and the second direction is vertical to the first direction;

after forming the transitional third layer, removing a part of the initial first layer and a part of the initial second layer on two sides of the initial stacked structure in the second direction to form a stacked structure, wherein the stacked structure comprises the first layer, the second layer positioned on the first layer and the transitional third layer positioned on the second layer;

and forming a gate structure.

2. The method of forming a semiconductor structure of claim 1, wherein the first layer comprises a first portion having a first projection on the substrate and a second portion on the first portion having a second projection on the substrate, the first projection having an area larger than an area of the second projection, and the second projection being within the range of the first projection.

3. The method of forming a semiconductor structure of claim 1, wherein after forming the initial stack structure and before forming the transitional third layer, further comprising: and forming an isolation structure in the groove, wherein the isolation structure exposes the side wall surface of the initial third layer, and the top surface of the isolation structure is lower than or flush with the bottom plane of the initial third layer.

4. The method of forming a semiconductor structure of claim 3, wherein the method of forming the gate structure comprises: and forming a gate structure on the surface of the stacked structure exposed by the isolation structure.

5. The method of forming a semiconductor structure of claim 3, wherein the method of forming the transitional third layer comprises: forming a first liner layer on an isolation structure, the first liner layer being located at a top surface and a sidewall surface of the initial third layer; forming a second mask layer on the first liner layer, wherein the patterns of the second mask layer are arranged along a second direction; etching the initial third layer by taking the second mask layer as a mask until the surface of the initial second layer is exposed to form the transitional third layer; and after forming the transitional third layer, removing the second mask layer and the first liner layer.

6. The method of forming a semiconductor structure of claim 5, wherein the method of forming the isolation structure comprises: forming a layer of spacer material on the initial stacked structure; planarizing the isolation material layer until the top surface of the initial stacking structure is exposed to form an initial isolation layer; etching back the initial isolation layer until the initial third layer is completely exposed to form a transition isolation structure; and removing the transitional isolation structures on the side walls of the initial first layer and the initial second layer in the second direction to form the isolation structures.

7. The method of forming a semiconductor structure of claim 3, wherein the material of the isolation structure comprises a dielectric material comprising silicon oxide.

8. The method of forming a semiconductor structure of claim 1, wherein the gate structure comprises a gate dielectric layer on a surface of the second layer and a gate layer on the gate dielectric layer.

9. The method of forming a semiconductor structure of claim 8, further comprising: the interlayer dielectric layer is positioned between the second layer and the gate dielectric layer; and the work function layer is positioned between the gate dielectric layer and the gate electrode layer.

10. The method of forming a semiconductor structure of claim 1, further comprising, after forming the stacked structure: and thinning the third transitional layer along the vertical direction of the side wall.

11. The method of forming a semiconductor structure of claim 10, wherein thinning the transitional third layer comprises: carrying out oxidation treatment on the surface of the transitional third layer to form an oxide layer; and removing the oxide layer.

12. The method of forming a semiconductor structure of claim 1, wherein the method of forming the initial stack structure comprises: forming a first mask layer on the stacked material structure, wherein the patterns of the first mask layer are arranged along a first direction; and etching the third material layer, the second material layer and part of the first material layer by taking the first mask layer as a mask, and forming the initial stacking structure on the substrate.

13. The method of forming a semiconductor structure of claim 1, wherein removing portions of the initial first layer and the initial second layer of the initial stacked structure on both sides of the second direction comprises: forming a second liner layer on the initial second layer, the second liner layer being located at top and sidewall surfaces of the transitional third layer; forming a third mask layer on the second liner layer, wherein the third mask layer exposes the top surfaces of two sides of a part of the initial second layer in the second direction, and the third mask layer is in the range of the initial second layer; etching the second liner layer, the initial second layer and the initial first layer by taking the third mask layer as a mask to form the stack structure; and after the stack structure is formed, removing the second liner layer and the third mask layer.

14. The method of forming a semiconductor structure of claim 1, wherein the material of the first layer comprises a semiconductor material comprising silicon or silicon germanium; the material of the second layer comprises a semiconductor material comprising silicon or silicon germanium; the material of the transitional third layer comprises a semiconductor material comprising silicon or silicon germanium.

15. The method of forming a semiconductor structure of claim 1, wherein the first layer has first ions therein, the first ions comprising N-type ions or P-type ions; the second layer is provided with second ions, and the second ions comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or boron fluoride ions.

16. The method of forming a semiconductor structure of claim 15, wherein the first ions are of opposite ion type to the second ions.

17. The method of claim 1, wherein a plurality of said recesses extend through said initial stacked structure in a second direction parallel to a surface of a substrate, said second direction being perpendicular to said first direction.

18. The method of forming a semiconductor structure of claim 2, wherein the first portion has a thickness in a range of 10nm to 100 nm; the thickness of the second part ranges from 10nm to 100 nm; the thickness range of the second layer is 10 nm-100 nm.

19. The method of forming a semiconductor structure of claim 1, wherein a width of the recess in the first direction is in a range of 20nm to 100 nm.

20. The method of forming a semiconductor structure according to claim 1, wherein a dimension of the third layer in the first direction is 5nm to 50 nm; the third layer has a dimension in the second direction of 5nm to 50 nm.

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.

Background

In the semiconductor field, a Vertical field-effect transistor (VFET) is widely used.

Vertical transistors may provide a smaller layout area than previous transistor-based designs, increasing the packing density of the device. Vertical field effect transistors include a channel that is perpendicular to the substrate surface, rather than being disposed along the plane of the substrate surface, and thus the gate length is not defined by the lateral line width but by the vertical thickness of the layer, thus allowing the vertical transistor to greatly reduce the gate length while effectively improving the short channel effects associated with planar devices.

Vertical transistors have various structures, and a new method of forming a vertical transistor is now proposed.

Disclosure of Invention

The invention provides a method for forming a semiconductor structure, which is used for forming the semiconductor structure.

To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a stacked material structure on a substrate, the stacked material structure comprising a first material layer, a second material layer on the first material layer, and a third material layer on the second material layer; forming a plurality of grooves in the stacked material structure, wherein the bottoms of the grooves are positioned in the first material layer, the grooves are arranged along a first direction parallel to the surface of the substrate to form an initial stacked structure, and the initial stacked structure comprises an initial first layer, an initial second layer positioned on the initial first layer and an initial third layer positioned on the initial second layer; etching the initial third layer to form a plurality of transitional third layers, wherein the transitional third layers are arranged along a second direction parallel to the surface of the substrate, and the second direction is vertical to the first direction; after forming the transitional third layer, removing a part of the initial first layer and a part of the initial second layer on two sides of the initial stacked structure in the second direction to form a stacked structure, wherein the stacked structure comprises the first layer, the second layer positioned on the first layer and the transitional third layer positioned on the second layer; and forming a gate structure.

Optionally, the first layer includes a first portion and a second portion located on the first portion, the first portion has a first projection on the substrate, the second portion has a second projection on the substrate, an area of the first projection is larger than an area of the second projection, and the second projection is located within a range of the first projection.

Optionally, after forming the initial stacked structure and before forming the third transitional layer, the method further includes: and forming an isolation structure in the groove, wherein the isolation structure exposes the side wall surface of the initial third layer, and the top surface of the isolation structure is lower than or flush with the bottom plane of the initial third layer.

Optionally, the forming method of the gate structure includes: and forming a gate structure on the surface of the stacked structure exposed by the isolation structure.

Optionally, the forming method of the transition third layer includes: forming a first liner layer on an isolation structure, the first liner layer being located at a top surface and a sidewall surface of the initial third layer; forming a second mask layer on the first liner layer, wherein the patterns of the second mask layer are arranged along a second direction; etching the initial third layer by taking the second mask layer as a mask until the surface of the initial second layer is exposed to form the transitional third layer; and after forming the transitional third layer, removing the second mask layer and the first liner layer.

Optionally, the method for forming the isolation structure includes: forming a layer of spacer material on the initial stacked structure; planarizing the isolation material layer until the top surface of the initial stacking structure is exposed to form an initial isolation layer; etching back the initial isolation layer until the initial third layer is completely exposed to form a transition isolation structure; and removing the transitional isolation structures on the side walls of the initial first layer and the initial second layer in the second direction to form the isolation structures.

Optionally, the material of the isolation structure includes a dielectric material, and the dielectric material includes silicon oxide.

Optionally, the gate structure includes a gate dielectric layer located on the second layer surface and a gate layer located on the gate dielectric layer.

Optionally, the method further includes: the interlayer dielectric layer is positioned between the second layer and the gate dielectric layer; and the work function layer is positioned between the gate dielectric layer and the gate electrode layer.

Optionally, after forming the stacked structure, the method further includes: and thinning the third transitional layer along the vertical direction of the side wall.

Optionally, the method for thinning the transition third layer includes: carrying out oxidation treatment on the surface of the transitional third layer to form an oxide layer; and removing the oxide layer.

Optionally, the method for forming the initial stacked structure includes: forming a first mask layer on the stacked material structure, wherein the patterns of the first mask layer are arranged along a first direction; and etching the third material layer, the second material layer and part of the first material layer by taking the first mask layer as a mask, and forming the initial stacking structure on the substrate.

Optionally, the method for removing the initial first layer and the initial second layer on both sides of the initial stacked structure in the second direction includes: forming a second liner layer on the initial second layer, the second liner layer being located at top and sidewall surfaces of the transitional third layer; forming a third mask layer on the second liner layer, wherein the third mask layer exposes the top surfaces of two sides of a part of the initial second layer in the second direction, and the third mask layer is in the range of the initial second layer; etching the second liner layer, the initial second layer and the initial first layer by taking the third mask layer as a mask to form the stack structure; and after the stack structure is formed, removing the second liner layer and the third mask layer.

Optionally, the material of the first layer comprises a semiconductor material comprising silicon or silicon germanium; the material of the second layer comprises a semiconductor material comprising silicon or silicon germanium; the material of the transitional third layer comprises a semiconductor material comprising silicon or silicon germanium.

Optionally, the first layer has first ions therein, and the first ions include N-type ions or P-type ions; the second layer is provided with second ions, and the second ions comprise N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or boron fluoride ions.

Optionally, the ion type of the first ion is opposite to the ion type of the second ion.

Optionally, a plurality of the grooves penetrate through the initial stacked structure along a second direction parallel to the surface of the substrate, and the second direction is perpendicular to the first direction.

Optionally, the thickness of the first portion ranges from 10nm to 100 nm; the thickness of the second part ranges from 10nm to 100 nm; the thickness range of the second layer is 10 nm-100 nm.

Optionally, the width of the groove in the first direction ranges from 20nm to 100 nm.

Optionally, the size of the third layer in the first direction is 5nm to 50 nm; the third layer has a dimension in the second direction of 5nm to 50 nm.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

the technical scheme of the invention provides a method for forming a semiconductor structure, so as to form the semiconductor structure, wherein the semiconductor structure has stronger channel control capability and higher integration level, and can be applied to the advanced semiconductor technology.

Drawings

FIGS. 1 and 2 are schematic cross-sectional views of a semiconductor structure according to an embodiment;

fig. 3 to 16 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.

Detailed Description

As described in the background, a vertical transistor has a variety of structures, one of which is now being analyzed.

Fig. 1 and 2 are schematic cross-sectional views of a semiconductor structure according to an embodiment.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view along a section line BB 'of fig. 2, and fig. 2 is a schematic cross-sectional view along a section line AA' of fig. 1, including: a substrate 100; a stacked structure on a substrate 100, the stacked structure comprising a first layer 101, a second layer 102 on the first layer 101 and several third layers 103 on the second layer 102; the first layer 101 comprises a first portion (not shown) having a first projection on the substrate 100 and a second portion (not shown) on the first portion having a second projection on the substrate, the first projection having an area larger than the second projection and the second projection being within the first projection; the second layer 102 is located on a second portion of the first layer 101; a number of said third layers 103 are arranged along a first direction parallel to the surface of the substrate 100; a plurality of grooves (not shown) in the stacked structure, wherein the bottoms of the grooves are located in the first layer 101, the plurality of grooves are arranged along a second direction parallel to the surface of the substrate, the second direction is perpendicular to the first direction, and the plurality of grooves penetrate through the stacked structure along the first direction parallel to the surface of the substrate; an isolation structure 104 located in the recess, wherein the isolation structure 104 exposes the sidewall surface of the third layer 103, and the top surface of the isolation structure 104 is lower than or flush with the bottom plane of the third layer 103; and a gate structure 105 located on the surface of the stacked structure exposed by the isolation structure.

The semiconductor structure has stronger channel control capability and higher integration level, and can be applied to the advanced semiconductor technology.

The technical scheme of the invention provides a method for forming the semiconductor structure, so that the semiconductor structure is realized.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 16 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.

Referring to fig. 3, a substrate 200 is provided.

In this embodiment, the material of the substrate 200 is silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

Referring to fig. 4, a stacked material structure is formed on a substrate 200, and the stacked material structure includes a first material layer 201, a second material layer 202 on the first material layer 201, and a third material layer 203 on the second material layer 202.

The first material layer 201 provides a material layer for a first layer to be formed later, the second material layer 202 provides a material layer for a second layer to be formed later, and the third material layer 203 provides a material layer for a third layer to be formed later.

The material of the first material layer 201 comprises a semiconductor material comprising silicon or silicon germanium; the material of the second material layer 202 comprises a semiconductor material comprising silicon or silicon germanium; the material of the third material layer 203 includes a semiconductor material including silicon or silicon germanium.

The first material layer 201 has first ions therein, and the first ions include N-type ions or P-type ions; the second material layer 202 has second ions therein, the second ions including N-type ions or P-type ions; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or boron fluoride ions.

In this embodiment, the ion type of the first ion is opposite to the ion type of the second ion.

The ion type of the first ions is opposite to that of the second ions, so that in a subsequently formed semiconductor structure, the first layer and the second layer form a PN junction, and a circuit of the formed semiconductor structure can be conducted.

Referring to fig. 5 and 6, fig. 6 is a schematic cross-sectional structure of fig. 5 along a section line CC 'direction, fig. 5 is a schematic cross-sectional structure of fig. 6 along a section line DD' direction, a plurality of grooves 209 are formed in the stacked material structure, a bottom of the grooves 209 is located in the first material layer 201, the plurality of grooves 209 are arranged along a first direction X parallel to the substrate surface, and an initial stacked structure is formed, the initial stacked structure includes an initial first layer, an initial second layer 207 located on the initial first layer, and an initial third layer 208 located on the initial second layer 207.

A number of said grooves 209 extend through said initial stacked structure along a second direction Y parallel to the substrate surface, said second direction Y being perpendicular to said first direction X.

The width of the groove 209 in the first direction X ranges from 20nm to 100 nm.

The initial first layer comprises an initial first portion 205 and an initial second portion 206 located on the initial first portion 205, the initial first portion 205 having a first projection on the substrate 200, the initial second portion 206 having a second projection on the substrate 200, the area of the first projection being larger than the area of the second projection, and the second projection being located within the range of the first projection.

The forming method of the initial stacking structure comprises the following steps: forming a first mask layer 204 on the stacked material structure, wherein the patterns of the first mask layer 204 are arranged along a first direction X; and etching the third material layer 203, the second material layer 202 and a part of the first material layer 201 by taking the first mask layer 204 as a mask, and forming the initial stack structure on the substrate 200.

The material of the first mask layer 204 includes a dielectric material including one or a combination of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. The process of etching the third material layer 203, the second material layer 202 and the part of the first material layer 201 includes one or more of a dry etching process and a wet etching process.

In this embodiment, the material of the first mask layer 204 includes silicon nitride; the process of etching the third material layer 203, the second material layer 202 and part of the first material layer 201 includes a dry etching process.

The first mask layer 204 also protects the top surface of the initial third layer 208 that is formed.

The initial first portion 205 has a thickness in the range of 10nm to 100 nm.

The initial second portion 206 has a thickness in the range of 10nm to 100 nm.

Referring to fig. 7, fig. 7 is a schematic structural diagram based on fig. 6, wherein an isolation structure 210 is formed in the recess 209, the isolation structure 210 exposes a sidewall surface of the initial third layer 208, and a top surface of the isolation structure 210 is lower than or flush with a bottom plane of the initial third layer 208.

The isolation structures 210 serve to protect the initial first and second layers 207 such that the initial first and second layers 207 are not damaged during subsequent formation of the third layer.

The method for forming the isolation structure 210 includes: forming a layer of spacer material (not shown) on the initial stacked structure; planarizing the isolation material layer until the top surface of the initial stacked structure is exposed, forming an initial isolation layer (not shown); etching back the initial isolation layer until the initial third layer 208 is completely exposed, forming a transitional isolation structure (not shown); and removing the transitional isolation structures on the sidewalls of the initial first layer and the initial second layer 207 in the second direction Y to form the isolation structure 210.

The material of the isolation structure 210 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In the present embodiment, the material of the isolation structure 210 includes silicon oxide.

Next, the initial third layer 208 is etched, and a plurality of transitional third layers 213 are formed on the initial second layer 207, wherein the plurality of transitional third layers 213 are arranged along a second direction Y parallel to the surface of the substrate 200, and the second direction Y is perpendicular to the first direction X. Please refer to fig. 8 to fig. 10 for the formation process of the transition third layer 213.

Referring to fig. 8 and 9, fig. 9 is a schematic cross-sectional view taken along a sectional line EE 'of fig. 8, fig. 8 is a schematic cross-sectional view taken along a sectional line FF' of fig. 9, a first liner layer 211 is formed on an isolation structure 210, the first liner layer 211 is located on a top surface and a sidewall surface of the initial third layer 208; a second mask layer 212 is formed on the first liner layer 211, and the pattern of the second mask layer 212 is arranged along the second direction Y.

The first liner layer 211 provides structural support for the second mask layer 212.

The material of the first liner layer 211 includes an organic material including amorphous carbon or an inorganic material including amorphous silicon.

In this embodiment, the material of the first liner layer 211 includes amorphous carbon; the material of the second mask layer 212 includes photoresist.

Referring to fig. 10, fig. 10 is a schematic structural diagram based on fig. 8, in which the initial third layer 208 is etched using the second mask layer 212 as a mask until the surface of the initial second layer 207 is exposed, so as to form the transitional third layer 213.

The process of etching the initial third layer 208 includes one or a combination of dry and wet etching processes.

In this embodiment, the process of etching the initial third layer 208 includes a dry etching process, and the dry etching process can form the transitional third layer 213 with a good sidewall profile.

With continued reference to fig. 10, after forming the third transitional layer 213, the second mask layer 212 and the first liner layer 211 are removed.

In this embodiment, the process of removing the second mask layer 212 includes an ashing process; the process of removing the first liner layer 211 includes a dry etching process.

After forming the transitional third layer 213, a portion of the initial first layer and a portion of the initial second layer 207 of the initial stacked structure on both sides in the second direction Y are removed to form a stacked structure including the first layer, the second layer 307 on the first layer, and the transitional third layer 213 on the second layer 307. Please refer to fig. 11 to 14 for a process of forming the stacked structure.

Referring to fig. 11 and 12, fig. 12 is a schematic cross-sectional view taken along a section line GG 'of fig. 11, and fig. 11 is a schematic cross-sectional view taken along a section line HH' of fig. 12, wherein a second liner layer 214 is formed on the initial second layer 207 and on the isolation structure 210, and the second liner layer 214 is located on a top surface and a sidewall surface of the transition third layer 213; a third mask layer 215 is formed on the second liner layer 214, wherein the third mask layer 215 exposes a portion of the top surface of the initial second layer 207 on both sides in the second direction Y, and the third mask layer 215 is within the range of the initial second layer 207.

The second liner layer 214 provides structural support for the third mask layer 215.

The material of the second liner layer 214 includes an organic material including amorphous carbon or an inorganic material including amorphous silicon.

In this embodiment, the material of the second liner layer 214 includes amorphous carbon; the material of the third mask layer 215 includes photoresist.

Referring to fig. 13 and 14, fig. 14 is a schematic cross-sectional structure of fig. 13 along a section line II ', fig. 13 is a schematic cross-sectional structure of fig. 14 along a section line JJ', the third mask layer 215 is used as a mask to etch the second liner layer 214, the initial second layer 207 and the initial first layer, so that the initial second layer 207 forms a second layer 307, the initial first portion 205 forms a first portion 305, the initial second portion 206 forms a second portion 306, and the stacked structure is formed, wherein the stacked structure includes the first layer, the second layer 307 on the first layer, and the transitional third layer 213 on the second layer 307.

The first layer comprises a first portion 305 and a second portion 306 located on the first portion 305.

The first layer comprises a first portion 305 and a second portion 306 located on the first portion 305, the first portion 305 having a first projection on the substrate 200, the second portion 306 having a second projection on the substrate 200, the area of the first projection being larger than the area of the second projection, and the second projection being located within the range of the first projection.

The area of the first projection is larger than that of the second projection, and the second projection is located within the range of the first projection, so that when a conductive structure electrically connected with the first layer is formed subsequently, the conductive structure is easily connected with the second portion 306, and the forming process of the conductive structure is simple.

In this embodiment, the thickness of the second layer 307 is in the range of 10nm to 100 nm.

After the stacked structure is formed, the second liner layer 214 and the third mask layer 215 are removed.

In the embodiment, the process of removing the third mask layer 215 includes an ashing process; the process of removing the second liner layer 214 includes a dry etching process.

With continuing reference to fig. 13 and 14, after forming the stacked structure, the method further includes: the transitional third layer 213 is thinned in the sidewall vertical direction to form a third layer 313.

The method of thinning the transitional third layer 213 comprises: performing oxidation treatment on the surface of the transition third layer 213 to form an oxide layer (not shown); and removing the oxide layer.

The process for removing the oxide layer comprises one or more of a dry etching process and a wet etching process.

By thinning the transition third layer 213, the size of the transition third layer 213 can be further reduced, so that the limitation of lithography technology can be overcome, and the size of the transition third layer 213 cannot be reduced when the transition third layer 213 is formed.

In the present embodiment, the size of the third layer 313 ranges from 5nm to 50nm in the first direction X. The third layer 313 has a size ranging from 5nm to 50nm in the second direction Y.

In other embodiments, the transitional third layer can be omitted from thinning.

Referring to fig. 15 and 16, fig. 16 is a schematic cross-sectional view taken along a section line KK 'in fig. 15, and fig. 15 is a schematic cross-sectional view taken along a section line LL' in fig. 16, wherein a gate structure 310 is formed on a surface of the second layer 307.

The forming method of the gate structure 310 includes: the gate structure 310 is formed on the surface of the stacked structure exposed by the isolation structure 210.

The gate structure 310 includes a gate dielectric layer (not shown) on the surface of the second layer 307 and a gate layer (not shown) on the gate dielectric layer.

In this embodiment, the method further includes: an interlayer dielectric layer (not shown) between the second layer and the gate dielectric layer; a work function layer (not shown) between the gate dielectric layer and the gate electrode layer.

The gate dielectric layer comprises a high dielectric constant material, the dielectric constant of the high dielectric constant material is greater than 3.9, and the high dielectric constant material comprises aluminum oxide or hafnium oxide; the material of the gate layer comprises a metal, and the metal comprises tungsten; the material of the work function layer comprises an N-type work function material or a P-type work function material, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride; the material of the interlayer dielectric layer comprises a low dielectric constant material, the dielectric constant of the low dielectric constant material is less than or equal to 3.9, and the low dielectric constant material comprises silicon oxide.

The semiconductor structure formed by the method has stronger channel control capability and higher integration level, and can be applied to the advanced semiconductor technology.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.