Drive circuit and DCDC boost system

文档序号：1877976 发布日期：2021-11-23 浏览：2次中文

阅读说明：本技术 驱动电路及dcdc升压系统 (Drive circuit and DCDC boost system ) 是由霍晓强金楠何云于 2021-10-26 设计创作，主要内容包括：本发明提供一种驱动电路及DCDC升压系统,包括：电源模块,将DCDC升压电路的输入电压及输出电压进行比较,并将较大的作为工作电压；振荡信号产生模块,连接输入电压及工作电压,用于产生振荡信号,并基于电感电流的大小调整振荡信号的频率；电荷泵模块,连接于振荡信号产生模块的输出端,基于振荡信号对工作电压进行升压；驱动模块,连接于振荡信号产生模块及电荷泵模块的输出端,当输出电压低于设定输出电压时为NMOS、PMOS功率管提供驱动信号。本发明在输入电压较低的情况下,能完全开启NMOS功率管,加快升压速度,解决带载无法升压的问题；同时,当输出电压达到设定输出电压后,本发明的驱动电路停止工作,不参与后续的环路控制。(The invention provides a drive circuit and a DCDC boosting system, comprising: the power supply module compares the input voltage and the output voltage of the DCDC booster circuit and takes the larger voltage as the working voltage; the oscillation signal generating module is connected with the input voltage and the working voltage, and is used for generating an oscillation signal and adjusting the frequency of the oscillation signal based on the magnitude of the inductive current; the charge pump module is connected to the output end of the oscillation signal generation module and used for boosting the working voltage based on the oscillation signal; and the driving module is connected with the output ends of the oscillation signal generating module and the charge pump module and provides driving signals for the NMOS and PMOS power tubes when the output voltage is lower than the set output voltage. Under the condition of lower input voltage, the NMOS power tube can be completely started, the boosting speed is accelerated, and the problem that the voltage cannot be boosted under load is solved; meanwhile, when the output voltage reaches the set output voltage, the driving circuit stops working and does not participate in subsequent loop control.)

1. A driver circuit for driving a DCDC boost circuit, the driver circuit comprising at least:

the power supply module compares the input voltage and the output voltage of the DCDC booster circuit and takes the larger of the input voltage and the output voltage as the working voltage of the driving circuit;

the oscillation signal generation module is connected with the input voltage and the working voltage, and is used for generating an oscillation signal and adjusting the frequency of the oscillation signal based on the magnitude of the inductive current in the DCDC booster circuit;

the charge pump module is connected to the output end of the oscillation signal generation module and used for boosting the working voltage based on the oscillation signal output by the oscillation signal generation module;

and the driving module is connected with the output ends of the oscillation signal generating module and the charge pump module and provides driving signals for an NMOS power tube and a PMOS power tube in the DCDC booster circuit when the output voltage is lower than a set output voltage.

2. The drive circuit according to claim 1, wherein: the oscillation signal generation module comprises a first charging unit, a second charging unit, a first discharging unit, a second discharging unit, a first capacitor, a second capacitor and a logic unit;

the first charging unit is connected with the upper electrode plates of the first capacitor and the second capacitor and provides a first charging current related to the input voltage;

the second charging unit is connected with the upper electrode plates of the first capacitor and the second capacitor and provides a second charging current related to the working voltage;

the first discharging unit is connected with the upper pole plates of the first capacitor and the second capacitor, and when the inductive current in the DCDC booster circuit is larger than a first preset value, the first discharging unit discharges the first capacitor and the second capacitor;

the second discharging unit is connected with the upper pole plates of the first capacitor and the second capacitor, and when the inductive current is smaller than the first preset value, the first capacitor and the second capacitor are discharged through the second discharging unit;

the logic unit is connected with the upper pole plates of the first capacitor and the second capacitor, generates a first oscillation signal based on the voltages of the first capacitor and the second capacitor, and outputs a second oscillation signal in phase opposition to the first oscillation signal, a third oscillation signal in phase with the oscillation signal and a delay signal of the second oscillation signal when an enable signal of the oscillation signal generation module is effective;

the lower pole plate of the first capacitor is grounded, and the lower pole plate of the second capacitor is connected with the first oscillating signal; a discharge current in the first discharge cell is less than a discharge current in the second discharge cell.

3. The drive circuit according to claim 2, wherein: the first charging unit comprises a first PMOS tube, a first resistor, a first NMOS tube, an NMOS current mirror, a PMOS current mirror and a second PMOS tube; the source electrode of the first PMOS tube is connected with the input voltage, the grid electrode of the first PMOS tube receives a first enabling signal, and the drain electrode of the first PMOS tube is connected with the input end of the NMOS current mirror through the first resistor; the drain electrode of the first NMOS tube is connected with the input end of the NMOS current mirror, the grid electrode of the first NMOS tube receives the first enabling signal, and the source electrode of the first NMOS tube is grounded; the input end of the PMOS current mirror is connected with the output end of the NMOS current mirror, and the power supply end is connected with the input voltage; the source electrode of the second PMOS tube is connected with the output end of the PMOS current mirror, the grid electrode of the second PMOS tube is connected with the first oscillation signal, and the drain electrode of the second PMOS tube is connected with the upper polar plates of the first capacitor and the second capacitor; the first enable signal controls the first charging unit to provide the first charging current when the oscillation signal generation module works normally and the first oscillation signal is at a low level.

4. The drive circuit according to claim 2, wherein: the second charging unit comprises a third PMOS tube and a second resistor; the source electrode of the third PMOS tube is connected with the working voltage, the grid electrode of the third PMOS tube receives a second enabling signal, and the drain electrode of the third PMOS tube is connected with the upper pole plates of the first capacitor and the second capacitor through the second resistor; the second enable signal controls the second charging unit to provide the second charging current when the oscillation signal generation module works normally and the first oscillation signal is at a low level.

5. The drive circuit according to claim 2, wherein: the first discharge unit comprises a second NMOS tube and a third resistor; the source electrode of the second NMOS tube is grounded, the grid electrode of the second NMOS tube is connected with the first oscillation signal, and the drain electrode of the second NMOS tube is connected with the upper pole plates of the first capacitor and the second capacitor through the third resistor.

6. The drive circuit according to claim 2, wherein: the second discharge unit comprises a fourth resistor, a fifth resistor, a sixth resistor, a third NMOS tube, a fourth NMOS tube and a fifth NMOS tube; one end of the fourth resistor is connected with the working voltage, and the other end of the fourth resistor is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with a drain electrode voltage detection signal of the NMOS power tube, and the source electrode is grounded; one end of the fifth resistor is connected with the grid electrode of the third NMOS tube, and the other end of the fifth resistor is grounded; the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the first oscillation signal, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube; and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode is connected with the upper pole plates of the first capacitor and the second capacitor through the sixth resistor.

7. The drive circuit according to any one of claims 2 to 6, wherein: the oscillation signal generation module further comprises a first control unit; the first control unit receives a driving signal of an NMOS power tube and the first oscillation signal, and the output end of the first control unit is connected with the input end of the logic unit; when the inductive current is larger than a second preset value, the logic unit adjusts the first oscillating signal to further control the NMOS power tube to be turned off.

8. The drive circuit according to claim 7, wherein: the first control unit comprises a sixth NMOS transistor, a seventh resistor, a first Schmitt trigger, a first phase inverter, a second phase inverter, an eighth resistor, a third capacitor, a seventh NMOS transistor and a first OR logic gate; the source electrode of the sixth NMOS tube is grounded, the grid electrode of the sixth NMOS tube is connected with the driving signal of the NMOS power tube, and the drain electrode of the sixth NMOS tube is connected with the working voltage through the seventh resistor; the input end of the first Schmitt trigger is connected with the drain electrode of the sixth NMOS tube; the first inverter and the second inverter are sequentially connected in series with the output end of the first Schmitt trigger; one end of the eighth resistor is connected with the output end of the second inverter, and the other end of the eighth resistor is connected with the upper polar plate of the third capacitor; the lower polar plate of the third capacitor is grounded; the source electrode of the seventh NMOS tube is grounded, the grid electrode of the seventh NMOS tube is connected with the output end of the first phase inverter, and the drain electrode of the seventh NMOS tube is connected with the upper polar plate of the third capacitor; and a first input end of the first OR logic gate is connected with an upper polar plate of the third capacitor, a second input end of the first OR logic gate is connected with the first oscillation signal, and an output end of the first OR logic gate is connected with the logic unit.

9. The drive circuit according to any one of claims 2 to 6, wherein: the oscillation signal generation module further comprises a second control unit; the second control unit receives the drain voltage of the NMOS power tube, and the output end of the second control unit is connected with the input end of the logic unit; when the drain voltage of the NMOS power tube is smaller than the working voltage, the logic unit is used for adjusting the first oscillation signal so as to control the PMOS power tube to be switched off.

10. The drive circuit according to claim 9, wherein: the second control unit comprises a comparator, a fourth capacitor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor and a ninth resistor; the comparator compares the drain voltage of the NMOS power tube with the working voltage and outputs a comparison result; the source electrode of the eighth NMOS tube is grounded, the grid electrode of the eighth NMOS tube is connected with the normal working signal of the oscillation signal generation module, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube; the grid electrode of the ninth NMOS tube is connected with the output end of the comparator, and the drain electrode of the ninth NMOS tube is connected with the working voltage and the logic unit through the ninth resistor; an upper polar plate of the fourth capacitor is connected with the output end of the comparator, and a lower polar plate of the fourth capacitor is connected with a source electrode of the ninth NMOS tube; and the source electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube, the grid electrode of the tenth NMOS tube is connected with a driving signal of the NMOS power tube, and the drain electrode of the tenth NMOS tube is connected with the output end of the comparator.

11. The drive circuit according to any one of claims 2 to 6, wherein: the drive circuit further comprises an NMOS power tube drain voltage detection module, wherein the NMOS power tube drain voltage detection module comprises an eighth PMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a third phase inverter, a third OR logic gate, a tenth resistor and a ninth PMOS tube; the source electrode of the eighth PMOS tube is connected with the working voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifteenth NMOS tube; the source electrode of the fifteenth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube; the source electrode of the sixteenth NMOS tube is grounded; the grid electrodes of the eighth PMOS tube, the fifteenth NMOS tube and the sixteenth NMOS tube are connected with the driving signal of a PMOS power tube; the input end of the third inverter is connected with the drain electrode of the eighth PMOS tube; the input end of the third OR logic gate is connected with the output end of the third inverter and the switching signal; one end of the tenth resistor is connected with the drain electrode of the NMOS power tube, and the other end of the tenth resistor is connected with the source electrode of the ninth PMOS tube; the grid electrode of the ninth PMOS tube is connected with the output end of the third OR logic gate, and the drain electrode of the ninth PMOS tube outputs an NMOS power tube drain electrode voltage detection signal; wherein the switching signal is active when the output voltage is lower than a set output voltage.

12. The drive circuit according to claim 2, wherein: the driving module comprises a first driving unit and a second driving unit;

the first driving unit receives an output signal of the charge pump module, and generates a first driving signal with the same frequency as the delay signal of the second oscillation signal when the output voltage is lower than a set output voltage, wherein the high level of the first driving signal is equal to the level of the output signal of the charge pump module; when the output voltage is higher than the set output voltage, the first driving signal is in a high-impedance state; the first driving signal is used for driving the NMOS power tube;

the second driving unit receives the working voltage, and generates a second driving signal with the same frequency as the second oscillating signal when the output voltage is lower than a set output voltage, wherein the high level of the second driving signal is equal to the level of the working voltage; when the output voltage is higher than the set output voltage, the second driving signal is in a high-impedance state; the second driving signal is used for driving the PMOS power tube.

13. The drive circuit according to claim 12, wherein: the first driving unit comprises a fourth PMOS tube, a fifth PMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a first NOR gate and a second NOR gate; the source electrode of the fourth PMOS tube is connected with the output end of the charge pump module, the grid electrode of the fourth PMOS tube receives a switching signal, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the inverse signal of the enable signal of the driving circuit, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the eleventh NMOS tube and outputs the first driving signal; the grid electrode of the eleventh NMOS tube receives the delay signal of the second oscillation signal, and the source electrode of the eleventh NMOS tube is grounded; the input end of the first NOR logic gate is connected with the switching signal and an inverted signal of an enabling signal of the driving circuit; the input end of the second NOR logic gate is connected with the output end of the first NOR logic gate and the delay signal of the second oscillation signal; the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, the grid electrode of the twelfth NMOS tube is connected with the output end of the second NOR logic gate, and the source electrode of the twelfth NMOS tube is grounded; when the output voltage is lower than the set output voltage, the switching signal is effective, and the first driving unit is controlled to work.

14. The drive circuit according to claim 12, wherein: the second driving unit comprises a sixth PMOS tube, a seventh PMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a third NOR gate and a second OR gate; the source electrode of the sixth PMOS tube is connected with the working voltage, the grid electrode of the sixth PMOS tube is connected with the enabling signal of the driving circuit, and the drain electrode of the sixth PMOS tube outputs the driving signal of the PMOS power tube; the input end of the third NOR logic gate is connected with the inverse signal of the second oscillating signal and the switching signal; the input end of the second OR logic gate is connected with the output end of the third NOR logic gate and the enable signal of the driving circuit; the source electrode of the seventh PMOS tube is connected with the working voltage, the grid electrode of the seventh PMOS tube is connected with the output end of the second OR logic gate, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube; the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the thirteenth NMOS tube is connected with the output end of the second OR logic gate, and the source electrode of the thirteenth NMOS tube is connected with the drain electrode of the fourteenth NMOS tube; the grid electrode of the fourteenth NMOS tube is connected with a high-level enabling signal of the oscillation signal generating module, and the source electrode of the fourteenth NMOS tube is grounded.

15. A DCDC boost system, characterized in that it comprises at least:

a DCDC boost circuit, a PWM loop control circuit and a drive circuit according to any one of claims 1 to 14;

the DCDC booster circuit comprises an NMOS power tube and a PMOS power tube; when the output voltage of the DCDC booster circuit is lower than a set output voltage, the driving circuit provides driving signals for the NMOS power tube and the PMOS power tube; when the output voltage of the DCDC booster circuit is higher than the set output voltage, the PWM loop control circuit provides driving signals for the NMOS power tube and the PMOS power tube.

Technical Field

The invention relates to the field of power management, in particular to a driving circuit and a DCDC boosting system.

Background

Some portable electronic devices currently use a power management chip such as a DCDC converter. The battery energy of the portable device is limited, and the service life of the battery is prolonged, which is particularly important for the DCDC boost switching power supply. In the existing DCDC boost chip, there are often problems that the NMOS power transistor cannot be completely turned on when the input voltage is very low, the boost speed is slow, or the boost cannot be realized with load, and how to solve these problems becomes one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present invention is to provide a driving circuit and a DCDC boost system, which are used to solve the problems that the NMOS power transistor cannot be completely turned on, the boost speed is slow, and the boost cannot be realized with load when the input voltage of the DCDC boost chip in the prior art is very low.

To achieve the above and other related objects, the present invention provides a driving circuit for driving a DCDC boost circuit, the driving circuit comprising at least:

and the driving module is connected with the output ends of the oscillation signal generation module and the charge pump module and provides driving signals for the NMOS power tube and the PMOS power tube when the output voltage is lower than a set output voltage.

Optionally, the oscillation signal generating module includes a first charging unit, a second charging unit, a first discharging unit, a second discharging unit, a first capacitor, a second capacitor, and a logic unit;

the first charging unit is connected with the upper electrode plates of the first capacitor and the second capacitor and provides a first charging current related to the input voltage;

the second charging unit is connected with the upper electrode plates of the first capacitor and the second capacitor and provides a second charging current related to the working voltage;

More optionally, the first charging unit includes a first PMOS transistor, a first resistor, a first NMOS transistor, an NMOS current mirror, a PMOS current mirror, and a second PMOS transistor; the source electrode of the first PMOS tube is connected with the input voltage, the grid electrode of the first PMOS tube receives a first enabling signal, and the drain electrode of the first PMOS tube is connected with the input end of the NMOS current mirror through the first resistor; the drain electrode of the first NMOS tube is connected with the input end of the NMOS current mirror, the grid electrode of the first NMOS tube receives the first enabling signal, and the source electrode of the first NMOS tube is grounded; the input end of the PMOS current mirror is connected with the output end of the NMOS current mirror, and the power supply end is connected with the input voltage; the source electrode of the second PMOS tube is connected with the output end of the PMOS current mirror, the grid electrode of the second PMOS tube is connected with the first oscillation signal, and the drain electrode of the second PMOS tube is connected with the upper polar plates of the first capacitor and the second capacitor; the first enable signal controls the first charging unit to provide the first charging current when the oscillation signal generation module works normally and the first oscillation signal is at a low level.

More optionally, the second charging unit includes a third PMOS transistor and a second resistor; the source electrode of the third PMOS tube is connected with the working voltage, the grid electrode of the third PMOS tube receives a second enabling signal, and the drain electrode of the third PMOS tube is connected with the upper pole plates of the first capacitor and the second capacitor through the second resistor; the second enable signal controls the second charging unit to provide the second charging current when the oscillation signal generation module works normally and the first oscillation signal is at a low level.

More optionally, the first discharge unit includes a second NMOS transistor and a third resistor; the source electrode of the second NMOS tube is grounded, the grid electrode of the second NMOS tube is connected with the first oscillation signal, and the drain electrode of the second NMOS tube is connected with the upper pole plates of the first capacitor and the second capacitor through the third resistor.

More optionally, the second discharge unit includes a fourth resistor, a fifth resistor, a sixth resistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; one end of the fourth resistor is connected with the working voltage, and the other end of the fourth resistor is connected with the drain electrode of the third NMOS tube; the grid electrode of the third NMOS tube is connected with a drain electrode voltage detection signal of the NMOS power tube, and the source electrode is grounded; one end of the fifth resistor is connected with the grid electrode of the third NMOS tube, and the other end of the fifth resistor is grounded; the source electrode of the fourth NMOS tube is grounded, the grid electrode of the fourth NMOS tube is connected with the first oscillation signal, and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube; and the grid electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the drain electrode is connected with the upper pole plates of the first capacitor and the second capacitor through the sixth resistor.

More optionally, the oscillation signal generation module further includes a first control unit; the first control unit receives a driving signal of an NMOS power tube and the first oscillation signal, and the output end of the first control unit is connected with the input end of the logic unit; when the inductive current is larger than a second preset value, the logic unit adjusts the first oscillating signal to further control the NMOS power tube to be turned off.

More optionally, the first control unit includes a sixth NMOS transistor, a seventh resistor, a first schmitt trigger, a first inverter, a second inverter, an eighth resistor, a third capacitor, a seventh NMOS transistor, and a first or logic gate; the source electrode of the sixth NMOS tube is grounded, the grid electrode of the sixth NMOS tube is connected with the driving signal of the NMOS power tube, and the drain electrode of the sixth NMOS tube is connected with the working voltage through the seventh resistor; the input end of the first Schmitt trigger is connected with the drain electrode of the sixth NMOS tube; the first inverter and the second inverter are sequentially connected in series with the output end of the first Schmitt trigger; one end of the eighth resistor is connected with the output end of the second inverter, and the other end of the eighth resistor is connected with the upper polar plate of the third capacitor; the lower polar plate of the third capacitor is grounded; the source electrode of the seventh NMOS tube is grounded, the grid electrode of the seventh NMOS tube is connected with the output end of the first phase inverter, and the drain electrode of the seventh NMOS tube is connected with the upper polar plate of the third capacitor; and a first input end of the first OR logic gate is connected with an upper polar plate of the third capacitor, a second input end of the first OR logic gate is connected with the first oscillation signal, and an output end of the first OR logic gate is connected with the logic unit.

More optionally, the oscillation signal generation module further includes a second control unit; the second control unit receives the drain voltage of the NMOS power tube, and the output end of the second control unit is connected with the input end of the logic unit; when the drain voltage of the NMOS power tube is smaller than the working voltage, the logic unit is used for adjusting the first oscillation signal so as to control the PMOS power tube to be switched off.

More optionally, the second control unit includes a comparator, a fourth capacitor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, and a ninth resistor; the comparator compares the drain voltage of the NMOS power tube with the working voltage and outputs a comparison result; the source electrode of the eighth NMOS tube is grounded, the grid electrode of the eighth NMOS tube is connected with the normal working signal of the oscillation signal generation module, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube; the grid electrode of the ninth NMOS tube is connected with the output end of the comparator, and the drain electrode of the ninth NMOS tube is connected with the working voltage and the logic unit through the ninth resistor; an upper polar plate of the fourth capacitor is connected with the output end of the comparator, and a lower polar plate of the fourth capacitor is connected with a source electrode of the ninth NMOS tube; and the source electrode of the tenth NMOS tube is connected with the source electrode of the ninth NMOS tube, the grid electrode of the tenth NMOS tube is connected with the driving signal of the NMOS power tube, and the drain electrode of the tenth NMOS tube is connected with the output end of the comparator.

More optionally, the driving circuit further includes an NMOS power transistor drain voltage detection module, where the NMOS power transistor drain voltage detection module includes an eighth PMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a third inverter, a third or logic gate, a tenth resistor, and a ninth PMOS transistor; the source electrode of the eighth PMOS tube is connected with the working voltage, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the fifteenth NMOS tube; the source electrode of the fifteenth NMOS tube is connected with the drain electrode of the sixteenth NMOS tube; the source electrode of the sixteenth NMOS tube is grounded; the grid electrodes of the eighth PMOS tube, the fifteenth NMOS tube and the sixteenth NMOS tube are connected with the driving signal of the PMOS power tube; the input end of the third inverter is connected with the drain electrode of the eighth PMOS tube; the input end of the third OR logic gate is connected with the output end of the third inverter and the switching signal; one end of the tenth resistor is connected with the drain electrode of the NMOS power tube, and the other end of the tenth resistor is connected with the source electrode of the ninth PMOS tube; the grid electrode of the ninth PMOS tube is connected with the output end of the third OR logic gate, and the drain electrode of the ninth PMOS tube outputs an NMOS power tube drain electrode voltage detection signal; wherein the switching signal is active when the output voltage is lower than a set output voltage.

More optionally, the driving module includes a first driving unit and a second driving unit;

More optionally, the first driving unit includes a fourth PMOS transistor, a fifth PMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a first nor gate, and a second nor gate; the source electrode of the fourth PMOS tube is connected with the output end of the charge pump module, the grid electrode of the fourth PMOS tube receives a switching signal, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the fifth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the inverse signal of the enable signal of the driving circuit, and the drain electrode of the fifth PMOS tube is connected with the drain electrode of the eleventh NMOS tube and outputs the first driving signal; the grid electrode of the eleventh NMOS tube receives the delay signal of the second oscillation signal, and the source electrode of the eleventh NMOS tube is grounded; the input end of the first NOR logic gate is connected with the switching signal and an inverted signal of an enabling signal of the driving circuit; the input end of the second NOR logic gate is connected with the output end of the first NOR logic gate and the delay signal of the second oscillation signal; the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the eleventh NMOS tube, the grid electrode of the twelfth NMOS tube is connected with the output end of the second NOR logic gate, and the source electrode of the twelfth NMOS tube is grounded; when the output voltage is lower than the set output voltage, the switching signal is effective, and the first driving unit is controlled to work.

More optionally, the second driving unit includes a sixth PMOS transistor, a seventh PMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a third nor logic gate, and a second or logic gate; the source electrode of the sixth PMOS tube is connected with the working voltage, the grid electrode of the sixth PMOS tube is connected with the enabling signal of the driving circuit, and the drain electrode of the sixth PMOS tube outputs the driving signal of the PMOS power tube; the input end of the third NOR logic gate is connected with the inverse signal of the second oscillating signal and the switching signal; the input end of the second OR logic gate is connected with the output end of the third NOR logic gate and the enable signal of the driving circuit; the source electrode of the seventh PMOS tube is connected with the working voltage, the grid electrode of the seventh PMOS tube is connected with the output end of the second OR logic gate, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the sixth PMOS tube; the drain electrode of the thirteenth NMOS tube is connected with the drain electrode of the seventh PMOS tube, the grid electrode of the thirteenth NMOS tube is connected with the output end of the second OR logic gate, and the source electrode of the thirteenth NMOS tube is connected with the drain electrode of the fourteenth NMOS tube; the grid electrode of the fourteenth NMOS tube is connected with a high-level enabling signal of the oscillation signal generating module, and the source electrode of the fourteenth NMOS tube is grounded.

To achieve the above and other related objects, the present invention provides a DCDC boost system, including at least:

a DCDC booster circuit, a PWM loop control circuit and the drive circuit;

As described above, the driving circuit and the DCDC boost system according to the present invention have the following advantageous effects:

the drive circuit and the DCDC boosting system can completely start the NMOS power tube under the condition of lower input voltage (0.8V as an example), accelerate the boosting speed and solve the problem that the boosting cannot be carried out. Meanwhile, when the output voltage reaches the set output voltage, the driving circuit stops working and does not participate in subsequent loop control.

Drawings

Fig. 1 is a schematic structural diagram of a driving circuit according to the present invention.

Fig. 2 is a schematic structural diagram of an oscillation signal generating module according to the present invention.

Fig. 3 is a schematic structural diagram of an enable signal generating unit according to the present invention.

Fig. 4 is a schematic structural diagram of a driving module according to the present invention.

Fig. 5 is a schematic structural diagram of an NMOS power transistor drain voltage detection module according to the present invention.

Fig. 6 is a schematic diagram of the DCDC boost system according to the present invention.

Fig. 7 is a schematic diagram showing the relationship between the waveforms of the driving signals NG and PG and the inductor current according to the present invention.

FIG. 8 is a diagram illustrating a simulation curve according to the present invention.

Description of the element reference numerals

1-a drive circuit; 11-a power supply module; 12-an oscillation signal generating module; 120-a first charging unit; 120a-NMOS current mirror; 120b-PMOS current mirror; 121-a second charging unit; 122-a first discharge cell; 123-a second discharge cell; 124-logic unit; 124 a-third and logic gate; 124 b-fifth or logic gate; 124 c-fourth and logic gate; 124 d-fifth and logic gate; 124 e-delay subunit; 125-enable signal generation unit; 126-a first enable signal generation unit; 126 a-first and logic gate; 126 b-second and logic gate; 127-a second enable signal generating unit; 128-a first control unit; 128 a-a first or logic gate; 129-a second control unit; 129 a-a comparator; 13-a charge pump module; 14-a drive module; 141-a first drive unit; 141 a-a first nor logic gate; 141 b-a second nor logic gate; 142-a second drive unit; 142 a-a third nor logic gate; 142 b-a second or logic gate; 15-NMOS power tube drain voltage detection module; 151-third or logic gate; 2-a PWM loop control circuit; 3-DCDC boost circuit.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present embodiment provides a driving circuit 1 for driving a DCDC boost circuit, where the driving circuit 1 includes: the system comprises a power module 11, an oscillation signal generating module 12, a charge pump module 13 and a driving module 14.

As shown in fig. 1, the power module 11 compares the input voltage VIN and the output voltage VOUT of the DCDC boost circuit, and uses the larger of the input voltage VIN and the output voltage VOUT as the operating voltage VDD of the driving circuit 1.

Specifically, the power module 11 compares the input voltage VIN with the output voltage VOUT and outputs the greater voltage VIN, and any circuit structure capable of implementing the comparison function and outputting the greater voltage is suitable for the present invention, which is not repeated herein.

As shown in fig. 1, the oscillating signal generating module 12 is connected to the input voltage VIN and the operating voltage VDD, and configured to generate an oscillating signal, and adjust the frequency of the oscillating signal based on the magnitude of the inductor current in the DCDC boost circuit.

Specifically, the oscillating signal generating module 12 generates oscillating signals with different frequencies based on the voltage value of the input voltage VIN. As shown in fig. 2, in the present embodiment, the oscillation signal generating module 12 includes a first charging unit 120, a second charging unit 121, a first discharging unit 122, a second discharging unit 123, a first capacitor C1, a second capacitor C2 and a logic unit 124. The lower plate of the first capacitor C1 is grounded, and the lower plate of the second capacitor C2 is connected to the first oscillation signal osc output by the logic unit 124; a discharge current in the first discharge cell 122 is smaller than a discharge current in the second discharge cell 123.

Specifically, as shown in fig. 3, as an implementation manner of the present invention, the oscillation signal generating module 12 further includes an enable signal generating unit 125, and the enable signal generating unit 125 includes a fourth inverter not4, a tenth PMOS transistor P10, an eleventh resistor R11, a seventeenth NMOS transistor N17, a fifth capacitor C5, a fifth inverter not5, a first nor gate 1, and a sixth inverter not 6. The input terminal of the fourth inverter not4 is connected to the soft start signal sys _ soft of the driving circuit 1. The source of the tenth PMOS transistor P10 is connected to the operating voltage VDD, the gate thereof is connected to the output terminal of the fourth inverter not4, and the drain thereof is connected to the drain of the seventeenth NMOS transistor N17 via the eleventh resistor R11. The gate of the seventeenth NMOS transistor N17 is connected to the output terminal of the fourth inverter not4, and the source is grounded. An upper polar plate of the fifth capacitor C5 is connected with a drain electrode of the seventeenth NMOS transistor N17, and a lower polar plate is grounded. An input end of the fifth inverter not5 is connected to a drain electrode of the seventeenth NMOS transistor N17. An input terminal of the first nor gate nor1 is connected to an output terminal of the fifth inverter not5 and the switching signal chp _ off, and outputs a high-level enable signal en _ h of the oscillation signal generation module 12. The sixth inverter not6 is connected to the output terminal of the first nor gate nor1, and outputs a low level enable signal en _ l of the oscillation signal generating block 12. When the high level enable signal en _ h is at a high level and the low level enable signal en _ l is at a low level, the oscillation signal generating module 12 works normally.

More specifically, as shown in fig. 2, the first charging unit 120 is connected to the upper plates of the first capacitor C1 and the second capacitor C2, and provides a first charging current related to the input voltage VIN. As an example, the first charging unit 120 includes a first PMOS transistor P1, a first resistor R1, a first NMOS transistor N1, an NMOS current mirror 120a, a PMOS current mirror 120b, and a second PMOS transistor P2. The source of the first PMOS transistor P1 is connected to the input voltage VIN, the gate thereof receives a first enable signal en1, and the drain thereof is connected to the input terminal of the NMOS current mirror 120a via the first resistor R1. The drain of the first NMOS transistor N1 is connected to the input terminal of the NMOS current mirror 120a, the gate receives the first enable signal en1, and the source is grounded. The input end of the PMOS current mirror 120b is connected to the output end of the NMOS current mirror 120a, and the power end is connected to the input voltage VIN. The source of the second PMOS transistor P2 is connected to the output terminal of the PMOS current mirror 120b, the gate thereof is connected to the first oscillation signal osc, and the drain thereof is connected to the upper plates of the first capacitor C1 and the second capacitor C2. In this embodiment, the NMOS current mirror 120a is formed by two NMOS transistors, and the PMOS current mirror 120b is formed by two PMOS transistors, which are not described herein. Wherein the first enable signal en1 controls the first charging current unit 120 to provide the first charging current when the oscillation signal generation module 120 is operating normally and the first oscillation signal osc is low. In this embodiment, the first charging current satisfies: VIN-VTH/R1, wherein VIN is the threshold voltage of the first PMOS transistor P1, and R1 is the resistance of the first resistor. The first charging current is a portion of a charging current that is enabled to be correlated with input and output after the output voltage VOUT reaches the input voltage VIN.

More specifically, as shown in fig. 2, as another implementation manner of the present invention, the oscillation signal generating module 12 further includes a first enable signal generating unit 126; the first enable signal generating unit 126 includes a first and logic gate 126a, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, an eleventh PMOS transistor P11, a twelfth PMOS transistor P12, a thirteenth PMOS transistor P13, a second and logic gate 126b, and a first nand gate nand 1. The input terminal of the first and logic gate 126a is connected to the high-level enable signal en _ h and the second oscillation signal chp _ step output by the logic unit 124. The eighteenth NMOS transistor N18 has a source grounded, a gate connected to the output of the first and logic gate 126a, and a drain connected to the drain of the eleventh PMOS transistor P11 and the gate of the twelfth PMOS transistor P12. The sources of the eleventh PMOS transistor P11 and the twelfth PMOS transistor P12 are connected to the input voltage VIN. The drain of the nineteenth NMOS transistor N19 is connected to the drain of the twelfth PMOS transistor P12 and the gate of the eleventh PMOS transistor P11, the gate is connected to the first oscillation signal osc, and the source is grounded. The source of the thirteenth PMOS transistor P13 is connected to the input voltage VIN, the gate is connected to the high-level enable signal en _ h, and the drain is connected to the drain of the nineteenth NMOS transistor N19. The input terminal of the second and logic gate 126b is connected to the high level enable signal en _ h and the enable signal en of the driving circuit. An input end of the first nand gate nand1 is connected to the drain of the nineteenth NMOS transistor N19 and the output end of the second and logic gate 126b, and outputs the first enable signal en 1. As an example, the first and logic gate 126a and the second and logic gate 126b are implemented by connecting nand gates to inverters, and in practical use, any circuit structure capable of implementing and logic is suitable for the present invention.

More specifically, as shown in fig. 2, the second charging unit 121 is connected to the upper plates of the first capacitor C1 and the second capacitor C2, and provides a second charging current related to the operating voltage VDD. As an example, the second charging unit 121 includes a third PMOS transistor P3 and a second resistor R2. The source of the third PMOS transistor P3 is connected to the operating voltage VDD, the gate thereof receives a second enable signal en2, and the drain thereof is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the upper plates of the first capacitor C1 and the second capacitor C2. Wherein the second enable signal en2 controls the second charging unit 121 to provide the second charging current when the oscillation signal generating module 120 is operating normally and the first oscillation signal osc is at a low level.

More specifically, as shown in fig. 2, as another implementation manner of the present invention, the oscillation signal generating module 12 further includes a second enable signal generating unit 127; the second enable signal generating unit 127 includes a fourth or logic gate, an input terminal of which is connected to the low level enable signal en _ l and the first oscillation signal osc, and outputs the second enable signal en 2. As an example, the fourth or logic gate is implemented by connecting the output end of the nor gate to the inverter, and in practical use, any circuit structure capable of implementing or logic is suitable for the present invention.

More specifically, as shown in fig. 2, the first discharging unit 122 is connected to the upper plates of the first capacitor C1 and the second capacitor C2, and when the inductor current in the DCDC boost circuit is greater than a first preset value, the first discharging unit 122 discharges the first capacitor C1 and the second capacitor C2. As an example, the first discharge unit 122 includes a second NMOS transistor N2 and a third resistor R3. The source of the second NMOS transistor N2 is grounded, the gate thereof is connected to the first oscillation signal osc, and the drain thereof is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the upper plates of the first capacitor C1 and the second capacitor C2.

More specifically, as shown in fig. 2, the second discharging unit 123 is connected to the upper plates of the first capacitor C1 and the second capacitor C2, and when the inductor current is smaller than the first preset value, the first capacitor C1 and the second capacitor C2 are discharged through the second discharging unit 123. As an example, the second discharge unit 123 includes a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a third NMOS transistor N3, a fourth NMOS transistor N4, and a fifth NMOS transistor N5. One end of the fourth resistor R4 is connected to the operating voltage VDD, and the other end is connected to the drain of the third NMOS transistor N3. The grid electrode of the third NMOS tube N3 is connected with the drain electrode voltage detection signal step _ ctr of the NMOS power tube, and the source electrode is grounded. One end of the fifth resistor R5 is connected to the gate of the third NMOS transistor N3, and the other end is grounded. The source of the fourth NMOS transistor N4 is grounded, the gate thereof is connected to the first oscillation signal osc, and the drain thereof is connected to the drain of the fifth NMOS transistor N5. The gate of the fifth NMOS transistor N5 is connected to the drain of the third NMOS transistor N3, and the drain is connected to one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the upper plates of the first capacitor C1 and the second capacitor C2. As another example, the second discharge unit 123 further includes a twentieth NMOS transistor 20, a source and a gate of the twentieth NMOS transistor 20 are grounded, and a drain of the twentieth NMOS transistor 20 is connected to the gate of the fifth NMOS transistor.

It should be noted that the first preset value may be set to a specific value according to actual needs, which is not described herein in detail. In this embodiment, the resistance of the third resistor R3 is greater than that of the sixth resistor R6, so as to generate different discharge times; when the inductive current is large, the branch circuit where the third resistor R3 is located is used for discharging, the discharging time is longer, and the inductive current is exhausted; on the contrary, when the inductive current is smaller, the branch circuit where the sixth resistor R6 is located is used for discharging, the discharging time is shortened, and the inductive current energy storage period is entered more quickly.

More specifically, as shown in fig. 2, the logic unit 124 is connected to the upper plates of the first capacitor C1 and the second capacitor C2, generates a first oscillation signal osc based on the charging and discharging of the first capacitor C1 and the second capacitor C2, and outputs a second oscillation signal chp _ step that is opposite in phase to the first oscillation signal osc, a third oscillation signal chp _ osc that is in phase with the first oscillation signal osc, and a delay signal chp _ step _ d of the second oscillation signal when the enable signals (the high-level enable signal en _ h and the low-level enable signal en _ l) of the oscillation signal generation module 12 are active.

More specifically, as shown in fig. 2, as another implementation manner of the present invention, the oscillation signal generation module 12 further includes a first control unit 128; the first control unit 128 receives the driving signal NG of the NMOS power transistor and the first oscillation signal osc, and the output terminal is connected to the input terminal of the logic unit 124; when the inductor current is greater than a second predetermined value, the logic unit 124 adjusts the first oscillation signal osc to control the NMOS power transistor Q1 to turn off. As an example, the first control unit 128 includes a sixth NMOS transistor N6, a seventh resistor R7, a first schmitt trigger smit1, a first inverter not1, a second inverter not2, an eighth resistor R8, a third capacitor C3, a seventh NMOS transistor N7, and a first or logic gate 128 a. The source of the sixth NMOS transistor N6 is grounded, the gate is connected to the driving signal NG of the NMOS power transistor, and the drain is connected to the operating voltage VDD via the seventh resistor R7. The input end of the first Schmitt trigger smit1 is connected with the drain electrode of the sixth NMOS tube N6. The first inverter not1 and the second inverter not2 are sequentially connected in series at the output end of the first schmitt trigger smit 1. One end of the eighth resistor R8 is connected to the output end of the second inverter not2, and the other end is connected to the upper plate of the third capacitor C3. The lower plate of the third capacitor C3 is grounded. The source of the seventh NMOS transistor N7 is grounded, the gate thereof is connected to the output terminal of the first inverter not1, and the drain thereof is connected to the upper plate of the third capacitor C3. The first or logic gate 128a has a first input connected to the upper plate of the third capacitor C3, a second input connected to the first oscillation signal osc, and an output connected to the logic unit 124. The first or logic gate 128a is implemented by connecting the output terminal of the nor gate to the inverter, and any circuit structure capable of implementing or logic is suitable for the present invention in practical use.

It should be noted that the second preset value may be set to a specific value according to actual needs, which is not described herein in detail. The first control unit 128 is used for limiting the turn-on time of the NMOS power transistor Q1; the sixth NMOS transistor N6 has the same type as the NMOS power transistor Q1, the same channel length L, and the channel width W ratio of N: 1, n is a real number; the seventh resistor R7 is used to control the on-time of the NMOS power transistor Q1 when the input voltage VIN is very small, so as to ensure that the NMOS power transistor Q1 can be turned off only when the current on the inductor reaches (VIN/R7) × n.

More specifically, as shown in fig. 2, as another implementation manner of the present invention, the oscillation signal generating module 12 further includes a second control unit 129; the second control unit 129 receives the drain voltage SW of the NMOS power transistor, and the output end is connected to the input end of the logic unit 124; when the drain voltage SW of the NMOS power transistor is less than the working voltage VDD, the logic unit 124 adjusts the first oscillation signal osc to control the PMOS power transistor Q2 to turn off. As an example, the second control unit includes a comparator 129a, a fourth capacitor C4, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, and a ninth resistor R9. The comparator 129a compares the drain voltage SW of the NMOS power transistor with the working voltage VDD, and outputs a comparison result; in this embodiment, the comparator 129a includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a twenty-first NMOS transistor N21, a twenty-second NMOS transistor N22, and a twenty-third NMOS transistor N23; one end of the twelfth resistor R12 is connected with the drain voltage SW of the NMOS power tube, and the other end is connected with the drain and the grid of the twenty-first NMOS tube N21; one end of the thirteenth resistor R13 is connected with the working voltage VDD, and the other end of the thirteenth resistor R13 is connected with the drain of the twenty-second NMOS transistor N22; the grid electrode of the twenty-second NMOS transistor N22 is connected with the grid electrode of the twenty-first NMOS transistor N21, and the source electrode of the twenty-second NMOS transistor N22 is connected with the source electrode of the twenty-first NMOS transistor N21 and the drain electrode of the twenty-third NMOS transistor N23; the gate of the twenty-third NMOS transistor N23 is connected to the high-level enable signal en _ h, and the source is grounded; one end of the fourteenth resistor R14 is connected to the drain of the twenty-second NMOS transistor N22, and the other end outputs the comparison result; in practical use, any circuit structure capable of comparing the drain voltage SW of the NMOS power transistor with the operating voltage VDD and outputting the comparison result is suitable for the present invention, and is not limited to this embodiment. The eighth NMOS transistor N8 has a source grounded, a gate connected to the normal operation signal (the high level enable signal en _ h) of the oscillation signal generating module 12, and a drain connected to the source of the ninth NMOS transistor N9. The gate of the ninth NMOS transistor N9 is connected to the output terminal of the comparator 129a, and the drain is connected to the operating voltage VDD and the logic unit 124 through the ninth resistor R9. The upper plate of the fourth capacitor C4 is connected to the output terminal of the comparator 129a, and the lower plate is connected to the source of the ninth NMOS transistor N9. The source of the tenth NMOS transistor N10 is connected to the source of the ninth NMOS transistor N9, the gate is connected to the driving signal NG of the NMOS power transistor, and the drain is connected to the output terminal of the comparator 129 a.

It should be noted that the resistances of the third resistor R3 and the sixth resistor R6 are fixed, and if the discharge time of the third resistor R3 is too long and the PMOS power transistor is turned on too long, the inductor will be in a low power state. Therefore, the second control unit detects the drain voltage SW of the NMOS power tube, judges that the inductive current is exhausted when the drain voltage SW of the NMOS power tube is lower than the working voltage VDD, changes the fixed frequency, closes the PMOS power tube in advance, and starts a new charging period.

It should be noted that, in the case of including the first control unit 128 and the second control unit 129, as shown in fig. 2, the logic unit 124 includes a third and logic gate 124a, a fifth or logic gate 124b, a fourth and logic gate 124c, a second schmitt trigger smit2, a ninth inverter not9, a fifth and logic gate 124d, a tenth inverter not10, a second nand gate nand2, and a delay subunit 124 e. A first input terminal of the third and logic gate 124a is connected to the upper plates of the first capacitor C1 and the second capacitor C2, and a second input terminal thereof is connected to an output terminal of the first control unit 128; as an example, a twenty-fourth NMOS transistor N24, a seventh inverter not7 and an eighth inverter not8 are further included between the first input terminal of the third and logic gate 124a and the upper plates of the first capacitor C1 and the second capacitor C2; the drain electrode of the twenty-fourth NMOS transistor N24 is connected to the upper electrode plates of the first capacitor C1 and the second capacitor C2, the gate electrode is connected to the low-level enable signal en _ l, and the source electrode is grounded; the seventh inverter not7 and the eighth inverter not8 are sequentially connected in series to the upper plates of the first capacitor C1 and the second capacitor C2. An input of the fifth or logic gate 124b is connected to the output of the third and logic gate 124a and the first oscillating signal osc. The input of the fourth and logic gate 124c is connected to the outputs of the third and logic gate 124a and the fifth or logic gate 124 b. An input terminal of the second schmitt trigger smit2 is connected to an output terminal of the second control unit 129, and an input terminal of the ninth inverter not9 is connected to an output terminal of the second schmitt trigger smit 2. The input terminal of the fifth and logic gate 124d is connected to the output terminals of the fourth and logic gate 124c and the ninth inverter not9, and outputs the first oscillation signal osc. An input terminal of the tenth inverter not10 is connected to an output terminal of the fifth and logic gate 124d, and outputs the second oscillation signal chp _ step inverted from the first oscillation signal osc. An input terminal of the second nand gate nand2 is connected to the output terminal of the tenth inverter not10 and the high level enable signal en _ h, and outputs the third oscillation signal chp _ osc which is in phase with the first oscillation signal osc when the oscillation signal generating module 12 is operating normally. The delay subunit 124e is connected to the output end of the tenth inverter not10, and is configured to generate a delayed signal chp _ step _ d of the second oscillation signal; as an example, the delay subunit 124e includes a second nor gate nor2, a twenty-sixth NMOS transistor N26, a fifteenth resistor R15, a fourteenth PMOS transistor P14, the fifth capacitor C5, and the eleventh inverter not 11; an input terminal of the second nor gate nor2 is connected to an output terminal of the tenth inverter not10 and the low level enable signal en _ l; the source of the twenty-sixth NMOS transistor N26 is grounded, and the gate is connected to the output end of the second nor gate 2; the drain electrode is connected with the drain electrode of the fourteenth PMOS tube P14 through the fifteenth resistor R15; the gate of the fourteenth PMOS transistor P14 is connected to the output end of the second nor gate 2, and the source is connected to the working voltage VDD; an upper polar plate of the fifth capacitor C5 is connected with a drain electrode of the twenty-sixth NMOS transistor N26, and a lower polar plate is grounded; an input end of the eleventh inverter not11 is connected to a drain of the twenty-sixth NMOS transistor N26, and outputs a delayed signal chp _ step _ d of the second oscillation signal; the delay time may be set by adjusting the resistance of the fifteenth resistor R15 and the capacitance of the fifth capacitor C5 as required, which is not limited herein. As an example, the third and logic gate 124a, the fourth and logic gate 124c, and the fifth and logic gate 124d are implemented by connecting an output end of a nand gate to an inverter, and in practical use, any circuit structure capable of implementing and logic is suitable for the present invention; the fifth or logic gate 124b is implemented by connecting the output end of the nor gate to the inverter, and in practical use, any circuit structure capable of implementing or logic is suitable for the present invention.

As shown in fig. 1, the charge pump module 13 is connected to the output end of the oscillation signal generating module 12, and boosts the operating voltage VDD based on the oscillation signal output by the oscillation signal generating module 12 to output VCHP.

Specifically, in the present embodiment, the voltage value of the output signal VCHP of the charge pump module 13 is set to VDD + vth-2 VDD (including the end point).

Specifically, the structure of the charge pump module 13 is not limited, and any structure capable of boosting the working voltage VDD is suitable for this, which is not repeated herein. In this embodiment, the charge pump module 13 receives the third oscillation signal chp _ osc, and also receives the enable signal en, the high-level enable signal en _ h, and the low-level enable signal en _ l of the driving circuit, and when each enable signal is valid, the charge pump module 13 starts to operate, so as to ensure that the charge pump module 13 starts to operate after the oscillation signal generation module 12 normally operates, thereby saving energy consumption.

As shown in fig. 1, the driving module 14 is connected to the output terminals of the oscillation signal generating module 12 and the charge pump module 13, and provides driving signals for the NMOS power transistor Q1 and the PMOS power transistor Q2 when the output voltage VOUT is lower than a set output voltage UVLO.

Specifically, the driving module 14 includes a first driving unit 141 and a second driving unit 142. The first driving unit 141 receives the output signal VCHP of the charge pump module 13, and generates a first driving signal (i.e., the driving signal NG of the NMOS power transistor Q1) having the same frequency as the delay signal chp _ step _ d of the second oscillation signal when the output voltage VOUT is lower than the set output voltage UVLO, where a high level of the first driving signal is equal to a level of the output signal VCHP of the charge pump module 13; when the output voltage VOUT is higher than a set output voltage UVLO, the first driving signal is in a high-impedance state; the first driving signal is used for driving the NMOS power transistor Q1. The second driving unit 142 receives the working voltage VDD, and generates a second driving signal (i.e., the driving signal PG of the PMOS power transistor Q2) with the same frequency as the second oscillating signal chp _ step when the output voltage VOUT is lower than a set output voltage UVLO, where a high level of the second driving signal is equal to a level of the working voltage VDD; when the output voltage VOUT is higher than a set output voltage UVLO, the second driving signal is in a high-impedance state; the second driving signal is used for driving the PMOS power transistor Q2.

More specifically, as shown in fig. 4, the first driving unit 141 includes a fourth PMOS transistor P4, a fifth PMOS transistor P5, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a first nor gate 141a, and a second nor gate 141 b. The source of the fourth PMOS transistor P4 is connected to the output signal VCHP of the charge pump module 13, the gate receives a switching signal chp _ off (the switching signal chp _ off is obtained by a detection signal UVLO _ off through a twelfth inverter not12 and a thirteenth inverter not13 in cascade, the detection signal UVLO _ off is effective when the output voltage VOUT is lower than the set output voltage UVLO, in this embodiment, the detection signal UVLO is effective in a low level), and the drain is connected to the source of the fifth PMOS transistor P5. The gate of the fifth PMOS transistor P5 is connected to the inverse signal of the enable signal en of the driving circuit (obtained by the enable signal en of the driving circuit passing through the sixteenth inverter not 16), and the drain is connected to the drain of the eleventh NMOS transistor N11 to output the first driving signal. The gate of the eleventh NMOS transistor N11 receives the delayed signal chp _ step _ d of the second oscillation signal (transmitted to the gate of the eleventh NMOS transistor N11 via the cascaded fourteenth inverter not14 and fifteenth inverter not 15), and the source is grounded. The input end of the first nor logic gate 141a is connected to the switching signal chp _ off and the inverse signal of the enable signal en of the driving circuit; in this embodiment, the first nor logic gate 141a is implemented as a nor gate. The input terminal of the second nor gate 141b is connected to the output terminal of the first nor gate 141a and the delayed signal chp _ step _ d of the second oscillation signal. The drain of the twelfth NMOS transistor N12 is connected to the drain of the eleventh NMOS transistor N11, the gate thereof is connected to the output terminal of the second nor gate 141b, and the source thereof is grounded. When the output voltage VOUT is lower than the set output voltage UVLO, the switching signal chp _ off is asserted to control the first driving unit 141 to operate. As an example, the second nor logic gate 141b is implemented by connecting an output terminal of an or gate to an inverter.

More specifically, as shown in fig. 4, the second driving unit 142 includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a third nor gate 142a, and a second or gate 142 b. The source of the sixth PMOS transistor P6 is connected to the operating voltage VDD, the gate is connected to the enable signal en of the driving circuit (the enable signal en of the driving circuit is transmitted to the gate of the sixth PMOS transistor P6 via the sixteenth inverter not16 and the seventeenth inverter not17, which are cascaded), and the drain outputs the driving signal PG of the PMOS power transistor Q2. The input terminal of the third nor logic gate 142a is connected to the inverse signal of the second oscillation signal chp _ step (obtained by the second oscillation signal chp _ step passing through the eighteenth inverter not 18) and the switching signal chp _ off; as an example, the third nor logic gate 142a is implemented by a nor gate. An input terminal of the second or logic gate 142b is connected to an output terminal of the third nor logic gate 142a and an enable signal en of the driving circuit. The source of the seventh PMOS transistor P7 is connected to the operating voltage VDD, the gate thereof is connected to the output terminal of the second or logic gate 142b (in this embodiment, the output terminal of the second or logic gate 142b is connected to the gate of the seventh PMOS transistor P7 through the nineteenth inverter not19 and the twentieth inverter not20, which are cascaded), and the drain thereof is connected to the drain of the sixth PMOS transistor P6. The drain of the thirteenth NMOS transistor N13 is connected to the drain of the seventh PMOS transistor P7, the gate is connected to the output of the second or logic gate 142b (in this embodiment, the output of the second or logic gate 142b is connected to the gate of the thirteenth NMOS transistor N13 through the cascaded nineteenth inverter not19 and twenty inverter not 20), and the source is connected to the drain of the fourteenth NMOS transistor N14. The gate of the fourteenth NMOS transistor N14 is connected to the high-level enable signal en _ h of the oscillation signal generating module (in the embodiment, the high-level enable signal en _ h is connected to the gate of the fourteenth NMOS transistor N14 through the twenty-first inverter not21 and the twenty-second inverter not22 in cascade), and the source is grounded. As an example, the second or logic gate 142b is implemented by connecting an output end of a nor gate to an inverter.

In low-voltage operation, the detection signal uvlo _ off is at a logic low level, so that the fourth PMOS transistor P4 is normally on; an enable signal en of the driving circuit is at a logic high level, so that the fifth PMOS transistor P5 is normally on; thus, the voltage of the driving signal NG of the NMOS power transistor Q1 is the voltage of VCHP, the delay signal chp _ step _ d of the second oscillation signal controls the on and off of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12, the output signal VCHP of the charge pump module 13 is not enough to have an excessive load capacity in the prior art, so the driving signal NG of the NMOS power transistor Q1 is pulled down to 0 by the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12, and the on and off of the eleventh NMOS transistor N11 and the twelfth NMOS transistor N12 can realize that NG 0 to VCHP waveforms are generated. The twelfth NMOS transistor N12 is further controlled by the detection signal uvlo _ off and the enable signal en of the driving circuit, so as to be in a high impedance state after the control loop is switched. The driving signal PG of the PMOS power transistor Q2 is controlled by the enable signal en, the second oscillation signal chp _ step, the switching signal chp _ off, and the high-level enable signal en _ h of the driving circuit, and cooperates with the oscillation signal generating module 12 to switch the PMOS power transistor Q2, so as to be in a high impedance state after switching a control loop.

As shown in fig. 5, as another implementation manner of the present invention, the driving circuit 1 further includes an NMOS power transistor drain voltage detection module 15, where the NMOS power transistor drain voltage detection module 15 includes an eighth PMOS transistor P8, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a third inverter not3, a third or logic gate 151, a tenth resistor R10, and a ninth PMOS transistor P9. The source of the eighth PMOS transistor P8 is connected to the operating voltage VDD, and the drain is connected to the drain of the fifteenth NMOS transistor N15. The source of the fifteenth NMOS transistor N15 is connected to the drain of the sixteenth NMOS transistor N16. The source of the sixteenth NMOS transistor N16 is grounded. The gates of the eighth PMOS transistor P8, the fifteenth NMOS transistor N15 and the sixteenth NMOS transistor N16 are connected to the driving signal PG of the PMOS power transistor. The input end of the third inverter not3 is connected to the drain of the eighth PMOS transistor P8. An input terminal of the third or logic gate 151 is connected to an output terminal of the third inverter not3 and the switching signal chp _ off. One end of the tenth resistor R10 is connected to the drain (SW) of the NMOS power transistor, and the other end is connected to the source of the ninth PMOS transistor P9. The gate of the ninth PMOS transistor P9 is connected to the output terminal of the third or logic gate 151, and the drain thereof outputs an NMOS power transistor drain voltage detection signal step _ ctr. Wherein the switching signal chp _ off is active when the output voltage VOUT is lower than a set output voltage UVLO.

It should be noted that the eighth PMOS transistor P8 is configured to detect an inductor current after the driving voltage PG of the PMOS power transistor is completely turned on; the eighth PMOS transistor P8 has the same type as the PMOS power transistor Q2, the same channel length L and the channel width W ratio of m: 1, m is a real number.

Example two

As shown in fig. 6, the present embodiment provides a DCDC boost system, including:

a DCDC boost circuit 3, a PWM loop control circuit 2, and a drive circuit 1.

As shown in fig. 6, the DCDC boost circuit 3 includes an NMOS power transistor Q1 and a PMOS power transistor Q2; when the output voltage VOUT of the DCDC boost circuit 3 is lower than a set output voltage, the driving circuit 1 provides driving signals for the NMOS power transistor Q1 and the PMOS power transistor Q2; when the output voltage VOUT of the DCDC boost circuit 3 is higher than a set output voltage, the PWM loop control circuit 2 provides driving signals for the NMOS power transistor Q1 and the PMOS power transistor Q2.

Specifically, in the present embodiment, the DCDC boost circuit 3 includes an inductor L, NMOS power transistor Q1, a PMOS power transistor Q2, and a capacitor C. One end of the inductor L is connected to the input voltage VIN, and the other end is connected to the drain (denoted as SW) of the NMOS power transistor Q1. The gate of the NMOS power transistor Q1 receives the driving signal NG, and the source is grounded. The drain of the PMOS power transistor Q2 is connected to the drain of the NMOS power transistor Q1, the gate receives the driving signal PG, the source is grounded via the capacitor C, and the output voltage is output. In practical use, the structure of the DCDC boost circuit 3 is not limited, and any circuit structure that can realize a boost function based on the NMOS power tube Q1 and the PMOS power tube Q2 is applicable.

Specifically, when the output voltage VOUT of the DCDC boost circuit 3 is lower than a set output voltage, the driving circuit 1 provides driving signals for the NMOS power transistor Q1 and the PMOS power transistor Q2. The structure and the operation principle of the driving circuit 1 are as described in the first embodiment, and are not described herein in detail.

Specifically, when the output voltage VOUT of the DCDC boost circuit 3 is higher than a set output voltage, the PWM loop control circuit 2 provides driving signals for the NMOS power transistor Q1 and the PMOS power transistor Q2. The PWM loop control circuit 2 generates the driving signals of the NMOS power transistor Q1 and the PMOS power transistor Q2 based on system parameters including, but not limited to, a load, an output voltage VOUT, an input voltage VIN, an input ac power, and the like, and specific principles thereof are not described herein in detail.

As shown in fig. 7, the relationship between the waveforms of the driving signals NG and PG and the inductor current in the present invention is shown, the present invention can still raise the gate voltage of the NMOS power transistor to a reasonable threshold range when the starting voltage is 0.8V, and the waveform of the gate voltage of the PMOS power transistor is generated along with the waveform change of the gate voltage of the NMOS power transistor, so that the inductor can complete a more efficient charge and discharge cycle. After the output voltage reaches a certain value, the PMOS power tube and the NMOS power tube are switched to main drive logic control (controlled by a PWM loop control circuit 2). As shown in fig. 8, for an actual simulation curve of the output voltage, the DCDC boost circuit is divided into three stages of boost, and the PMOS power transistor is half-turned on in the first stage, so that VOUT reaches VIN; in the second stage, boosting is carried out through a charge pump, NG is started to store energy for inductive current, and then PG is started to enable VOUT to reach a set output voltage UVLO; and in the third stage, loop control is adopted to charge and discharge the inductive current, so that VOUT reaches a target value and the voltage is constant. The design of the invention is a scheme for boosting VOUT in a phase (second phase) that VIN < VOUT < UVLO.

In summary, the present invention provides a driving circuit and a DCDC boost system, including: the power supply module compares the input voltage and the output voltage of the DCDC booster circuit and takes the larger of the input voltage and the output voltage as the working voltage of the driving circuit; the oscillation signal generation module is connected with the input voltage and the working voltage, and is used for generating an oscillation signal and adjusting the frequency of the oscillation signal based on the magnitude of the inductive current in the DCDC booster circuit; the charge pump module is connected to the output end of the oscillation signal generation module and used for boosting the working voltage based on the oscillation signal output by the oscillation signal generation module; and the driving module is connected with the output ends of the oscillation signal generation module and the charge pump module and provides driving signals for the NMOS power tube and the PMOS power tube when the output voltage is lower than a set output voltage. According to the driving circuit and the DCDC boosting system, under the condition that the input voltage is low (0.8V as an example), the NMOS power tube is completely started, the boosting speed is increased, and the problem that the voltage cannot be boosted when the load is carried is solved. Meanwhile, when the output voltage reaches the set output voltage, the driving circuit stops working and does not participate in subsequent loop control. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

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