阅读说明：本技术 片上低频振荡器 (On-chip low frequency oscillator ) 是由 卢志坚 于 2021-08-31 设计创作，主要内容包括：本申请涉及一种振荡器电路,包括反相模块,其输入端耦合到所述振荡器电路的输出端；反相模块,其第一端耦合到所述反相模块的输出端,其第二端耦合到所述振荡器电路的输出端,所述电容模块包括至少两个彼此串联的第一电容和第二电容,所述第一电容的第一端耦合到所述反相模块的输出端,所述第一电容的第二端与所述第二电容的第一端以及所述振荡器电路的输出端彼此耦合,所述第二电容的第二端接地；充电模块,耦合在电源和电容模块之间,配置为向所述电容模块充电；放电模块,耦合在所述电容模块和地之间,配置为给所述电容模块放电；所述充电模块与所述放电模块通过所述振荡器电路的输出端彼此耦合,且所述充电模块和所述放电模块导通的状态相反。(An oscillator circuit includes an inverting module having an input coupled to an output of the oscillator circuit; an inverting module having a first terminal coupled to the output terminal of the inverting module and a second terminal coupled to the output terminal of the oscillator circuit, the capacitive module including at least two first and second capacitors connected in series with each other, the first terminal of the first capacitor being coupled to the output terminal of the inverting module, the second terminal of the first capacitor being coupled to the first terminal of the second capacitor and the output terminal of the oscillator circuit, the second terminal of the second capacitor being connected to ground; a charging module coupled between a power source and a capacitive module, configured to charge the capacitive module; a discharge module coupled between the capacitive module and ground configured to discharge the capacitive module; the charging module and the discharging module are coupled with each other through the output end of the oscillator circuit, and the conduction states of the charging module and the discharging module are opposite.)

1. An oscillator circuit, comprising:

an inverting module having an input coupled to an output of the oscillator circuit;

a capacitance module comprising at least two first and second capacitors connected in series, a first end of the first capacitor being coupled to the output of the inverting module, a second end of the first capacitor being coupled to the first end of the second capacitor and to the output of the oscillator circuit, and a second end of the second capacitor being coupled to ground;

a charging module coupled between a power source and a capacitive module, configured to charge the capacitive module; and

a discharge module coupled between the capacitive module and ground configured to discharge the capacitive module;

wherein the charging module and the discharging module are coupled to each other through an output terminal of the oscillator circuit, and states of conduction of the charging module and the discharging module are opposite.

2. The oscillator circuit of claim 1, wherein the inverting module includes an even number of inverters connected in series with one another.

3. The oscillator circuit of claim 2, wherein the charging module includes a first current source and a first switch coupled in series between a power supply and the oscillator circuit output, the first switch conducting when the output signal of the inverting module is low; and/or

The discharge module includes a second switch and a second current source coupled in series between the oscillator circuit output and ground, the second switch being conductive when the output signal of the inverter module is high.

4. The oscillator circuit of claim 3, wherein the currents of the first and second current sources are the same.

5. The oscillator circuit of claim 2, wherein the first and second capacitances are the same value.

6. The oscillator circuit of claim 3, wherein the first switch is a PMOS transistor and the second switch is an NMOS transistor.

7. The oscillator circuit of claim 2, further comprising

A charge-discharge signal generation module comprising an odd number of inverters, the input terminals of which are coupled to the output terminals of the inversion module;

the charging module comprises a first current source and a third switch which are coupled between a power supply and the output end of the oscillator circuit in series, the output end of the charging and discharging signal generation module is coupled to the control end of the third switch, and the third switch is turned on when the output signal of the charging and discharging signal generation module is high;

the discharge module includes a fourth switch and a fourth current source coupled in series between the oscillator circuit output and ground, the output of the inverter module is coupled to the control terminal of the fourth switch, and the fourth switch is turned on when the output signal of the inverter module is high.

8. An electronic device comprising an oscillator circuit as claimed in any one of claims 1 to 7.

Technical Field

The application relates to the technical field of integrated circuits, in particular to an on-chip low-frequency oscillator.

Background

Clock signals are only present in the digital chip once and are used for indicating the sequence of different events; the analog chip only needs to process analog signals, the occurrence of signal processing or events and input signals of the chip generate an instant relation, and a clock signal is not needed to indicate the sequence. With the wide application of the digital-analog mixed signal processing technology, for example, through communication between chips, the hardware configuration of an analog circuit is controlled to be changed as required, the accuracy and robustness of analog parameters are improved through digital calibration, the frequency conversion processing of communication signals and the like, and the occurrence and the ending of events are required to be specified by a clock signal with a certain accuracy requirement in a traditional analog chip.

Large-scale communication system on chip (SoC) has high requirement for clock accuracy, and a crystal oscillator is designed by matching with an off-chip quartz crystal to obtain a high-accuracy reference clock signal, even the off-chip high-accuracy reference clock signal is directly used. However, in many other application scenarios, an on-chip oscillator without an external reference is a preferred solution for generating the reference clock in consideration of low control cost, low requirement on clock accuracy, and low clock frequency.

Generally, an on-chip low-frequency oscillator without an external reference has a simple structure, low power consumption, and a certain degree of robustness of frequency according to a Process corner, a supply Voltage, and an ambient Temperature (PVT). The application provides an on-chip low-frequency oscillator which is widely applicable to a semiconductor process and has a simple structure.

Fig. 1 is a circuit diagram of a conventional Ring Oscillator (Ring Oscillator) on a chip. The basic structure is that odd inverters are connected end to form a ring, and the oscillation frequency is determined by the equivalent resistance of the switching transistor and the inter-stage parasitic capacitance. Because the oscillation frequency is greatly influenced by process, temperature and voltage (PVT), the ring oscillator is mostly designed in a frequency-adjustable form and used in a closed loop mode of a Phase-locked loop (PLL), and therefore, the ring oscillator cannot be directly applied to an on-chip low-frequency timing function without external reference.

Fig. 2 shows another conventional on-chip low-frequency oscillator circuit, which is an RC relaxation oscillator based on comparator for state switching. The principle is that two capacitors are charged and discharged circularly by using fixed current, the voltage on the capacitors is compared with the voltage drop on the resistor in turn, the charging and discharging states of the capacitors are switched when the comparison result is changed, the capacitors are circulated repeatedly, the working period (frequency) is directly determined by an RC constant and is basically irrelevant to the power supply voltage and the process change of a switching transistor. The structure is suitable for the application of low power consumption nW grade and low frequency KHz grade; for the accuracy of the frequency, the calibration of the RC constant is relied upon. The structure is complicated and not suitable for wide application.

Fig. 3(a) shows another conventional on-chip low frequency oscillator circuit. The RC is used for charging and discharging, the Vx voltage of the target node is compared with the overturning threshold value of the inverter, and the voltage of the target node related to the capacitor can jump instantly by depending on the intrinsic driving capability of the inverter so as to trigger state switching. The structure inherits the characteristics that the relaxation oscillator is suitable for low power consumption and low frequency, and depends on the calibration of an RC constant and a power supply voltage for the precision of the frequency.

FIG. 3(b) is a schematic diagram of the target node output signal of the circuit shown in FIG. 3 (a). As shown, the target node Vx voltage will overshoot momentarily by 1.5 times the supply voltage, so this configuration has some degree of limitation on the selection of transistors in the inverter (reliability considerations) and the generation of the supply voltage.

In summary, the conventional on-chip oscillator scheme cannot consider the factors of the precision of the frequency under the PVT variation, the simplicity of the structure and the implementation, the freedom of device selection, and the like.

Disclosure of Invention

An oscillator circuit is provided, comprising an inverting module having an input coupled to an output of the oscillator circuit; a capacitance module comprising at least two first and second capacitors connected in series, a first end of the first capacitor being coupled to the output of the inverting module, a second end of the first capacitor being coupled to the first end of the second capacitor and to the output of the oscillator circuit, and a second end of the second capacitor being coupled to ground; a charging module coupled between a power source and a capacitive module, configured to charge the capacitive module; a discharge module coupled between the capacitive module and ground configured to discharge the capacitive module; wherein the charging module and the discharging module are coupled to each other through an output terminal of the oscillator circuit, and states of conduction of the charging module and the discharging module are opposite.

In particular, the inversion module comprises an even number of inverters connected in series with each other.

In particular, the charging module comprises a first current source and a first switch coupled in series between a power supply and the oscillator circuit output, the first switch being conductive when the output signal of the inverting module is low; and/or the discharge module comprises a second switch and a second current source coupled in series between the oscillator circuit output and ground, the second switch being conductive when the output signal of the inverter module is high.

In particular, the first current source and the second current source have the same current.

In particular, the first and second capacitances are of the same value.

Specifically, the first switch is a PMOS transistor, and the second switch is an NMOS transistor.

Particularly, the oscillator circuit further comprises a charge-discharge signal generating module, which comprises an odd number of inverters, wherein the input end of the charge-discharge signal generating module is coupled to the output end of the inverting module; the charging module comprises a first current source and a third switch which are coupled between a power supply and the output end of the oscillator circuit in series, the output end of the charging and discharging signal generation module is coupled to the control end of the third switch, and the third switch is turned on when the output signal of the charging and discharging signal generation module is high; and/or the discharge module comprises a fourth switch and a fourth current source coupled in series between the oscillator circuit output and ground, the output of the inverter module is coupled to the control terminal of the fourth switch, and the fourth switch is turned on when the output signal of the inverter module is high.

The present application further provides an electronic device comprising an oscillator circuit as described in any of the preceding.

Drawings

Preferred embodiments of the present application will now be described in further detail with reference to the accompanying drawings, in which:

FIG. 1 is a circuit diagram of a conventional on-chip ring oscillator;

FIG. 2 illustrates another prior art on-chip low frequency oscillator circuit;

FIG. 3(a) shows another prior art on-chip low frequency oscillator circuit;

FIG. 3(b) is a schematic diagram of the target node output signal of the circuit shown in FIG. 3 (a);

FIG. 4 is a schematic diagram of an oscillator circuit according to one embodiment of the present application;

FIG. 5 is a schematic diagram of the operating timing signals of the oscillator shown in FIG. 4; and

fig. 6 is a schematic diagram of an oscillator circuit according to another embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof and in which is shown by way of illustration specific embodiments of the application. In the drawings, like numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized and structural, logical or electrical changes may be made to the embodiments of the present application.

Fig. 4 is a schematic diagram of an oscillator circuit according to an embodiment of the present application.

According to an embodiment, the oscillator may comprise an inverting module, which may comprise an even number of inverters connected in series, the input of the inverting module may be coupled to the output node Z of the oscillator circuit. According to one embodiment, the inverting module may include an inverter 401 and an inverter 402 connected in series, with an output of the inverter 401 coupled to an input of the inverter 402, i.e., node X; the output end of the inverting module is a node Y.

Alternatively, according to an embodiment, the oscillator may further include a charge and discharge signal generation module, for example, may include an odd number of inverters connected in series in sequence. According to an embodiment, the charge and discharge signal generation block may include an inverter 403, an input terminal of which may be coupled to the output node Y of the inversion block.

According to one embodiment, the oscillator may further comprise a capacitive module coupled between the inverting module output and ground. According to one embodiment, the capacitive module may comprise, for example, a capacitor 404 and a capacitor 405, which are connected in series between the output node Y of the inverting module and ground, wherein a first terminal of the capacitor 404 is coupled to the output of the inverting module, a second terminal of the capacitor 405 is connected to ground, and a second terminal of the capacitor 404 is coupled to a first terminal of the capacitor 405, i.e. the output terminal node Z of the oscillator. According to one embodiment, the capacitance values of the capacitor 404 and the capacitor 405 may be the same.

According to one embodiment, the oscillator may further include a charging module and a discharging module.

According to an embodiment, the charging module may comprise a current source 406 and a switch 408 connected in series, a first terminal of the current source 406 being coupled to the power supply, a first terminal of the switch 408 being coupled to a second terminal of the current source 406, a second terminal of the switch 408 being coupled to a node between the capacitor 404 and the capacitor 405, i.e. the output terminal node Z of the oscillator. According to one embodiment, the charging module is configured to charge the capacitance 404 and the capacitance 405 in the capacitance module simultaneously.

According to one embodiment, the discharging module may include a switch 409 and a current source 407 connected in series in this order, wherein a first terminal of the current source 407 is coupled to a second terminal of the switch 409, and a second terminal thereof is grounded; a first terminal of switch 409 is coupled to oscillator circuit output terminal node Z, i.e. the node between capacitor 404 and capacitor 405. According to one embodiment, the discharge module may be configured to discharge the capacitance 404 and the capacitance 405 simultaneously.

According to one embodiment, the charging module and the discharging module are connected in series with each other in opposite conduction states, the discharging module being turned off when the charging module is turned on, and the discharging module being turned on when the charging module is turned off.

According to one embodiment, the switches 408 and 409 may be the same type of switch and the same control signal applies. Therefore, if the charging and discharging modules need to be in opposite conduction states, the charging and discharging signal generating module needs to be arranged, so that opposite control signals are provided for the charging and discharging modules. According to one embodiment, the charge and discharge signal generation module may include an odd number of inverters.

According to an embodiment, the charge-discharge signal generation module may be coupled between the output terminal of the inversion module and the control terminal of the charging module. For example, the switch 408 may operate under the control of the output signal of the charge and discharge signal generation module, e.g., the output of the inverter 403 may control the operating state of the switch 408, e.g., when the output of the inverter 403 is high, the switch 408 is turned on, otherwise it is turned off.

According to one embodiment, the output terminal of the inverting module may be coupled to the control terminal of the discharging module. For example, the switch 409 may operate under the control of the output signal of the inverting module, e.g., when the output of the inverter 402 is high, the switch 409 is on, otherwise it is off.

According to one embodiment, in the inverting module, the inverter 401 may be at the voltage V of the node Z_ZAs an input signal, with the voltage V of the node X_XAs an output signal, inverter 401 may be configured to couple to an input signal V_ZInverse amplification and/or shaping is performed.

According to one embodiment, in an inverting module, inverter 402 in series with inverter 401 is at voltage V at node X_XAs an input signal, with the voltage V of the node Y_YAs an output signal, inverter 402 may be configured to couple to an input signal V_XPerforming inverse amplification and/or shaping to output signal V_YMay be used to drive the first terminal of the capacitor 404 and to control the on and off of the switch 409.

According to one embodiment, the inverter 403 in the charge and discharge signal generation module is driven by the voltage V of the node Y_YAs an input, configured to couple to an input signal V_YIs inverted and the output signal of the inverter 403 is controlled to be onThe switch 408 is turned on and off to ensure that both the switch 408 and the switch 409 have one and only one of them in a conducting state at any one time.

In the capacitor module, the capacitor 404 and the capacitor 405 are charged by the P-type reference current source 406 or discharged by the N-type reference current source 407, and the charging operation is performed such that V is_ZThe voltage can be gradually increased, and the discharge operation makes V_ZGradually decreases. The presence of the capacitor 404 causes the oscillator output signal V_ZLet V be in the time of switching state_ZThe voltage jumps instantaneously to realize the relaxation function.

According to one embodiment, capacitor 405 is coupled to node Z at a first terminal and to ground at a second terminal. Introduction of capacitance 405 to V_ZVoltage is divided by instantaneous jump of variable, V_Z＝C₄₀₄/(C₄₀₄+C₄₀₅) VDD, C in proportion₄₀₄The smaller the jump, the smaller the jump amount, V_zThe more can be in the range of 0 to VDD so that V_ZMust be between 0 and the power supply voltage V_DDWithin the scope, the device type selection limitation or the limitation of a power supply voltage scheme caused by reliability risks caused by overvoltage is solved.

Fig. 5 is a schematic diagram illustrating an operating state of an oscillator circuit according to an embodiment of the present application.

According to one embodiment, the P-type and N-type reference current sources 408 and 409 have the same current value, which is labeled as I_REF。

According to one embodiment, the capacitance 404 and the capacitance 405 have the same value, and the capacitance value is labeled C.

Of course, the values of the capacitor 404 and the capacitor 405 may be different, and the values of the currents of the P-type and N-type reference current sources 408 and 409 may also be different. If not, the duty cycle of the output waveform is not 50%.

As shown in fig. 5, at t₀Time of day, V_XHigh level V_DD，V_Y、V_ZAre all low level, SW_NOff, SW_PConducting, and charging the series and parallel capacitors by the P-type reference current source; over time, V_ZGradually increasing.

When the time approaches t₁Time of day, V_ZGradually rise to approach V_DD/2 (inversion voltage of inverter 401), V_XStart to decrease, resulting in V_YStarts to rise, V, since the inverters (401, 402) have a large gain_YA sharp rise in the short time will result in V_ZAnd also rises sharply, creating a positive feedback effect.

At t₁Time of day, V_XAnd V_YRespectively jump to V rapidly_XAt a low level, V_YAt a high level V_DDDue to the voltage division between capacitors 404 and 405, V_ZThen from V_DDJump/2 to V_DDThe P-type and N-type switch states change accordingly, 409 becomes on, 408 becomes off, and the N-type reference current source 407 begins to discharge the capacitors 404 and 405.

Over time and the discharge operation proceeds, V_ZGradually decrease as time approaches t₂Time of day, V_ZGradually decreasing to approach V_DD/2 (inverter switching voltage), V_XInitially increased, resulting in V_YStarts to fall, V due to the larger gain of the inverter_YA sharp drop in a short time will result in V_ZAnd also drops sharply, forming a positive feedback effect.

At t₂Time of day, V_XAnd V_YRespectively jump to V rapidly_XAt a high level V_DD，V_YAt a low level, V is present due to the voltage division between the capacitors 404 and 405_ZThen from V_DDThe/2 transition to low level, the state of the P-type and N-type switches 408 and 409 changes accordingly, 409 turns off, 408 turns on, the P-type reference current source 406 starts to charge the capacitors 404 and 405, and the oscillator returns to the same state as t₀The same state at the same time; the oscillating state is repeated according to the above process.

According to one embodiment, the relationship between the oscillation period of the oscillator and various parameters in the oscillation circuit can be expressed as:

T＝2C×V_DD/I_REF

where C is the capacitance of the capacitor 404 or the capacitor 405, I_REFIs the current value of current source 406 or 407. Since the capacitance value C is affected little by the PVT conditions, the period of the oscillator is affected little by the PVT.

Fig. 6 is a schematic diagram of an oscillator circuit according to another embodiment of the present application. Most of which are similar to those shown in fig. 4, but the oscillator shown in fig. 6 does not include a charge and discharge control signal generation module. According to one embodiment, the charging module includes a P-type current source 606 and a PMOS transistor 608 connected in series between the power supply and the node Z, and the discharging module includes an NMOS transistor 609 and an N-type current source 607 connected in series between the node Z and ground. According to one embodiment, the PMOS transistor 608 and the NMOS transistor 609 are the same size and have opposite turn-on voltages. Therefore, the charging and discharging control signal generation module is not needed, the working states of the charging module and the discharging module can be controlled simultaneously by directly utilizing the output signal of the phase reversal module, and only one of the charging module and the discharging module is ensured to be switched on at the same time.

By using the conventional oscillator circuit provided by the present application, V can be converted into_ZVoltage is restricted to 0-V_DDWithin the range, the device type selection limitation or the limitation of a power supply voltage scheme caused by reliability risks caused by overvoltage are solved, and a proper load voltage is provided for the reference current source, so that the current of the whole current source working process is kept relatively constant.

In addition, it is more convenient to obtain the constant current to the analog chip, so that the capacitor is used for charging and discharging instead of the resistor, a main factor influencing the frequency accuracy is reduced, and the frequency accuracy of the oscillator is less influenced by PVT compared with the oscillator in the prior art without an additional calibration means.

The above-described embodiments are provided for illustrative purposes only and are not intended to be limiting, and various changes and modifications may be made by those skilled in the art without departing from the scope of the present disclosure, and therefore, all equivalent technical solutions should fall within the scope of the present disclosure.