阅读说明：本技术 一种eMMC芯片随机写入速率优化实现方法 (Random write rate optimization implementation method for eMMC chip ) 是由 樊凌雁 林伟 于 2021-06-24 设计创作，主要内容包括：本发明公开了一种eMMC芯片随机写入速率优化实现方法,包括以下步骤：S1,对eMMC芯片进行数据写入；S2,对写入方式进行判断；S3,如是随机写入,则写入额外配置区域；如是顺序写入,则写入用户区域；S4,根据映射关系表在数据前附加标签；S5,合并数据写入用户区域。本发明针对顺序写入占据大多数的数据传输方式,将随机写入合成顺序写入方式的做法能够有效地提高随机数据写入的速率。(The invention discloses a random write-in rate optimization realization method for an eMMC chip, which comprises the following steps: s1, writing data into the eMMC chip; s2, judging the writing mode; s3, if it is random writing, writing additional configuration area; if the writing is sequential writing, writing into the user area; s4, attaching a label before the data according to the mapping relation table; s5, the merged data is written in the user area. Aiming at the data transmission mode with most sequential writing, the method for combining the random writing into the sequential writing mode can effectively improve the random data writing speed.)

1. A random write rate optimization implementation method for an eMMC chip is characterized by comprising the following steps:

s1, writing data into the eMMC chip;

s2, judging the writing mode;

s3, if it is random writing, writing additional configuration area;

if the writing is sequential writing, writing into the user area;

s4, attaching a label before the data according to the mapping relation table;

s5, the merged data is written in the user area.

2. The method for implementing eMMC chip random write rate optimization according to claim 1, wherein the determining the write mode is specifically determining to write sequentially when the number of written data sectors is equal to or exceeds N; when the number of written data sectors is less than N, where N is 32, it is determined to be randomly written.

3. The method of claim 1, wherein each 4-byte logical address in the mapping table corresponds to a 4-byte physical address.

4. The method for implementing random write rate optimization for an eMMC chip according to claim 1, wherein the eMMC chip is divided into M regions, and wherein 1bit of data is used for sequential writing and random writing in each region.

5. The method for implementing random write rate optimization for the eMMC chip according to claim 4, wherein 1bit of data in each region indicates sequential writing when the data is 0 and indicates random writing when the data is 1.

6. The eMMC chip random write rate optimization implementation of claim 1, wherein the tag is 4KB in size.

7. The method of claim 1, wherein the tag comprises a logical address, a physical address, a number of data sectors, a number of tags, a tag flag, and a total parity bit in that order.

8. The method of claim 1, wherein the additional configuration area is configured as a sequence of tags and random data, and so on.

Technical Field

The invention belongs to the technical field of data storage, and relates to a random write-in rate optimization implementation method for an eMMC chip.

Background

In order to meet the requirement of mobility of electronic devices such as a tablet and a mobile phone, eMMC (Embedded multimedia controller) is born under the precondition of being light, thin and low in power consumption. Therefore, the eMMC interface is defined by the IO pin, so that the interface is simple and low in power consumption; in addition, the effect of the eMMC on apple iPad, android tablet computers and mobile phones is huge, and the tablet and the mobile phone are small, so that the eMMC packages a controller and NAND particles in a package, and the eMMC cannot contain many NAND particles and is low in capacity.

Summarizing the characteristics of the eMMC, such as low power consumption, small capacity and relatively poor random read-write performance;

as one of the data interaction modes of the chip, random reading and writing are mainly proposed relative to sequential reading and writing, which is understood from the literal sense, if the sequential reading and writing follows the sequence in the reading and writing process, the address of each data access request is continuous. Random reading and writing does not follow a fixed sequence, and data can be randomly switched to a certain position to be read and written when the data is read and written.

An analogy is made to the problem of random writing in a sequential writing manner. In short, if the sequentially written data are written from positions 1, 2, 3 and 4 sequentially, the addresses between the consecutive data are continuous, and the logical block address DirectEBA and the physical block address PhyEBA of the eMMC are equal, which results in a faster data transfer rate. However, in the random writing mode, the position of data writing is not fixed. For example, after the first data is written, the next data may be located at the first data address by one more step, and the next data may be written between the first data, which results in a very split between the data, and the DirectEBA and PhyEBA are not equal. Also because of address jumping and other problems with each write, the data writing rate is very slow, which is also a disadvantage of random writing and is more time consuming.

Disclosure of Invention

In order to solve the above problems, the present invention provides a method for implementing eMMC chip random write rate optimization, including the following steps:

s1, writing data into the eMMC chip;

s2, judging the writing mode;

s3, if it is random writing, writing additional configuration area;

if the writing is sequential writing, writing into the user area;

s4, attaching a label before the data according to the mapping relation table;

s5, the merged data is written in the user area.

Preferably, the determining the writing manner specifically determines to be sequential writing when the number of written data sectors is equal to or exceeds N; when the number of written data sectors is less than N, where N is 32, it is determined to be randomly written.

Preferably, each logical address of 4bytes in the mapping relation table corresponds to a physical address of 4 bytes.

Preferably, the eMMC chip is divided into M regions, and 1bit data represents sequential writing and random writing in each region.

Preferably, when the data of 1bit in each area is 0, the sequential writing is represented, and when the data of 1bit is 1, the random writing is represented.

Preferably, the tag is 4KB in size.

Preferably, the tag is composed of a logical address, a physical address, a data sector number, a tag flag, and a total check bit in sequence.

Preferably, the configuration of the additional configuration area is a tag and random data that are sequentially arranged, and so on.

The beneficial effects of the invention at least comprise:

1) in order to improve the speed of the eMMC chip in random data writing, the random data which are relatively split originally are combined into sequential continuous data to be written, so that a random writing mode with a relatively slow transmission speed originally has a relatively high transmission speed like sequential writing;

2) the relative position relation between random data provides a mapping relation from the logic EBA to the PhyEBA by adding Tag to ensure that the data finally written into the memory does not have a dislocation relation;

3) for the data transmission mode with most sequential writing, the method of combining random writing into sequential writing mode can effectively increase the random data writing speed.

Drawings

Fig. 1 is a schematic diagram of data arrangement of an eMMC chip random write rate optimization implementation method according to an embodiment of the present invention;

fig. 2 is a flowchart illustrating a method for implementing eMMC chip random write rate optimization according to an embodiment of the present invention;

fig. 3 is a schematic diagram of sequential write and random write of an eMMC chip random write rate optimization implementation method according to an embodiment of the present invention;

fig. 4 is a mapping relationship representation intention of the eMMC chip random write rate optimization implementation method according to the embodiment of the present invention;

fig. 5 is a schematic diagram illustrating a tag configuration of an eMMC chip random write rate optimization implementation method according to an embodiment of the present invention;

fig. 6 is a random write comparison diagram of a random write rate optimization implementation method for an eMMC chip according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

On the contrary, the invention is intended to cover alternatives, modifications, equivalents and alternatives which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, certain specific details are set forth in order to provide a better understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details.

Referring to fig. 1, as can be seen from the eMMC data arrangement, there is a normal User Area and a Fixed extra configured Fixed OP (over provisioning) in the eMMC, and generally, a position where a User normally views data is located at the User Area.

The optimization idea of the invention is to write the data to be written randomly into the OP area in a sequential writing manner to be combined in a sequential manner, and finally to merge the data into the user area under the idle condition of the hardware.

Referring to fig. 2, a flow chart of the method of the present invention is shown, which comprises: s1, writing data into the eMMC chip;

s2, judging the writing mode;

s3, if it is random writing, writing additional configuration area;

if the writing is sequential writing, writing into the user area;

s4, attaching a label before the data according to the mapping relation table;

s5, the merged data is written in the user area.

Referring to fig. 3, illustrated is eMMC0 connected by channel 0: the set judgment condition of sequential writing and random writing is that when the sector (data sector) needing to be written is 512 bytes, the written data is considered to be sequential when the number of sectors is equal to or more than 32, and when the number of sectors is less than 32, the data is considered to be random writing and is used for simulating the conditions of sequential writing and random writing. LBA is called Logic Block Address in English, and is the same as DirectEBA in Logic Block Address, but there is a difference between the two. Taking fig. 1 as an example, in the data writing process, in order to equalize data writing, a plurality of channels are used to write to different EMMCs, and therefore, it is necessary to perform switching to different channels after writing a block of a certain size. The LBA is a logical block address of data in multiple channels, and the DirectEBA is a logical block header address of data written in a channel, for example, channel 0.

It can be seen that, in fig. 3, when the LBA is 32, the number of sector counts corresponding to the size of sector data of 64k is 128, because the size of a single sector is 512 bytes, where 64k actually refers to the total size of sectors, and 1k of data is equivalent to two sector counts, and the basis for determining whether there is random data is the number of sector counts, that is, whether the sector count is greater than 32, so the number of sectors is 128. In addition, the sector size of sector with 64k size is chosen here for illustration only, and it is a sequential write because it is set larger than the value related to the random and sequential write threshold, and it is sufficient to write data directly to the corresponding LBA position of User Area, because DirectEBA and PhyEBA are the same at the time of sequential write, and LBA is 34 at the second time, but since the number of sectors is 4, it is a random write, in which case we write data to the OP Area, i.e. the extra allocation Area. It should be noted that since the LBA is 34, for the same DirectEBA, the previous 32 and 33 data and a part of the following data are still missing, so that the remaining data needs to be copied from the User Area to the OP Area, which ensures that the data of the OP Area is the latest valid data. The third writing is similar to the second writing, and data is added after the second writing, so that the random data are ensured to be sequential in the OP area.

See fig. 4 for a schematic diagram of the Mapping relationship between DirectEBA and PhyEBA in Mapping Table, how to ensure that the order of the random data written back to User Area is correct? Therefore, there is a general Mapping Table for providing the location relationship between DirectEBA and PhyEBA. DirectEBA and PhyEBA are equal for sequential writing, but not for random writing.

It can be seen that the representation of addresses requires 4bytes in order to reduce the size of the mapping table. We divide the whole eMMC into 32 Region regions, which varies depending on the selected eMMC's own capacity, and take a 256G disc with 4 emmcs as an example, the capacity of a single eMMC is 64G, so each Region is 2G after being divided into 32 regions, each Region uses only bit0 to indicate that the Region is sequentially written, bit1 indicates that the Region is randomly written, so for those cases where the sequential writing is most and the random writing indicates less, for the Mapping relationship of sequential writing, we only need to replace the original 4bytes with 1-bit data 0, and for the Mapping relationship of sequential writing, after random writing, we find the Mapping Table (the composition of Mapping Table is as described in fig. 4, each eMMC logical address of 4bytes corresponds to an eMMC physical address of 4bytes, and the complete mapping table is formed by a series of mapping relation groups. The method and the device ensure that when data are written, the data are written into the correct physical address position through the eMMC logical address by means of the mapping table. ) The table look-up efficiency can be effectively improved by the method.

And, next, most critical. The random data written in the OP area needs to be provided with necessary DirectEBA information, as described above, for random writing, the DirectEBA and PhyEBA of the random writing are not equal, so a mapping relation table is needed, and only this part of information is added to ensure that the mapping relation between the DirectEBA and PhyEBA of the random writing data is not lost in case of power failure, thereby ensuring that the random data can be correctly written back to the original logic block position of the eMMC.

See fig. 5 for Tag and its composition for randomly written data. The 4 parts of the content can be actually regarded as two parts because the series of the 4 parts of the content is composed of a random Write Tag with the size of 4KB and a group of random data, so that the rear part and a part of the content are actually the same concept as the front part, except that the specific content of the rear Tag and the random data are not consistent with the front part.

Then, with respect to Random Write Tag, his constituent content is the portion of the landscape Tag that is displayed. The total size is 4 KB. The components are as follows in sequence: 1) DirectEBA is the logical address of eMMC, 2) PhyEBA is the physical address of eMMC, 3) Sector Count is, as mentioned above, the number of Sector counts in the SATA command that is written, and it is also proved that the data that is subsequently sent includes random data (the number is larger than the threshold of 32), 4) Tag Count is to ensure that the front and back relationship between the random data that are sequentially concatenated is not disturbed, because the random data are written in a serial form, the data that is later should be added instead of covering the data that is earlier, so the difference of Tag can also see the precedence relationship of the random data, 5) Tag Flag and CheckSum are to ensure the correctness of the data when writing, because various interferences can cause the problem of error of the written data when any data is written, data is misplaced or 1 is written to 0, 0 is written to 1, these all result in data write errors, and the CheckSum is an additional check bit to provide a check when the write data is erroneous.

Then is the Data of Random Cmd, which is the Random Data that needs to be written sequentially in series.

Referring to OP Area in fig. 5, it is necessary to add a Tag to the written data before writing random data each time, and the Tag records mapping information about random writing. This ensures that the data content ultimately stored in the User Area is guaranteed to be free from misalignment, although the information that needs to be written randomly is written sequentially by combining them together. It should be noted that before writing, trim (erase) is required for the OP area, and the random writing mode after optimization is shown in fig. 6.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.